JPH11234247A - Fm multiplex broadcasting receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FM multiplex broadcasting receiver capable of improving the error correction capability of data. SOLUTION: In order to extract multiplexed data contained in FM multiplex broadcasting, an FM multiplex broadcasting receiver 1 is provided with a front end 12, intermediate amplification/FM detection circuit 14, filtering circuit 16, LMSK demodulation circuit 18, error detection and correction circuit 22, memories 23 and 26, CPU 24 and tuner circuit 30. Concerning data consisting of one frame, the (first) lateral correction, longitudinal correction and (second) lateral correction for the unit of a block are performed but concerning the block with which the proper corrected result can be provided in the first lateral correction but any error is caused in the second lateral correction, data provided by the first lateral correction are used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an FM multiplex broadcast receiver for receiving an FM multiplex broadcast in which various data are multiplexed.

[0002]

2. Description of the Related Art In recent years, a road traffic information communication system (VICS) that provides various information such as traffic congestion and traffic regulation to vehicles by FM multiplex broadcasting, and text information such as news and weather forecasts are provided by FM multiplex broadcasting. So-called “visible radio”
Has been put to practical use. The user can obtain a desired service screen by selecting a program. VICS-compatible FM multiplex broadcast receivers are often used in combination with an in-vehicle navigation device having a display device, and an FM multiplex broadcast receiver compatible with “visible radio” is generally combined with an in-vehicle navigation device. In addition, it is used as a single portable receiver.

[0003]

By the way, the above-mentioned F
Since the M multiplex broadcast receiver is often used while moving, and is sometimes used in a weak electric field area, the multiplexed data after demodulation may include an error. Therefore, in order to correct this data error after demodulation, redundant bits for error correction are added in advance on the transmission side. FM using DARC (DataRadio Channel) method
In multiplex broadcasting, data error correction is performed by (272,
190) This is performed by a product code using a shortened difference set cyclic code vertically and horizontally. Specifically, after performing horizontal error correction (hereinafter referred to as first horizontal correction) on a received frame, vertical error correction (hereinafter referred to as vertical correction) is performed, and horizontal error correction is performed again. (Hereinafter referred to as second horizontal correction). Here, the horizontal error correction refers to error correction performed in units of each block constituting a frame,
Vertical error correction refers to frame-based error correction in which bits at the same position in a plurality of blocks are grouped.

As described above, according to the correction method that combines the first horizontal correction, the vertical correction, and the second horizontal correction, correction can be performed with high probability, but errors such as data bursts occur over a wide range, and a plurality of errors occur. If such blocks are continuously missing, there is a risk that they will be incorrectly corrected by vertical correction. That is, in the vertical correction, since the bits at the same position in a plurality of blocks are collectively subjected to error correction, when a plurality of block data cannot be continuously received due to an error, the missing block data is deleted. Due to the influence, block data having no signal error or block data that has been correctly corrected by the first horizontal correction may be erroneously corrected.

FIG. 6 is a diagram showing the number of error blocks (blocks that could not be corrected) after the first horizontal correction and the number of error blocks after the second horizontal correction of each frame received by the conventional FM multiplex broadcasting receiver. It is. Originally, most of the error blocks after the first horizontal correction are correctly corrected by the subsequent vertical correction and the second horizontal correction, so the number of error blocks after the completion of the second horizontal correction is:
This should be less than the number of error blocks after the first horizontal correction. However, as shown in FIG. 6, there are frames in which the number of error blocks after the second horizontal correction is larger than the number of error blocks after the first horizontal correction (shown in FIG. 6). This is because blocks having no error that do not need to be corrected by the vertical correction have been erroneously corrected, and the number of blocks that cannot be corrected by the second horizontal correction has increased. As described above, the conventional FM multiplex broadcast receiver has a problem that data errors may increase when vertical correction is originally performed to increase the possibility of correction.

[0006] The present invention has been made in view of the above points, and an object of the present invention is to provide an FM multiplex broadcast receiver capable of improving the data error correction capability.

[0007]

In order to solve the above-mentioned problems, an FM multiplex broadcasting receiver according to the present invention demodulates multiplexed data included in FM multiplex broadcasting to extract data of a frame composed of a plurality of blocks. However, when performing the error correction processing a plurality of times on the extracted data, it is a case where there is no error in the first data after the previously performed error correction, and If an error occurs in the second data after the error correction performed later, the first data is selected instead of the second data. Therefore, when the erroneous correction is performed on the first data having no error, the original first data is used to select the correct one of the first data and the second data and to correct the corrected data. Therefore, the error correction capability of data can be improved.

In particular, when the first data is selected in place of the second data, a case where the first data is selected in a block unit and a case where the first data is selected in a frame unit are considered. In the case of a block unit, since correct data can be selected in a small unit, the data correction ability can be further enhanced. In the case of a frame unit, the entire frame data may be replaced, so that the processing can be simplified.

The plurality of error correction processes described above include a first correction process performed on a block basis and a frame correction on data existing at the same position in each block after the first correction process is completed. A second correction process performed in
It is preferable to include a third correction process that is performed in block units again after the second correction process is completed. Even if the error-free block data is obtained after the first correction processing is completed, the error correction may be performed by the next second correction processing. When the erroneous block data is obtained after the completion of the error correction processing, the error correction capability can be improved by using the error-free block data obtained by the first correction processing.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is shown in FIG.
When receiving an FM multiplex broadcast including VICS data or the like using the DARC method, the M multiplex broadcast receiver stores the data after the first horizontal correction if it is correct, and stores the data after the second horizontal correction. If an error occurs due to the error, it is characterized in that the stored correct data by the first horizontal correction is used. Hereinafter, an FM multiplex broadcast receiver according to an embodiment will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.
It is a figure showing the composition of M multiplex broadcast receiver. F shown in FIG.
The M multiplex broadcast receiver 1 demodulates and stores FM multiplex data from the FM broadcast signal received by the antenna 10,
Front end (F / E) 12, intermediate frequency amplification / FM detection circuit (IF / DET) 14, filter circuit 16, LM
SK (Level controlled Minimum Shift Keying) demodulation circuit 18, synchronization circuit 20, error detection and correction circuit 22, CP
U24, memories 23 and 26, and a tuning circuit 30 are included. Also, this FM multiplex broadcast receiver 1
Input / output interface (IF) for performing various data communications with the navigation device 2 connected to the outside
A section 28 is provided.

The front end 12 includes an antenna tuning circuit, a high-frequency amplifier circuit, a local oscillator circuit, a mixing circuit, etc., performs high-frequency amplification on an FM broadcast signal input from the antenna 10 and performs predetermined frequency conversion. Do.
For example, when an FM broadcast signal of a desired frequency to be received is input to the front end 12, it is converted to an intermediate frequency signal of 10.7 MHz. The intermediate frequency amplification / FM detection circuit 14 amplifies the intermediate frequency signal output from the front end 12, performs a tuning operation, and performs FM detection processing on the tuning result. Filter circuit 1
Reference numeral 6 is for separating a multiplex signal included in the signal after the FM detection. When considering FM multiplex broadcasting using the DARC method, as shown in FIG. 2, a signal after FM detection includes a multiplex signal of about 76 kHz, and only this signal component is extracted by the filter circuit 16. Is done.

The LMSK demodulation circuit 18 includes a filter circuit 1
The delay detection is performed on the LMSK modulation signal output from 6 to reproduce the bit clock and demodulate the bit data sequence. The synchronization circuit 20 detects the block synchronization and the frame synchronization with respect to the bit data string output from the LMSK demodulation circuit 18, and includes an error detection and correction circuit 22.
, CR is applied to this synchronized bit data sequence.
An error is detected by a C (Cyclic Redundancy Check) code, and if an error is detected, the error is corrected using the parity. For example, error correction is (272, 19
0) The error correction is performed in the order of the first horizontal correction, the vertical correction, and the second horizontal correction by the product code using the shortened difference set cyclic code in the vertical and horizontal double. After the first horizontal correction and the second horizontal correction, error detection is performed again by CRC, and a block including a bit data string having an error is determined as an error block. The memory 23 is used as a work area of the error detection and correction circuit 22.

The CPU 24 controls the FM multiplex broadcast receiver 1
Is set for the FM multiplex broadcast including the desired multiplexed data, and the data (data packet) output from the error detection and correction circuit 22 is edited to create various data of a higher hierarchical level. The memory 26 is partially CP
U24 is used as a work area, and another part is
4 is used as a storage area for the various data created by step 4. Further, the memory 26 stores a data packet in which no data error has occurred after the first horizontal correction.

The tuning circuit 30 is for setting the receiving frequency of the FM multiplex broadcasting receiver 1, and forms a PLL (phase locked loop) together with a local oscillation circuit in the front end 12. For example, it has a frequency dividing circuit composed of a programmable counter, and by changing the frequency dividing ratio according to an instruction from the CPU 24, the front end 1
The reception frequency is switched by changing the oscillation frequency of the local oscillation circuit in 2.

Next, a part of the hierarchical structure of the FM multiplex broadcasting using the DARC system will be briefly described. F mentioned above
The hierarchical structure of the DARC to be processed by the M multiplex broadcast receiver 1 includes a layer 1 for a transmission path, a layer 2 for error correction, and the like.

Layer 1 of the transmission line corresponds to the signal after FM detection (baseband signal) output from the above-described intermediate frequency amplification / FM detection circuit 14. As shown in FIG. 2, the signal after FM detection has an FM of about 76 kHz.
A multiplexed signal is included, and only this FM multiplexed signal is separated by the filter circuit 16 and the LMSK demodulation circuit 18
Through which the FM corresponding to this FM multiplex broadcast signal
Multiple data is obtained.

Layer 2 for error correction shows a frame structure for performing error detection and error correction. FIG.
3 is a diagram showing a frame structure corresponding to layer 2. FIG. As shown in the drawing, the FM multiplex broadcast data output from the LMSK demodulation circuit 18 is composed of a total of 272 blocks per frame, of which 190 blocks are blocks containing data packets, and the remaining 82 blocks are parity packets. It is a block containing. These 82 blocks are distributed among blocks including data packets. Various multiplexed data such as VICS data are transmitted using data packets included in 190 blocks in one frame shown in FIG.

The synchronization circuit 20 includes a block identification code BIC (Block Identify Code) included in the head of each block.
Block synchronization and frame synchronization are achieved by detecting e). Further, the error detection and correction circuit 22 detects an error of each bit data constituting the data packet based on a CRC included in each block, and when an error is detected, corrects the error using a parity packet or parity. Do. Specifically, in a block including a data packet, data error detection is performed using a 14-bit CRC, and if an error is detected, the first horizontal correction or the second horizontal correction is performed using an 82-bit parity. Corrections are made. When the frame shown in FIG. 3 is viewed in the vertical direction, the 190-bit data obtained by collecting the bits of the 190 data packets by using the 82-bit parity obtained by collecting the bits of the 82 parity packets. Is corrected vertically.

The above-mentioned LMSK demodulation circuit 18 corresponds to data demodulation means, the error detection and correction circuit 22 corresponds to error correction means, and the error detection and correction circuit 22 and the memory 23 correspond to data selection means. The first horizontal correction corresponds to the first correction processing, the vertical correction corresponds to the second correction processing, and the second horizontal correction corresponds to the third correction processing.

The FM multiplex broadcast receiver of the present embodiment has such a configuration, and its operation will be described next. FIG.
Is a flowchart showing an operation procedure of the FM multiplex broadcast receiver of the present embodiment, for example, an operation procedure in a case where VICS data is received as multiplexed data.

An instruction is sent from the CPU 24 to the channel selection circuit 30 to set the reception frequency to the frequency of the FM broadcast in which the VICS data is multiplexed, thereby obtaining the VICS
The reception of the FM multiplex broadcast including the data is started (step 100).

When an FM multiplex broadcast including VICS data is received, an intermediate frequency amplification / FM detection circuit (IF / D
ET) 14, filter circuit 16, LMSK (Level cont
When a bit data string corresponding to the VICS data is created through the demodulation circuit 18 and the synchronization circuit 20 synchronizes the block and the frame, the error detection and correction circuit 22 starts to operate as shown in FIG.
(Step 10)
1).

Next, the error detection and correction circuit 22 detects an error in each data packet based on the CRC in each block containing the data packet (step 102).
If there is an error in the data packet, the error detection and correction circuit 22 performs the first horizontal correction on the data packet and the CRC based on the parity in the block including the data packet (step 104). After the completion of the first horizontal correction, the error detection and correction circuit 22 performs error detection of the data packet by the CRC again (step 10).
5) Store the data packet in which no error was detected, that is, the data packet that did not need to be corrected by the first horizontal correction and the data packet that was correctly corrected by the first horizontal correction in the memory 23 (step 10).
6).

FIG. 5 shows the state of the memory 2 after the completion of the first horizontal correction.
FIG. 3 is a diagram illustrating an example of a data packet stored in No. 3;
For example, in step 105, data packets 2 and 6
Is detected, each data of the data packets other than these data packets is stored in the memory 23 together with the data packet number, as shown in FIG.

Next, the error detection and correction circuit 22 uses the 82 parity packets in the frame shown in FIG.
Vertical correction is performed on the 90 data packets and the corresponding CRCs (step 107). When the vertical correction is completed, the error detection and correction circuit 22 performs the second horizontal correction on the data packet and the CRC based on the parity in each block including the data packet (step 108). After the second horizontal correction is completed, the error detection and correction circuit 22 performs error detection of the data packet by using the CRC (step 109), and determines whether or not there is a data packet in which an error has been detected (step 110).

If there is a data packet in which an error has been detected, the error detection and correction circuit 22 determines whether a data packet having the same packet number as the data packet in which the error has been detected is stored in the memory 23, It is determined whether there is a data packet having no error immediately after the first horizontal correction among the data packets having an error after the second horizontal correction (step 111). Read the data packet
A process of replacing the data block with an error caused by the second correction is performed (step 112).

Next, the error detection and correction circuit 22 outputs each corrected data packet constituting the frame,
24 stores these data packets in the memory 26 (step 113). Each data packet output from the error detection and correction circuit 22 in this way includes a data packet in which no error was detected immediately after the first horizontal correction replaced in step 112.

In the error detection before the first horizontal correction in step 102 described above, if all data packets included in the frame have no error (if a negative determination is made in step 103), step 104 Each data packet is output from the error detection / correction circuit 22 without performing
Is stored in Alternatively, when the second horizontal correction is completed, there is no error in all data packets included in the frame (when a negative determination is made in step 110), or when an error occurs in the second horizontal correction, An error is detected in the data packet of the number even after the first horizontal correction, and the corresponding data packet is stored in the memory 23.
If the data packet is not stored in the error detection / correction circuit 22 (ie, if the determination in step 111 is negative), the data packet is output from the error detection and correction circuit 22 and stored in the memory 26 without performing the data packet replacement process in step 112. You.

Thereafter, the CPU 24 creates various data of the hierarchy 3 or a higher hierarchy based on each data packet stored in the memory 26.

As described above, a data packet in which no error has occurred after the first horizontal correction is stored, and if an error occurs after the vertical correction and the horizontal correction twice, the stored horizontal one is stored. By replacing the data packet with an error-free data packet immediately after the second correction, the error correction capability of the data can be improved. In particular, as shown in FIG.
When the number of errors increases after the second correction, the number of error blocks tends to increase sharply.
If the data packet immediately after the second correction can be used, the number of error blocks can be greatly reduced, and the reliability of the received multiplexed data can be greatly increased.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiment, as a result of performing the first horizontal correction by the error detection and correction circuit 22,
The data of the block in which no error was detected is stored in the memory 23.
However, data for one frame may be stored in the memory 23 regardless of the presence or absence of an error. When storing one frame, the capacity of the memory 23 is 288 bits (one block) × 272 (1
(Number of blocks in frame) = 78336 bits = 9792
You need bytes.

In the above-described embodiment, the data is replaced in block units. However, the data after the first horizontal correction is stored in the memory 23 for one frame, and the data after the second horizontal correction is stored. If the data error is greater than the data error after the first horizontal correction, the data of one frame stored in the memory 23 after the first horizontal correction is completed may be read and used. As shown in FIG. 6, when the number of data errors increases after the second horizontal correction, the number of error blocks increases extremely. Even if the entire data for one frame is replaced, the number of data errors significantly increases. Can be reduced.

In the above-described embodiment, the storage of the data after the first horizontal correction by the error detection and correction circuit 22 or
Although the data after the second horizontal correction is replaced, the CPU 24 may perform these processes. For example, the horizontal 1 output from the error detection and correction circuit 22
The error-free data packet after the second correction is stored in the memory 26 by the CPU 24, and when the frame data after the second horizontal correction is output from the error detection and correction circuit 22,
The erroneous data packet contained therein is stored in the memory 26.
The CPU 24 performs a process of appropriately replacing the data packet with an error-free data packet stored in the.

In the above-described embodiment, the case where VICS data is received has been described. However, the present invention can be similarly applied to the case where other multiplexed data such as teletext is received.

[0036]

As described above, according to the present invention, when error correction processing is performed a plurality of times on data of a frame composed of a plurality of blocks, the first error correction after the first error correction is performed.
In the case where there is no error in the data of the first data and the error occurs in the second data after error correction performed later on the first data, the first data is replaced with the first data. Is selected, the correct one of the first data and the second data can be selected as corrected data, and the error correction capability of the data can be improved.

In particular, when the first data is selected in place of the second data, correct data can be selected in small units to further enhance the data correction capability by using a block unit. By using the unit, the processing can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an FM multiplex broadcast receiver according to an embodiment.

FIG. 2 is a diagram illustrating a transmission path signal of a layer 1;

FIG. 3 is a diagram showing a frame structure corresponding to layer 2;

FIG. 4 is a flowchart showing an operation procedure of the FM multiplex broadcast receiver of the embodiment.

FIG. 5 is a diagram showing an example of a data packet stored in a memory after the first horizontal correction.

FIG. 6 shows the number of error blocks and the horizontal 2 after the first horizontal correction of each frame received by the conventional FM multiplex broadcasting receiver.
FIG. 14 is a diagram illustrating the number of error blocks after the second correction.

[Explanation of symbols]

 Reference Signs List 1 FM multiplex broadcast receiver 2 Navigation device 12 Front end (F / E) 14 Intermediate frequency amplification / FM detection circuit (IF / DET) 16 Filter circuit 18 LMSK demodulation circuit 20 Synchronization circuit 22 Error detection and correction circuit 23, 26 Memory 24 CPU 28 input / output interface (IF) 30 channel selection circuit

Claims (4)

[Claims] 1. A data demodulator for demodulating multiplexed data included in FM multiplex broadcasting to extract data of a frame composed of a plurality of blocks, and performing error correction processing on the data extracted by the data demodulator a plurality of times. Error correcting means for performing error correction on the first data after the error correction performed earlier and without error in the second data after error correction performed on the first data. And a data selecting means for selecting the first data in place of the second data when the error occurs. 2. The FM multiplex broadcast receiver according to claim 1, wherein the data selection means selects the first and second data in block units. 3. The FM multiplex broadcast receiver according to claim 1, wherein said data selection means selects said first and second data in frame units. 4. The error correction process according to claim 1, wherein the plurality of error correction processes performed by the error correction unit include a first correction process performed on a block-by-block basis and a first correction process performed on a block-by-block basis. After the end of the second correction process performed on a frame basis for data existing at the same position in each block, and a third correction process performed on a block basis after the second correction process is completed. Wherein the data selecting means selects one of the first data obtained by the first correction processing and the second data obtained by the third correction processing. FM multiplex broadcast receiver.