JPH11233644A - Semiconductor integrated circuit and its manufacturing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a polysilicon region having a higher or a high resistance rate which is suitable for producing a resistance element, by suppressing an increase of process steps in a manufacturing process of a semiconductor integrated circuit, and also by suppressing the increase in the kinds of masks used for the manufacturing process. SOLUTION: Regions A1 and A2 are of low resistance rate, and each region is of P<+> polysilicon gate or N<+> poly-silicon gate. A region A3 is one for producing a resistance element. First, a low density ion is implanted on the whole surface of regions A1-A3. Next, a P<+> impurity ion is implanted to the area A1 by mask covering with regions A2 and A3. Also, N<+> impurity ions are implanted to the region A2 by mask covering with regions A1 and A3. Then, the region A3 covered with any mask becomes an impurity region of low density, having a high resistance rate, suitable for producing the resistance element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a dual gate CMOS having both a P + polysilicon gate and an N + polysilicon gate, and a method of manufacturing the same. While suppressing the increase in the number, and while suppressing the increase in the type of mask used in the manufacturing process, it is suitable for producing a resistance element,
The present invention relates to a semiconductor integrated circuit capable of forming a polysilicon region having a higher or higher resistivity and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a resistance element in a semiconductor integrated circuit is generally made of polysilicon. This polysilicon is, for example, MOS (metal oxide semiconduc
It is optimized for digital MOS, such as a tor) gate, and has a low resistivity.

[0003]

Therefore, since the resistance is low, when a resistive element is formed, it takes a long time to obtain a necessary resistance value, which consumes a large area of the integrated circuit. For this reason, the analog cell has become large.

[0004] In addition, since a resistance element of polysilicon has a small variation in resistance value, it is indispensable for a high precision analog cell. Therefore, if an attempt is made to reduce the integrated circuit area in an analog cell, it is necessary to reduce the size of the polysilicon resistance element.

[0005] Here, the resistivity of polysilicon is high when the impurity concentration is low, and the resistivity decreases as the impurity concentration increases. Therefore, polysilicon having a high impurity concentration and a low resistivity for digital MOS, such as a wiring and a gate of a MOS, and polysilicon having a low impurity concentration and a high resistivity for forming a resistance element are both integrated into one semiconductor. It is conceivable to build it into a circuit. However, this causes a problem that the number of manufacturing steps of the semiconductor integrated circuit increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and suppresses an increase in the number of steps in the manufacturing process of a semiconductor integrated circuit and an increase in the number of types of masks used in the manufacturing process. It is an object of the present invention to provide a semiconductor integrated circuit capable of forming a region with a higher or higher resistivity suitable for forming a resistance element and a method for manufacturing the same.

[0007]

First, a semiconductor integrated circuit according to a first invention of the present application is a dual gate CMOS having both a P + polysilicon gate and an N + polysilicon gate.
In the semiconductor integrated circuit in which the impurity element is formed, the resistance element is formed in the polysilicon region having a lower impurity concentration than the region in which the P + polysilicon gate is formed and the region in which the N + polysilicon gate is formed. This has solved the above-mentioned problem.

In the semiconductor integrated circuit, the P
A semiconductor in which a titanium silicide film is formed on at least a part of an upper surface of a + polysilicon gate and an upper surface of the N + polysilicon gate, and a titanium silicide film is not formed on an upper surface of the resistance element By forming an integrated circuit, the present invention can be applied to a semiconductor integrated circuit using a titanium silicide film.

Next, a method for manufacturing a semiconductor integrated circuit according to a second invention of the present application is a method for manufacturing a semiconductor integrated circuit incorporating a dual gate CMOS having both a P + polysilicon gate and an N + polysilicon gate. In addition, low concentration impurity ion implantation is first performed on the silicon substrate in the entire region where the P + polysilicon gate and the N + polysilicon gate are formed, and thereafter, the high concentration impurity for forming the P + polysilicon gate is formed. P
At the time of + impurity ion implantation and high-concentration N + impurity ion implantation for forming the N + polysilicon gate, each ion implantation mask covers at least a part of the region for forming the resistance element. This has solved the problem.

In the method for manufacturing a semiconductor integrated circuit, when a titanium silicide film is formed on the upper surface of the P + polysilicon gate and the N + polysilicon gate, the titanium silicide film is formed before the film formation and the low concentration impurity is formed. After the ion implantation, a titanium silicide film is used by forming an oxide insulating film for preventing a titanium silicide film from being formed so as to cover at least a part of a region where the resistance element is formed. The present invention can be applied to a method for manufacturing a semiconductor integrated circuit.

Hereinafter, the operation of the present invention will be briefly described.

Attention is directed to a semiconductor integrated circuit that has built a dual gate CMOS having both a P + polysilicon gate and an N + polysilicon gate.
In the polysilicon process, a P + polysilicon gate and an N + polysilicon gate are separately formed by using dedicated masks.

Here, "P +" is a region to which a P-type impurity is added at a higher concentration. "N +"
This is a region in which N-type impurities are added at a higher concentration. Further, “P−” is a region to which a P-type impurity is added at a lower concentration. “N−” is a region to which an N-type impurity is added at a lower concentration.

In the silicon substrate of the present invention, first, low-concentration impurity ions are implanted into the entire region where the P + polysilicon gate and the N + polysilicon gate are formed, in addition to the region where the resistance element is formed. Do. This low concentration ion may be P- or N-.

Thereafter, in order to form a P + polysilicon gate, high concentration P + impurity ions are implanted only in that region by using the ion implantation mask. or,
In order to form an N + polysilicon gate, high-concentration N + impurity ions are implanted only in that region using the ion implantation mask.

In the present invention, any of these ion implantations may be performed first. Further, these ion implantation masks cover at least a part of a region where the resistance element is formed. In the present invention, as a method for adding an impurity, other than the ion implantation method, any other method using a mask can be used.

In this manner, the region covered by the mask for implanting P + impurity ions and the mask for implanting N + impurity ions is not subjected to any high-concentration ion implantation. Therefore, since only the low concentration impurity ion implantation already performed is performed, the resistivity is high. Therefore, it is suitable for forming a resistance element.

For example, in FIG. 1, the area A1 is P +
It is a P + impurity ion implanted region for forming a polysilicon gate and the like. The region A2 is an N + impurity ion implantation region for forming an N + polysilicon gate and the like.
The region A3 is a low-concentration impurity region for forming a resistance element or the like.

In the method for manufacturing a semiconductor integrated circuit according to the present invention,
First, low concentration ions are implanted into the entire regions A1 to A3. Thereafter, at the time of P + impurity ion implantation, the mask covers the regions A2 and A3. During N + impurity ion implantation, the mask covers regions A1 and A3.
Then, the region A3 covered with any of the masks becomes a region of low-concentration impurities, has a high resistivity, and is a region suitable for forming a resistance element.

In the present invention described above, it is necessary to first perform a low concentration impurity ion implantation process on the silicon substrate before the P + impurity ion implantation and the N + impurity ion implantation. However, there are cases where such a manufacturing process already exists. In some cases, it is only necessary to change the order of the manufacturing steps. In any case, the number of manufacturing steps to be added in the present invention is, at most, only the addition of a manufacturing step of low-concentration impurity ion implantation.

In the present invention, it is necessary that the mask for implanting the P + impurity ions covers a high resistivity region for forming the resistance element. Further, it is necessary that the mask for implanting the N + impurity ions covers a region having a high resistivity in which the resistive element is formed. However, the number (type) of required masks does not increase.

As described above, according to the present invention, it is possible to suppress the increase in the number of steps in the manufacturing process of a semiconductor integrated circuit, and to suppress the increase in the number of types of masks used in the manufacturing process. , A polysilicon region having a higher resistivity or a higher resistivity can be formed.

In the present invention, it may be desirable that the resistivity of polysilicon forming the resistance element is low, such as when a resistance element having a low resistance value is formed. In this case, P + impurity ion implantation or N
+ Impurity ion implantation may be performed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 2 to 6 are sectional views showing a method of manufacturing the semiconductor integrated circuit according to the first embodiment to which the present invention is applied.

This embodiment is a dual gate CM having a P + polysilicon gate and an N + polysilicon gate.
This is a method for manufacturing a semiconductor integrated circuit incorporating an OS.
FIGS. 2 to 6 show cross sections of the semiconductor integrated circuit in each step in the order of steps and in each step, thereby showing what is performed in the manufacturing step in order.
Further, in the present embodiment, and in a second embodiment to be described later, a cross-sectional view shown in a series
Corresponds to a BB section.

First, when polysilicon 10 is deposited on the upper surface of the silicon substrate 1, the result is as shown in FIG. When N-impurity ion implantation (low-concentration impurity ion implantation) is performed from the upper surface of the polysilicon 10, the cross section becomes as shown in FIG. Note that, in FIG. 3 and similarly in FIG. 4 and other drawings, arrows “N−”, “N +”,
“P +” schematically illustrates ion implantation.

FIG. 4 shows a cross section of a state after a photoresist 12 is formed on the upper surface of the polysilicon 10 by using a mask dedicated to the ion implantation, and high concentration N + impurity ions are implanted. In FIG. 5, after the photoresist 12 of FIG. 4 is removed, a photoresist 14 is formed on the upper surface of the polysilicon 10 using the mask dedicated to the ion implantation, and a cross section of the state after the high-concentration P + impurity ion implantation is performed. Is shown. In FIG. 6, the N + polysilicon gate 22, the P + polysilicon gate 24, and the resistance element 26
Are formed.

As described above, in a semiconductor integrated circuit in which a dual gate CMOS having both a P + polysilicon gate and an N + polysilicon gate is fabricated, the resistance element 26 can be fabricated by applying the present invention.
Further, in the semiconductor integrated circuit, the portions made of P + polysilicon, such as the N + polysilicon gate 22 and the P + polysilicon gate 24, can have low resistivity, and can transmit electric signals at high speed as wiring or the like. It is suitable to do. At the same time, a portion made of N-polysilicon, such as the resistance element 26, can have an appropriately increased resistivity, which is suitable for forming a resistance element. Therefore, a necessary resistance value can be produced in a short distance. Thus, while suppressing an increase in the number of steps in the manufacturing process of the semiconductor integrated circuit, and while suppressing an increase in the number of types of masks used in the manufacturing process, it is preferable to form a resistive element,
Alternatively, a high resistivity region can be formed.

FIGS. 7 to 18 show a second embodiment to which the present invention is applied.
FIG. 4 is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment.

This embodiment is a dual gate CM having a P + polysilicon gate and an N + polysilicon gate.
In a method of manufacturing a semiconductor integrated circuit incorporating an OS,
In particular, it includes a titanium salicide process.
FIGS. 7 to 18 show cross sections of the semiconductor integrated circuit in each step in the order of steps and in each step, thereby showing what is performed in the manufacturing step in order.

First, when polysilicon 10 is deposited on the upper surface of the silicon substrate 1, the result is as shown in FIG. When N-impurity ion implantation (low-concentration impurity ion implantation) is performed from the upper surface of the polysilicon 10, the cross section becomes as shown in FIG.

In FIG. 9, an oxide film (silicon oxide film) 40 is formed on the upper surface of FIG. The oxide film 40 is used as a mask so that the titanium silicide film does not ride on a portion where a resistance element is formed.

FIG. 10 shows that a photoresist 42 is formed on the upper surface of the polysilicon 10 using a mask dedicated to the ion implantation. In FIG. 11, the photoresist 42
Is used as a mask, and shows a cross section in a state after high-concentration N + impurity ion implantation. In FIG. 12, the photoresist 42 has been removed.

FIG. 13 shows that a photoresist 44 is formed on the upper surface of the polysilicon 10 using a mask dedicated to the ion implantation. FIG. 14 is a cross-sectional view showing a state after high-concentration P + impurity ion implantation is performed using the photoresist 44. In FIG. 15, the photoresist 44 has been removed.

In FIG. 16, N + polysilicon gate 2
2, a P + polysilicon gate 24 and a resistance element 26 are formed. Also, these N + polysilicon gates 2
2, sidewalls 46 are formed of an oxide film on the P + polysilicon gate 24, the resistance element 26, and the like.

FIG. 17 shows a state after the sputtering and annealing of titanium are performed. In this figure, a titanium silicide film 50 and a titanium vapor deposition film 52 are formed. Since the oxide film 40 is formed on the upper surface of the resistance element 26, the titanium silicide film 50 is not formed.

In FIG. 18, an unnecessary oxide film 40,
The titanium deposition film 52 has been removed. At this stage, N
+ Polysilicon gate 22 and P + polysilicon gate 2
4, a titanium silicide film 50 is formed. On the other hand, the titanium silicide film 50 is not formed on the upper surface of the resistance element 26.

As described above, in a semiconductor integrated circuit in which a dual-gate CMOS having both a P + polysilicon gate and an N + polysilicon gate is fabricated, and in which a titanium silicide film is used, the present invention is applied. Can be built. Further, in the semiconductor integrated circuit, the portions made of P + polysilicon, such as the N + polysilicon gate 22 and the P + polysilicon gate 24, can have low resistivity, and can transmit electric signals at high speed as wiring or the like. It is suitable to do. At the same time, the parts made of N-polysilicon, such as the resistance element 26,
The resistivity can be appropriately increased, which is suitable for forming a resistance element, and a necessary resistance value can be formed in a short distance. Thus, while suppressing an increase in the number of steps in the manufacturing process of the semiconductor integrated circuit and suppressing an increase in the number of types of masks used in the manufacturing process, it is preferable to form a resistive element having a high resistivity. Alternatively, a high resistivity region can be formed.

[0040]

According to the present invention, it is possible to suppress the increase in the number of steps in the manufacturing process of a semiconductor integrated circuit and to suppress the increase in the number of types of masks used in the manufacturing process, and to manufacture a resistance element. A region having a higher or higher resistivity can be formed.

[Brief description of the drawings]

FIG. 1 is a plan view of an integrated circuit illustrating an operation of the present invention.

FIG. 2 is a sectional view of a first stage showing a method of manufacturing a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 3 is a sectional view of a second stage of the manufacturing method.

FIG. 4 is a sectional view of a third stage of the manufacturing method.

FIG. 5 is a sectional view of a fourth stage of the manufacturing method.

FIG. 6 is a sectional view of a fifth stage of the manufacturing method.

FIG. 7 is a sectional view of a first stage showing a method of manufacturing a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 8 is a sectional view of a second stage of the manufacturing method.

FIG. 9 is a sectional view of a third stage of the manufacturing method.

FIG. 10 is a sectional view of a fourth stage of the manufacturing method.

FIG. 11 is a sectional view of a fifth stage of the manufacturing method.

FIG. 12 is a sectional view of a sixth step of the manufacturing method.

FIG. 13 is a sectional view of a seventh step of the manufacturing method.

FIG. 14 is a sectional view of an eighth stage of the manufacturing method.

FIG. 15 is a sectional view of a ninth stage of the manufacturing method;

FIG. 16 is a sectional view of a tenth stage of the manufacturing method.

FIG. 17 is a sectional view of an eleventh stage of the manufacturing method.

FIG. 18 is a sectional view of a twelfth stage of the manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 10 ... Polysilicon 12, 14, 42, 44 ... Photoresist 22 ... N + polysilicon gate 24 ... P + polysilicon gate 26 ... Resistor 40 ... Oxide film 46 ... Side wall 50 ... Titanium silicide film 52 ... Titanium Evaporated film

Claims (4)

[Claims] 1. A semiconductor integrated circuit in which a dual gate CMOS having both a P + polysilicon gate and an N + polysilicon gate is fabricated, wherein a region in which the P + polysilicon gate is fabricated and a region in which the N + polysilicon gate is fabricated. Compared to the area,
A semiconductor integrated circuit, wherein a resistance element is formed in a polysilicon region having a low impurity concentration. 2. The semiconductor integrated circuit according to claim 1, wherein a titanium silicide film is formed on at least a part of an upper surface of the P + polysilicon gate and at least a part of an upper surface of the N + polysilicon gate. A semiconductor integrated circuit, wherein a titanium silicide film is not formed on an upper surface of the resistance element. 3. A method for manufacturing a semiconductor integrated circuit in which a dual-gate CMOS having both a P + polysilicon gate and an N + polysilicon gate is fabricated. In the method, a P + polysilicon gate and an N + polysilicon gate are fabricated in addition to a resistance element. First, a low-concentration impurity ion implantation is performed on the silicon substrate in the entire region, and thereafter, a high-concentration P + impurity ion implantation for forming the P + polysilicon gate and the N + polysilicon gate are formed. A method for manufacturing a semiconductor integrated circuit, wherein at the time of high concentration N + impurity ion implantation, at least a part of a region where the resistance element is formed is covered with each ion implantation mask. 4. The method of manufacturing a semiconductor integrated circuit according to claim 3, wherein a titanium silicide film is formed on an upper surface of said P + polysilicon gate and said N + polysilicon gate.
Before the film formation and after the low concentration impurity ion implantation, an oxide insulating film for preventing a titanium silicide film from being formed is formed so as to cover at least a part of a region where the resistance element is formed. A method for manufacturing a semiconductor integrated circuit.