JPH11232783A - Semiconductor device and magnetic disk device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device for processing a channel signal being suitable for recording data in high density by generating an eraser flag for performing eraser correction for residual erroneous discrimination in a discrimination feedback type equalizer. SOLUTION: This device is constituted with a signal processing means recording digital information with an error correction code, a discrimination feedback type equalizer having at least two discrimination feedback loops as reproduced signal processing and having a means detecting an abnormal level of an input signal of a level detector and feeding back a discriminated result directly before detection and an inverse discriminated result, a means 12 generating an eraser flag signal from a detected output of an abnormal level in this two loops, and an error correction processing means 14 performing eraser correction using this eraser flag signal. Thereby, signal processing being suitable for high density recording can be realized, and a magnetic disk device having high density and large capacity can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method for recording digital data at a high density on a recording medium such as a magnetic disk, a semiconductor device using the signal processing method,
More specifically, the present invention relates to a read channel LSI for a magnetic disk, and the technical content relates to improvement of a decision feedback equalizer.

[0002]

2. Description of the Related Art As the operation speed of computers increases, application software requiring a large-capacity memory is used, and the demand for high-density compact magnetic disks is increasing. For this reason, recently, the partial response class
Attention has been paid to a PRML method that combines the equalization method 4 (hereinafter referred to as PR4) and maximum likelihood decoding, and an improvement of about 3 dB in S / N has been realized as compared with the conventional peak detection method. For details on these technical features, see, for example,
This is described in "PRML and Coding Techniques", Vol. 17-2, No. 4, August 1994.

On the other hand, a decision feedback equalizer (Decision feedbac
k equalization (hereinafter referred to as DFE) is used in digital signal reception systems in wired and wireless communications.
Recently, attention has been paid to signal processing of the recording / reproducing system of the magnetic disk. For example, Journal of Applied Phy
sics, Vol. 79, No. 8 (April 1996)
"Signal processing for 10 Gbit / in" by C. Modlin
magnetic disk recording and beyond "
The superiority of E is shown. That is, DFE reports that the area density can be improved by 1.1 to 1.2 times as compared with PRML.

[0004] Various improvements relating to DFE have been filed. For example, Japanese Patent Laid-Open Publication No.
An improvement relating to clock extraction is disclosed. Also,
FIG. 1 shows an embodiment constituted by a design concept created by the present inventors as an effective measure against error propagation as compared with the conventional DFE. 11-1 is a pre-filter (shown as FFF in the figure), 11-2 and 11-3 are subtraction circuits, 11-4 and 11-5 are level detectors, 11-6 and 11-7 are feedback filters, 11 -8, 11
-9 and 11-10 are switch circuits, 11-11
Is a latch circuit, 11-12 are two-stage shift registers,
Reference numeral 1-13 denotes a shift register having a plurality of stages, reference numeral 11-14 denotes an inverting circuit, and reference numeral 11-15 denotes a logic circuit for estimating a continuous determination error. This DFE has two loops,
The DFE is characterized by detecting the presence or absence of an abnormal level of the input signal to the level detectors 11-4 and 11-5, and feeding back the immediately preceding judgment result and the opposite judgment result to respective feedback loops. . Provisional judgment result, ie, D
When trying to get the detection result from 1 or D2 output,
According to the detection result of the abnormal level, whether the temporary determination is kept or inverted. The selection is performed by the switch 11-9. The output is the DFE detection result DATA.
This is the basic operation of the DFE 11. Note that n in the outputs D1n and D2n in FIG. 1 indicates time.

The general features of the DFE will be described with reference to the waveforms of FIG. In FIG. 2, a recording pattern (a) is recorded on a magnetic disk (not shown), and the recording pattern is reproduced by a reproducing head (not shown) to give a reproduction output (b). Generally, a reproduction output obtained when a pulse having a pulse width of a single bit interval is recorded in a magnetic recording / reproducing system is called a pulse response. The pulse response of the magnetic recording / reproducing system including the magnetic disk and the magnetic head is shown in FIG. This pulse response is made to correspond to the pulse indicated by 1 in the recording pattern (a), and an output obtained by adding the respective responses becomes a reproduction output (b). In the DFE, first, a pulse response (c) is equalized to a predetermined response (d) by a prefilter (hereinafter, referred to as an FFF). The response of the conventional PR4 equalization is shown by (d '). The response (d) for DFE has a long response that interferes with subsequent bits as a matter of course that there is a response to the bit. This suggests that the FFF of the DFE is of a low-pass type and has a narrower frequency band than that of PR4 equalization. Now, in the DFE, as shown in FIG. 1, a subtraction circuit 11-2,
Level detector 11-4 and feedback filter 11
-6 form one basic loop. As shown in FIG. 2 (d), at time tn, the presence or absence of this pulse response is determined, and if a response is detected, it is created by the feedback filter as a feedback component of the pulse response after time tn + 1. This feedback component is input to the subtraction circuit, and an interference component other than the bit is removed. That is, if there is no determination error in the past, the signal waveform (e) corresponding to the recording pattern is
-4 is input, and the level is determined. However, in an actual recording / reproducing system, since a reproduced signal including noise is targeted, a determination error cannot be avoided. If a decision error occurs, an erroneous feedback signal is generated, which has a serious adverse effect on subsequent decision results. For this reason, it is important to detect an error in the judgment circuit as soon as possible and to return to a normal state. Since an erroneous feedback signal is generated due to a determination error, a signal exceeding an original predetermined range is input to the input of the level detector. For this reason, the level detectors 11-4 and 11-5 determine whether the input signal is within a predetermined range or outside the range, and detect the presence or absence of an abnormal level. If an abnormal level is detected, it is assumed that the determination result immediately before generating the feedback signal (that is, one time before) is incorrect. Since two loops are provided, only the immediately preceding determination result is fed back to the first loop with a result that seems to be correct,
The opposite determination result is also fed back to the second loop.
If an abnormality is detected in the first loop, the judgment output of the second loop is adopted as being correct. As a result, a decision error due to noise is detected and corrected, and error propagation is prevented.

However, assuming a special situation such as a case where the noise is extremely large or a case where the noise continues for a long time, the apparatus has the two loops shown in FIG. In a DFE characterized by feeding back the opposite determination result, hereinafter simply referred to as “Ex-DFE”, it is necessary to consider that an error may occur for a very long time, although it is extremely rare.

In general, for such a long error, it is proposed to apply the encoding while interleaving the error correction encoding on the information data to be recorded on the recording side in advance. .

[0008]

If the redundancy of the error correction code can be inserted sufficiently large as compared with the information signal to be transmitted as in a communication system, error correction can be performed even for long errors by ordinary interleave correction processing. It is possible to do. However, in the magnetic disk system, since the redundancy assigned to error correction is small, it is necessary to efficiently perform error correction. If you know the location of the data that may be wrong, the erasure correction method is used,
It can work with twice the normal correction capacity. Therefore, an object of the present invention is to perform the erasure correction by using Ex
The object of the present invention is to provide a circuit configuration for outputting, as an erasure flag, a position where a decision error occurring in the DFE may exist. Another object of the present invention is to provide a semiconductor device including the circuit, and further provide a high-density recordable magnetic disk device incorporating the semiconductor device.

[0009]

According to the present invention, there is provided a signal processing means for recording digital information together with an error correction code, and at least a two-decision feedback loop as reproduction signal processing, wherein an abnormality in an input signal of a level detector is provided. A decision feedback equalizer having means for detecting a level and feeding back the immediately preceding decision result and the opposite decision result, means for generating an erasure flag signal from an abnormal level detection output in the two loops, Using the signal
It comprises error correction processing means for performing erasure correction.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to embodiments. FIG. 3 is a signal system diagram of the magnetic disk drive in the embodiment of the present invention. The computer interface 1 has a function of exchanging data between the computer main unit and the magnetic disk device. Normally, data is transferred between the magnetic disk device and the computer in 512-byte (1 byte is composed of 8 bits) sectors, each sector having a size of one sector. A signal from the interface 1 is recorded on a recording medium 7 via a semiconductor device 2 that performs signal processing for recording and reproduction. A reproduction signal from the recording medium 7 is also returned to the interface 1 via the semiconductor device 2.

In the signal processing on the recording side of the semiconductor device 2, first, the digital signal D
i is coded for error correction by the error correction coding circuit 3 and becomes a (Di + P) digital signal sequence. Here, P is a check code string of an error correction code. After that, it is converted into a recording code sequence Ci that can be easily recorded on the recording medium 7 by the channel encoder 4. The recording code sequence Ci is recorded on the recording medium 7 via the amplifier circuit 5 and the recording head 6. On the other hand, when a command to read the recording data of the recording medium 7 is given via the interface 1, the reproducing head 8 moves to the position of the data to be read and performs the reading operation.

A reproduction signal obtained from the recording medium 7 via the reproduction head 8 is amplified to a signal of a predetermined magnitude by an amplifier circuit 9 and input to a low-pass analog filter 10 for removing noise components outside the signal band. You. The Ex-DFE 11 whose basic configuration is shown in FIG.
(Ci + Er) in which the error Er is added to the signal sequence, that is, the DATA shown in FIG. 1 is detected. Further, the erasure flag generation means 12 generates an erasure flag signal E-Flag indicating a position of a part where an error included in the detected digital signal may have occurred from the abnormal level detection output obtained by the Ex-DFE 11. . The detected recording code sequence (Ci + Er) is converted by the channel decoding circuit 13 into (Di + P + Err). The error Er is also converted into the error Err by the channel decoding process. Using the erasure flag signal E-Flag, the error correction circuit 14 performs efficient erasure error correction,
The input digital signal sequence Di is restored.

FIG. 4 shows the output states of the abnormal level detection outputs Ex1 and Ex2 of the Ex-DFE11 used in the present invention and the DF.
9 shows the operation state of E. When the DFE 11 is normal, a signal within a predetermined range is input to the level detector 11-4 of the first loop, so that Ex1 = 0. On the other hand, since the second loop feeds back a signal obtained by inverting the previous normal decision, when the noise superimposed on the FFF output is small, a signal outside a predetermined range is input to the level detector 11-5. That is, Ex2 = 1. However, when the superimposed noise is large or when an error is propagating, the output form at the time of abnormality shown in FIG. 4 is adopted. From FIG. 4, it can be seen that the output of EX2 should be inverted and an OR operation should be performed with the output of Ex1 in order to set a flag when an abnormality occurs.

Next, the error correction interleave processing and the erasure correction will be described. FIG. 5 shows a digital signal sequence (D) included in one sector recorded on a recording track.
i) and the check code string P. However, the operation of the error correction coding is performed by dividing into three independent sequences of A, B, and C. That is, the case where three interleaving is performed is shown. In the A series, word A1, word A2,. . . And an error correction code is calculated for the digital data signal for every three words to form a check code string composed of AE4, AE5 and the like. The whole of the three sequences of check code strings is represented as a check code string P. A Reed-Solomon code is used as the error correction code. FIG. 6 shows 1 as viewed from the error correction code.
It is a data configuration of a sector. Three independent vertical error correction codes are configured. 5 words in each series (eg AE
1, AE2, AE3, AE4, and AE5) are formed, so that two-word random correction is possible. The random correction means that an error of up to two words can be corrected at any position. This means that random errors of three or more words cannot be dealt with. However, erasure correction can correct up to twice as many as four words. However, it must be possible to specify a word position where an error may occur. Therefore, as shown in FIG. 6, Ex-D
If the abnormal time in FIG. 4 is determined from the abnormality detection output of the FE, it is possible to know which word has an abnormality. Therefore, the erasure correction is performed using the abnormal time as an erasure flag. FIG. 7 shows an erasure flag generation circuit.
As described above, the Ex-2 output is inverted by the inverting circuit 12-1, and the Ex-1 output and the OR circuit 12-2 are input. The output of the OR circuit 12-2 is input to the set terminal of the set / reset flip-flop 12-3. Since the three-word interleave cycle clock I-CLK of the demodulated digital signal sequence is input to the reset terminal of the flip-flop 12-3, the presence or absence of the erasure flag can be confirmed at the interleave cycle.
Erasure correction is performed based on the erasure flag.
Even in this case, since more than 5 words cannot be corrected, when the number of erasure flags is too large, it is necessary to send a command request to the computer via the interface 1 for performing a specific process such as rereading.

The number of erasure flags can be grasped at a stage before performing an error correction operation. That is, by counting the number from the erasure flag or the abnormality detection output, for example, it is possible to determine and re-read the data and execute the same.

FIGS. 8 and 9 are signal system diagrams of another embodiment of the present invention. The DFE of FIG. 1 does not particularly show a circuit for extracting a reproduction clock necessary for the DFE, but FIG. 8 shows such a circuit. The output signal of the first loop subtraction circuit 11-3 is input to the level detector 11-4 and also to the clock extraction circuit 11-16. When there is no determination error, as shown in FIG. 2E, a sample value corresponding to the recording pattern is obtained as an output signal of the subtraction circuit 11-3. Although not described so far, in FIGS. 1 and 8, each signal is processed with a sample value sampled at a clock cycle. Using this sample value and the tentative determination result, that is, the output of the switch circuit 11-8, the reproduction clock phase for the FFF output can be determined. That is, since an actual sample value is obtained for a predetermined sample value having no noise or clock deviation, the difference and the provisional determination result are calculated by the phase detection circuit 11-16-1 to obtain the voltage control oscillator 11-16. The phase difference from the reproduced clock signal which is the output of -3 is detected. Further, the low-pass filter 11-1
By removing a sudden change in the phase difference information by 6-2 and inputting it to the voltage controlled oscillator 11-16-3,
A clock synchronized with the reproduction signal can be extracted. However, when the number of determination errors increases, the output of the subtraction circuit 11-3 is affected by an erroneous feedback signal. Therefore, the voltage-controlled oscillator 11-16-3 does not control the input phase information but retains the previous value. (Hold) should be controlled. The control signal for switching to the hold state is generated by the clock extraction control signal generation circuit 15 shown in FIG. As in FIG. 7, the inverted Ex2 output and the Ex1 output are input to the OR circuit 15-2. Since whether or not there is an abnormality is obtained at the bit interval, the number of the abnormality at the word interval is counted by the counter 15-3. The counter 15-3 is a predetermined number (set bits) in word units.
And a comparison circuit 15-4. The comparison circuit 15-4 generates a hold control signal so that phase information corresponding to a word whose number is equal to or greater than a predetermined number is not input to the voltage controlled oscillation circuit 11-16-3.

[0017]

According to the present invention, a signal processing method suitable for high-density recording is provided. In other words, it is possible to ensure the reliability of the magnetic disk device having a low resolution. That is, there is an effect of providing a margin in the spacing between the magnetic disk and the head, which is one of the parameters giving the resolution, and an effect of preventing self such as a head crash.

[Brief description of the drawings]

FIG. 1 is an example of a circuit configuration diagram of an Ex-DFE as a premise of the present invention.

FIG. 2 is a waveform chart for explaining the operation and characteristics of a decision feedback equalizer (DFE).

FIG. 3 is a signal system diagram of a recording / reproducing system according to the embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between an operation state and an abnormal level detection output in the EX-DFE of the present invention.

FIG. 5 is a diagram showing an example of a digital signal sequence on a recording track according to the embodiment of the present invention.

FIG. 6 is a diagram showing the form of a digital signal in which FIG. 5 is rewritten with an emphasis on the operation of an error correction code.

FIG. 7 is an example of an erasure flag generation circuit according to an embodiment of the present invention.

FIG. 8 is a signal system diagram of a clock extraction circuit according to the embodiment of the present invention.

FIG. 9 is a circuit configuration diagram of a hold control signal generation circuit of the voltage controlled oscillator according to the embodiment of the present invention.

[Explanation of symbols]

3 error correction coding circuit, 4 channel encoder, 7 recording medium, 8 reproduction head, 11 Ex-DFE, 12
Erasure flag generation means, 13: channel decoding circuit, 14: error correction circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11B 20/18 572 G11B 20/18 572F

Claims (8)

[Claims] 1. A reproduction signal processing semiconductor device mounted on a magnetic disk device for recording / reproducing digital information has at least two decision feedback loops and detects an abnormal level of an input signal of a level detector. A semiconductor device comprising: a decision feedback equalizer having means for feeding back the immediately preceding decision result and the opposite decision result; and a means for generating an erasure flag signal from a detection output of an abnormal level in the two loops. . 2. A semiconductor device for processing a reproduction signal mounted on a magnetic disk device for recording and reproducing digital information, comprising: signal processing means for recording digital information together with an error correction code; and at least two decision feedback loops. ,
A decision feedback equalizer having means for detecting an abnormal level of the input signal of the level detector and feeding back the immediately preceding judgment result and the opposite judgment result; and an erasure flag signal from the abnormal level detection output in the two loops And an error correction processing means for performing erasure correction using the erasure flag signal. 3. A reproduction signal processing semiconductor device mounted on a magnetic disk device for recording and reproducing digital information, the device having at least two decision feedback loops, detecting an abnormal level of an input signal of a level detector, A semiconductor device comprising: a decision feedback equalizer having means for feeding back the immediately preceding decision result and the opposite decision result; and means for generating a control signal from an abnormal level detection output in the two loops. . 4. The semiconductor device according to claim 3, wherein said control signal is a signal related to a reread command. 5. The semiconductor device according to claim 3, wherein said control signal is a signal related to a reproduced clock signal of a decision feedback equalizer. 6. A magnetic disk drive on which the semiconductor device according to claim 1 is mounted. 7. A magnetic disk drive on which the semiconductor device according to claim 2 is mounted. 8. A magnetic disk drive on which the semiconductor device according to claim 3 is mounted.