JPH11232209A - Computer system and method for allocating bus application right - Google Patents

Abstract

PROBLEM TO BE SOLVED: To preferentially execute an access request from a specific external device. SOLUTION: A computer system for successively providing the application right of a system bus 1 connected to a CPU 2 and a memory 3 to respective I/O control parts 6 respectively connected to external devices by a bus arbitration part 5 is provided with a timer circuit 7 for counting up time up to the time specified by a specific I/O control part 6 out of plural ones. The bus arbitration part 5 unconditionally provides the application right of the system bus 1 to the specific I/O control part 6 in response to the end of timing of the timer circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for receiving a plurality of access requests from external devices, and a method for allocating a bus right in the computer system.

[0002]

2. Description of the Related Art In a computer system which accepts a plurality of access requests from external devices, input access requests are once taken into an I / O (input / output) control unit. Then, each I / O control unit controls the C via the system bus.
An access request for a PU or a memory is sent.

In this case, a bus arbitration unit is provided in order to prevent contention of access requests from occurring on a system bus to which a CPU and a memory are connected. Is assigned to each I / O control unit. The most common allocation method of the right to use the system bus in the bus arbitration unit is a round robin method in which access requests of each I / O control unit are sequentially allocated in the order of acceptance.

In the round robin method, a data write request to a memory of a computer system, a data read request from a memory of a computer system, and a processing request in a computer system are performed by each I / O connected to each external device. Since all are equal to the O-control unit, each external device can always obtain the access result after a predetermined time has passed since sending the access request.

[0005]

However, even in a computer system that sequentially processes access requests from each external device using the above-described round robin method, there are still the following problems to be improved. Was.

That is, since all access requests from each external device are treated equally, for example, for a specific access request, it may be necessary to execute access processing immediately after the occurrence of the access request, that is, in real time. For example, it is assumed that a system in which process data that changes greatly with the passage of time is written to a memory at a fixed time interval, for example, and various calculations are performed using each data written in this memory in time series. I do.

In this case, in various calculations using each data, the amount of change and acceleration of the data are calculated on the assumption that the data written in the memory is written at regular time intervals. However, in the round robin method, the time interval for writing data to the memory is not always constant depending on the degree of occurrence of access requests from other external devices. As a result, there is a concern that the reliability of the calculation result calculated using each data stored in the memory may be reduced.

Therefore, in a computer system employing this method, there is a problem that processing for a plurality of access requests in which access requests requiring real-time processing are mixed cannot be performed properly.

The present invention has been made in view of such circumstances. For example, an access request from a specific I / O control unit that requires real-time processing is unconditionally used for a system bus. Even if a plurality of access requests are received from an external device, real-time performance can be reliably ensured for an access request from a specific I / O control unit, and the configuration is complicated. It is an object of the present invention to provide a computer system capable of extending the operation range of the entire system without any problem, and a method for allocating bus use rights of the computer system.

[0010]

According to a first aspect of the present invention, a right to use a system bus to which a CPU and a memory are connected is assigned by a bus arbitration unit to a plurality of buses connected to an external device. In a computer system that sequentially gives each I / O (input / output) control unit in the I / O control unit, until a time specified by a specific I / O control unit among a plurality of I / O control units Is provided. Further, the bus arbitration unit grants the right to use the system bus to a specific I / O control unit in response to the end of the timing of the timer circuit.

According to a second aspect of the present invention, a right to use a system bus to which a CPU and a memory are connected is controlled by a bus arbitration unit in each of a plurality of I / O control units connected to an external device. In a computer system that sequentially supplies the information to the units, a timer circuit that measures time until a time specified by a specific I / O control unit among the plurality of I / O control units is connected to at least a memory. A dedicated real-time bus is provided. Further, the memory is a dual port memory in which a system bus and a real-time dedicated bus are connected. Further, the bus arbitration unit grants the right to use the real-time dedicated bus to a specific I / O control unit in response to the end of the timing of the timer circuit.

Further, according to a third aspect of the present invention, there is provided a bus use system wherein a right to use a system bus in a computer system is sequentially given to each I / O control unit in a plurality of I / O control units connected to an external device. In the right assignment method, a time is counted up to a time designated by a specific I / O control unit among a plurality of I / O control units. The right to use the system bus is unconditionally given to the / O control unit.

In the computer system according to the first aspect and the method for allocating the bus use right according to the third aspect of the present invention, for example, of the plurality of I / O control units that issue an access request to the computer system, A specific I / O control unit that generates an access request that requires real-time property sets the time of occurrence of the next access request in a timer circuit. Then, the timer circuit starts measuring time, and when the time reaches the time, the bus arbitration unit operates, and the right to use the system bus is unconditionally given to this specific I / O control unit. Therefore, an access request of a specific I / O control unit is processed almost in real time.

Further, in the computer system according to the present invention, a real-time dedicated bus is provided in addition to a normal system bus. Further, since the memory is constituted by a dual-port memory, the above-mentioned access request from the specific I / O control unit which requires real-time performance is transmitted via one port of the dual-port memory via the real-time dedicated bus. Is performed on the memory.

In this period, a normal access request from another I / O control unit is executed to the memory via the other port via the system bus, so that the other normal access request is executed in real time. There is no need to wait until the end of processing for an access request that requires reliability.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a computer system of a first embodiment to which a bus use right assignment method of the present invention is applied.

A CPU 2 for performing various processing tasks on a system bus 1 comprising an address bus and a data bus;
A memory 2 for storing a control program and various processing data, a DMA control unit 4, a bus arbitration unit 5, and the like are connected. The DMA control unit 4 and the bus arbitration unit 5 each include a plurality of I / O control units 6 connected to an external device (not shown).
Is connected. The bus arbitration unit 5 is connected to a timer circuit 7.

In such a computer system, an external device (not shown) periodically or irregularly sends a data write or read access request to the memory 3 in the computer system. Each access request input from an external device (not shown) is once taken into each I / O control unit 6.

Each I / O control unit 6 sends the input access request to the DMA control unit 4 and the bus arbitration unit 5. In the normal state, the bus arbitration unit 5 sequentially assigns the right to use the system bus 1 to the input access request in a round-robin manner. That is, the bus arbitration unit 5 monitors the use state of the system bus 1 and
The access requests input from the I / O control unit 6 are stored in a queue memory (queue) in the order of input, and each I / O control unit 6
, The right to use the system bus 1 is allocated in the order of input.

The DMA control unit 4 sends an access request from the I / O control unit 6 to which the right to use the system bus 1 has been assigned by the bus arbitration unit 5 to the memory 3 via the system bus 1 without passing through the CPU 2. Then, an access process for writing and reading data to and from the corresponding memory 3 is executed, and the result of the access process is returned to the external device as the access request source via the I / O control unit 6.

When it is necessary for each external device to send an access request for which it is necessary to secure real-time properties, the external device determines the execution time of the access before sending this access request. Send to

The bus arbitration unit 5 outputs a specific I / O for outputting an access request for which this real-time property needs to be ensured.
When a specified time of access execution specifying the I / O control unit 6 from the control unit 6 is input, the specified time is set in the timer circuit 7. The timer circuit 7 measures the time until the designated time, and when the time measurement is completed, notifies the bus arbitration circuit 5 of the completion of the time measurement. At the same time, a bus use interrupt signal is sent to the CPU 2.

When the CPU 2 receives the interrupt signal from the timer circuit 7, if the CPU 2 itself uses the system bus 1, the CPU 2 temporarily stops using the system bus 1 after one or several clock cycles. Then, the system bus 1 is vacated.

When the bus arbitration circuit 5 receives from the timer circuit 7 the end of timekeeping specifying the specific I / O control unit 6,
The DMA control unit 4 is notified that the right to use the system bus 1 is unconditionally assigned to the specified I / O control unit 6.

The DMA controller 4 sends the access request of the specific I / O controller 6 to which the right to use the system bus 1 is assigned by the bus arbitration unit 5 via the system bus 1 without passing through the CPU 2. To perform an access process for writing and reading data to and from the corresponding memory 3, and return the result of the access process to the external device as the access request source via the I / O control unit 6.

FIG. 2 is a flowchart showing the arbitration operation of the bus arbitration circuit 5 described above. When there is a time setting request from a specific I / O control unit 6 that needs to execute real-time processing for an access request (S1), the timer circuit 7 specifies the corresponding time and the corresponding I / O control unit 6. I / O control unit ID
Is set (S2).

When the timer end notification is not input from the timer circuit 7 (S3), the right to use the system bus 1 is given to the I / O control unit 6 determined by the ordinary round robin method (S4). When the timer end notification is input from the timer circuit 7 (S3), the right to use the system bus 1 is given to the specific I / O control unit 6 designated by the clock end notification (S5).

In the computer system of the first embodiment configured as described above, of the plurality of external devices that issue an access request to the computer system, for example, a specification that issues an access request that requires real-time performance is specified. Can set the time of occurrence of the next access request to the timer circuit 7 via the I / O control unit 6 and the bus arbitration unit 5.

Then, when the relevant time is reached, the bus arbitration unit 5 operates, and the right to use the system bus 1 is unconditionally given to the I / O control unit 6 of this specific external device.
Therefore, an access request from a specific I / O control unit 6 is processed in real time.

As described above, when an access request from a plurality of external devices is received, for example, the system is given priority only to a specific access request that requires real-time property and to other general access requests. Since the right to use the bus can be given, the scope of application of the computer system can be greatly expanded.

(Second Embodiment) FIG. 3 is a block diagram showing a schematic configuration of a computer system according to a second embodiment of the present invention. The same parts as those of the computer system of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description of the overlapping parts will be omitted.

In the computer system according to the second embodiment, a real-time dedicated bus 8 is provided in addition to the system bus 1. Further, the memory 3 shown in FIG. 1 is replaced with a dual port memory 3a. One write / read port (terminal) of the dual port memory 3 a is connected to the system bus 1, and the other write / read port (terminal) is connected to the real-time bus 8.

The CPU 2 can access the dual port memory 3a via the system bus 1 and one of the write / read ports. The DMA controller 4a simultaneously responds to a plurality of access requests via the system bus 1 and the real-time dedicated bus 8 to the dual port memory 3 simultaneously.
a can be executed. Thus, DMA
The control unit 4a can execute a plurality of access requests, but, of course, is controlled so that access requests to the same address in the dual port memory 3a are not executed simultaneously.

The bus arbitration unit 5a can select either the system bus 1 or the real-time dedicated bus 8 for one access request and give the right to use. In the normal state, the bus arbitration unit 5a responds to each access request input from each external device via the I / O control unit 6 by using a round robin method. The right to use the Sysdem bus 1 is given. Therefore, in the normal state, the DMA controller 4a also accesses the dual port memory 3a via the system bus 1 for each access request given by the bus arbitration unit 5a in a round robin manner. ,
The access result is returned to the requesting external device.

When it is necessary for each external device to send an access request for which it is necessary to secure the real-time property, before sending this access request, the external device determines the execution time of the corresponding access by the bus arbitration unit 5a. Send to

The bus arbitration unit 5a outputs a specific I / O for outputting an access request for which this real-time property needs to be ensured.
When a specified time of access execution specifying the I / O control unit 6 from the O control unit 6 is input, the specified time is set to the timer circuit 7.
Set to a. The timer circuit 7a measures the time up to the designated time, and when the time measurement ends, the bus arbitration circuit 5a
To the end of timing.

When the bus arbitration circuit 5a receives the time-out from the timer circuit 7a specifying the specific I / O control unit 6, the bus arbitration circuit 5a responds to the access request from the specific I / O control unit 6 in response to the real-time dedicated DMA control unit 4
Notify a.

The DMA control unit 4a includes a bus arbitration unit 5a
Sends the access request of the specific I / O control unit 6 to which the right to use the real-time dedicated bus 8 is assigned to the dual-port memory 3a via the real-time dedicated bus 8, and writes / reads data to / from the dual-port memory 3a. Is executed, and the result of the access processing is
The access request is returned to the external device via the O control unit 6.

The bus arbitration unit 5a has a right to use the normal system bus 1 for an access request from each I / O control unit 6 other than an access request from a specific I / O control unit 6. Therefore, individual access requests are simultaneously assigned to the real-time dedicated bus 8 and the system bus 1. As a result, the DMA control unit 4a can simultaneously execute different access processing to the dual port memory 3a via the real-time dedicated bus 8 and the system bus 1.

FIG. 4 is a flowchart showing the arbitration operation of the bus arbitration circuit 5a. When there is a time setting request from a specific I / O control unit 6 that needs to execute real-time processing for an access request (R1), the timer circuit 7a specifies the corresponding time and the corresponding I / O control unit 6. An I / O control unit ID is set (R2).

If the timer end notification is not input from the timer circuit 7a (R3), the right to use the system bus 1 is given to the I / O control unit 6 determined by the ordinary round robin method (R4). When the clock end notification is input from the timer circuit 7a (R3), the real-time dedicated bus 8 is sent to the specific I / O control unit 6 specified by the clock end notification.
(R5). Then, the process proceeds to R4, and the right to use the system bus 1 is given to the I / O control unit 6 determined by the normal round robin method.

In the computer system of the second embodiment configured as described above, similarly to the computer system of the first embodiment, a specific external device that generates an access request requiring real-time processing is a bus arbitration unit 5a. , It is possible to set the time of occurrence of the next access request to the timer circuit 7a.

When the relevant time is reached, the bus arbitration unit 5a operates to give the I / O control unit 6 of this specific external device the right to use the real-time dedicated bus 8. Therefore, an access request from a specific I / O control unit 6 is processed in real time. In this case, an access request from a general external device other than a specific external device is transmitted to the normal system bus 1.
, The execution of the normal access request does not have to wait until the end of the access processing for the real-time access request.

As described above, when an access request from a plurality of external devices is received, for example, only a specific access request that requires real-time property is distinguished from other general access requests by another route. Since the access processing is executed, the specific access processing can be performed in real tile without affecting other general access requests. Therefore, the application range of the computer system can be further greatly expanded.

[0045]

As described above, in the computer system and the method for allocating the bus use right in the computer system according to the present invention, a timer circuit and a bus arbitration unit are provided so that, for example, a specific I / O which requires real-time performance is provided. The access right from the O control unit is unconditionally given the right to use the system bus.

Therefore, even when a plurality of access requests are received from an external device, it is possible to reliably ensure real-time access requests from a specific I / O control unit without complicating the configuration. The operation range of the entire system can be expanded.

Further, in the computer system of another invention, a dual port memory and a real-time dedicated bus are provided, and the real-time dedicated bus is provided for an access request from a specific I / O control unit requiring a real-time property. Has been granted the right to use.

Therefore, a specific access process can be performed in real tile without affecting other general access requests. Therefore, the application range of the computer system can be further greatly expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a computer system to which a bus use right assignment method according to a first embodiment of the present invention is applied;

FIG. 2 is a flowchart showing an operation of allocating a bus right in a bus arbitration unit of the computer system;

FIG. 3 is a block diagram showing a schematic configuration of a computer system according to a second embodiment of the present invention;

FIG. 4 is a flowchart showing an operation of allocating a bus right in a bus arbitration unit of the computer system;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... System bus 2 ... CPU 3 ... Memory 3a ... Dual port memory 4, 4a ... DMA control part 5, 5a ... Bus arbitration part 6 ... I / O control part 7, 7a ... Timer circuit 8 ... Real time exclusive bus

Claims (3)

[Claims] 1. A bus arbitration unit sequentially grants a right to use a system bus to which a CPU and a memory are connected to each I / O control unit in a plurality of I / O control units connected to an external device. In the computer system, a timer circuit for measuring a time until a time designated by a specific I / O control unit of the plurality of I / O control units is provided, and the bus arbitration unit is configured to measure the time of the timer circuit. In response to the termination, the computer system unconditionally grants a right to use the system bus to the specific I / O control unit. 2. A bus arbitration unit sequentially grants a right to use a system bus to which a CPU and a memory are connected to each I / O control unit in a plurality of I / O control units connected to an external device. In the computer system, a timer circuit that measures time until a time specified by a specific I / O control unit of the plurality of I / O control units;
A real-time dedicated bus to which at least the memory is connected; a dual-port memory, wherein the memory is connected to the system bus and the real-time dedicated bus; the bus arbitration unit responds to the end of timing of the timer circuit And giving the right to use the real-time dedicated bus to the specific I / O control unit. 3. A bus use right assignment method for sequentially assigning a use right to a system bus in a computer system to each I / O control unit in a plurality of I / O control units connected to an external device, The time up to the time specified by the specific I / O control unit of the plurality of I / O control units is measured, and when the time measurement up to the specified time is completed, the specific I / O control unit is stopped.
A method of assigning a right to use the system bus to the / O control unit unconditionally.