JPH11232097A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the real time performance of an event processing and to efficiently execute the event processing. SOLUTION: A bus interface 2 monitors a bus event, and when the bus event occurs, an event address EA is supplied to an event instruction issuing part 3, which is provided with a memory array divided by an instruction line so as to store processing instructions related to plural events. Each instruction line holds series of instructions including plural instructions for changing an instruction fetch address in advance. When the bus event occurs, the event instruction issuing part 3 is switched from an ordinary mode to an event processing mode and by switching a selector 4, in place of the instruction fetch from a cache 1, series of instructions corresponding to the instruction fetch address are supplied to a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus equipped with a CPU and the like, and more particularly to an information processing apparatus for efficiently executing an event process for an event that can be detected as a bus event.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus employs an event notification method using an interrupt for an event such as the end of a DMA transfer. In the case of event notification processing using interrupts, since many interrupt request sources are serviced using a limited interrupt line, the interrupt request source is uniquely identified from the interrupt line asserted when an interrupt occurs Can not do, CPU
The OS operating on the above searches the chain of the device structure expressing the device, and confirms whether or not each of the plurality of devices using the asserted interrupt line has issued the interrupt, thereby actually executing the interrupt. The device that issued the interrupt is identified (polling).

For example, JP-A-5-108479 and JP-A-6-28258 disclose techniques for providing a cache dedicated to event processing when an event occurs to speed up event processing and normal processing. Although the technique described above can execute the above-mentioned polling processing at high speed, it does not make the polling processing unnecessary.

[0004]

However, in the conventional polling method, the process of searching for a chain of a device structure and the process of confirming whether or not each device issues an interrupt are heavy, and the real-time performance is greatly increased. There was a problem of lowering.

The present invention has been made in view of the above circumstances, and has as its object to provide an information processing apparatus that can improve the real-time property of event processing and can execute the processing efficiently.

[0006]

According to a first aspect of the present invention, there is provided an arithmetic unit for outputting an instruction address and executing an instruction corresponding to the instruction address; Bus event monitoring means for monitoring, holding means for holding a series of a plurality of instructions related to the plurality of bus events, and when the bus event monitoring means detects a bus event, the bus event is held and detected by the holding means. Event instruction issuing means for outputting a series of plural instructions corresponding to the bus event to the arithmetic means.

According to the present invention, a series of a plurality of instructions related to a plurality of bus events is held in the holding means,
When a bus event is detected by the bus event monitoring unit, a series of multiple instructions corresponding to the detected bus event are output to the arithmetic unit by the event instruction issuing unit instead of the normal instruction and held by the holding unit. As a result, the polling process becomes unnecessary, the real-time property of the event process can be improved, and the event process can be executed efficiently.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

A. Configuration of Embodiment FIG. 1 is a block diagram showing a partial configuration of an information processing apparatus according to an embodiment of the present invention. In the figure, an instruction cache 1 caches an instruction for an instruction address output from a CPU to a CPU address ADD, and supplies a cache output instruction S2 corresponding to the instruction address to the selector 4. The bus interface 2 is connected to the data bus D
B, a bus address representing a bus event and a control signal (hereinafter, referred to as an event address EA) are taken out from an address bus (including a control bus) AB and supplied to the event instruction issuing unit 3.

The event instruction issuing unit 3 stores a plurality of event instructions related to a bus event, monitors an event address EA via the bus interface 2, and registers a bus event registered therein (readout for a specific address). / Write access) is detected, the mode signal MS is switched. In response to the mode signal MS, the selector 4 outputs the event instruction S3 registered in association with the cache output instruction S2 supplied from the cache 1 or the detected bus event from the event instruction issuing unit 3.
Is output as the CPU fetch instruction S3.
Therefore, when a registered bus event is detected, the CPU executes the instruction S3 registered in association with the detected bus event, regardless of the instruction address issued by the CPU itself.

A preferred example of the bus event is a final transfer access of a DMA transfer. That is, in the conventional information processing apparatus, the DMA activated by the CPU is
Completes a series (usually multiple) of data transfers,
, The end of the DMA transfer is notified by an interrupt. The CPU notified of the interrupt detects the device that issued the interrupt by polling the device associated with the asserted interrupt signal. However, as described above, the polling processing has a high processing cost and has been a cause of a decrease in real-time properties.
In the conventional information processing device, the polling process is required because it is not possible to prepare an interrupt signal enough to identify all exception events and CPU processing activation factors due to hardware resource restrictions. This is because events are aggregated and mapped.

When the DMA transfer is completed,
Since it is self-evident that an interrupt is notified when the final transfer access of the transfer is performed, the information processing apparatus of the present invention directly detects a bus event, thereby eliminating the need to map an event to an interrupt. Therefore, a polling process is not required for a registered event. In addition, by registering a part of the event processing routine in the event instruction issuing unit 3 at the time of starting the process of issuing the event, the event is immediately detected when the event is detected. It is possible to shift to event processing and improve real-time properties.

Next, FIG. 2 is a block diagram showing the configuration of the event instruction issuing unit 3 of the information processing apparatus of the present invention and its peripherals. Note that the same reference numerals are given to portions corresponding to FIG. In the figure, an event address EA from a bus interface 2 is supplied to an event address register 12. The event address register 12 holds the event address EA separately for a key portion K and a hash portion H, and stores the key portion K in the input A of the comparator 19.
And the hash portion H is supplied to one input terminal of the selector 15. The tag write register 13 receives a C
The bus event address supplied via the PU data bus IDB is separately stored in a key portion K and a hash portion H, and the key portion K is supplied to the tag array 17 so that the hash portion H
Is supplied to the other input terminal of the selector 15.

The instruction write register 14 sequentially stores event-related instructions from the CPU via the CPU data IDB under the control of the address decoder 10. In the present embodiment, the instruction write register 14 includes a plurality of instructions such as four consecutive instructions (hereinafter referred to as a line).
Can be held. When data is written to the tag write register 13 (at the time of registration operation), the selector 15
The hash portion H of the tag write register 13 is supplied to the hash decoder 16, and when the event address register 12 is written (at the time of issuing operation), the hash portion H of the tag write register 12 is supplied to the hash decoder 16.

The hash decoder 16 asserts an entry selection line corresponding to the hash part H, and
7. Select one of the instruction arrays 18. The tab array 17 includes a plurality of entries, and stores a key portion K supplied from the tag write register 13 at the time of registering an instruction. The instruction array 18 is composed of a plurality of entries like the tag array, and stores a plurality of instructions held in the instruction write register 14 in corresponding entries of the tag array 17.

The comparator 19 has a key part K from the event address register 12 and a key part K from the tag array 17.
Are compared, and if they match, the hit signal S5 is asserted. The latch 20 latches the hit signal S5,
The mode signal MS is supplied to the CPU address register 11, the instruction counter 22, and the selector 4. When the hit signal S5 is asserted, the instruction line buffer 21 latches the instruction line from the instruction array 18 and supplies it to the instruction selector 23.

When enabled by the mode signal MS, the instruction counter 22 counts up each time an instruction access is issued from the CPU. The instruction selector 23
According to the count value of the instruction counter 22, the event instruction S3 is selectively output from the output of the instruction line buffer 21. The selector 4 switches according to the state of the mode signal MS and normally outputs the cache output instruction S2 from the cache 1 in FIG. 1 as a CPU fetch instruction FI. When the mode signal MS is asserted, the selector 4 The latched event instruction S3 is output via the instruction selector 23.

B. Next, the operation of the above-described embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

B-1. Registration Operation First, a procedure for registering a bus event and an event-related instruction in the event instruction issuing unit 3 will be described. The registration of the bus event and the event-related instruction to the event instruction issuing unit 3 is performed before the CPU performs a process that may cause the event. Under the control of the address decoder 10, the CPU sequentially writes event-related instructions (a plurality of consecutive instructions such as four instructions: lines) to the instruction write register 14 via the CPU data bus IDB.

When the writing of the event-related instruction line to the instruction write register 14 is completed, the CPU writes the bus event address to the tag write register 13 via the CPU data bus IDB. It is assumed that the bus event address to be written includes the access type (read / write type, memory space type, I / O space type, etc.) of the bus event. For example, when data access of the system is performed in units of words (4 bytes), since the lower 2 bits of the CPU address are not related to the bus event, the access type is set in the lower 2 bits of the 32-bit CPU data. It is possible to include.

When data access of the system is performed in byte units, the number of bits corresponding to address bits not used in the address space including the bus event can be assigned to the access type. In this embodiment, the address / data length is 32 bits,
It is assumed that the system accesses in units of words, the event-related instruction line length is 4 words, and the tag array 17 and the instruction array 18 inside the event instruction issuing unit 3 each have 32 entries. However, each numerical value is an example, and the present invention is not limited to this.

Based on the above assumption, the tag write register 13
D0 and D1 of the CPU data to be written into the memory are unused, and here, the read / write type is indicated by D0. Since there are 32 tag entries, when the content of the tag write register 13 is divided into a hash portion H and a key portion K, the hash portion H becomes D6 to D2 so that 32 entries can be decoded, and the key portion K becomes D31 to D31.
D7 + D0.

When writing to the tag write register 13 is performed, the selector 15 is switched, and the hash portion H of the tag write register 13 is input to the hash decoder 16. The hash decoder 16 asserts an entry selection line corresponding to the hash portion H, and selects one of the tag array 17 and the instruction array 18. The key portion K of the tag write register 13 is written in the selected tag array 17, and a plurality of instructions held in the instruction write register 14 are collectively written in the corresponding entry of the selected instruction array 18. .

With the above operation, a bus event and an event-related instruction line can be registered in the event instruction issuing means 3.

B-2. Issue Operation Next, a process of detecting a bus event and a process of issuing the event instruction S3 will be described. The address bus AB is always
Event instruction issuing unit 3 via bus interface 2
When an event registered on the tag array 17 occurs on the address bus AB, the event address EA is supplied to the event address register 12. The output of the event address register 12 is divided into a key portion K and a hash portion H. The hash portion H is supplied to a hash decoder 16 via a selector 15, and the key portion K is supplied to an input A of a comparator 19. .

In the hash decoder 16, the hash part H
Is decoded, and one of the entry select lines is asserted. In the tag array 17, the content stored from the entry corresponding to the asserted entry selection line is read and supplied to the input B of the comparator 19. In the instruction array 18, the stored instruction line is read from the entry corresponding to the asserted entry selection line, and supplied to the instruction line buffer 21.

The comparator 19 compares the key K from the event address register 12 with the key K from the tag array 17. When the two match, the hit signal S5 is asserted, and the instruction line from the instruction array 18 is latched by the instruction line buffer 21 at the same time. The hit signal S5 is latched by the latch 20,
It is transmitted as a mode signal MS. When the mode signal MS is asserted, the selector 4 switches, and normally, the CP 4
Instead of the cache output instruction S2 output as the U fetch instruction FI, the event instruction S3 latched in the instruction line buffer 21 is output via the instruction selector 23.

The event instruction S3 is obtained by selectively outputting the output of the instruction line buffer 21 by the instruction selector 23 in accordance with the instruction counter 22. The instruction counter 22 enabled by the mode signal MS receives an instruction access from the CPU. Counted up every time. Therefore, the event instruction S3 is output as the CPU fetch instruction FI in order from the instruction line latched in the instruction line buffer 21. When the mode signal MS is asserted, the CPU address ADD is set in the CPU address register 11.

In the event processing, first, the address of the event processing routine for processing the detected event is set to CP.
The instruction address is changed so as to be set in the U address register 11. In the present embodiment, the instruction line registered in the instruction array entry is assumed to be four instruction lengths. However, in practice, it is necessary to have an instruction length at least capable of performing the above-described instruction address change. It is not limited.

When the content of the CPU address register 11 is changed to the event processing routine address, the CPU can execute the event processing as the normal mode processing. Therefore, in the subsequent processing, the contents of the CPU address register 11 holding the normal processing interruption address are read out and saved in the register or the memory for returning to the normal processing later, and then the latch 20 is cleared. Performs a dummy access to the address assigned to the memory cell and clears the latch 20, thereby negating the mode signal MS. When the mode signal MS is negated, C
The cache output instruction S2 is output to the PU fetch instruction FI. At this time, since the address of the event processing routine is already set in the CPU address register 11, the event processing routine is executed as the normal mode processing. Will be executed.

In the above-described embodiment, one example of the tag array 17 and the instruction array 18 is shown, but a plurality of sets of the tag array 17 and the instruction array 18 may be provided. The degree of association with the address EA is improved, and a plurality of event addresses having the same D6 to D2 can be registered.

In other words, as described above, when the tag array 17 and the instruction array 18 are each one set, D
Since it is not possible to register a plurality of event addresses having the same 6-D2, it is necessary to manage the events to be registered by software.

In the above-described embodiment, the tag array 17 and the instruction array 18 are assumed to have 32 entries. However, the present invention is not limited to this, and any number of events that may occur simultaneously can be registered. May be.

[0034]

As described above, according to the present invention, a series of a plurality of instructions related to a plurality of bus events is held in the holding means, and the bus event is detected by the bus event monitoring means. And by the event instruction issuing means, in place of the normal instruction, held in the holding means,
Since a series of multiple instructions corresponding to the detected bus event are output to the arithmetic means, polling processing becomes unnecessary, real-time performance of event processing can be improved, and efficient execution can be achieved. The advantage that it can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a partial configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an event instruction issuing unit 3 and its peripherals of the information processing apparatus of the present invention.

[Explanation of symbols]

ADD instruction address 1 cache (instruction output means) 2 bus interface (bus event monitoring means) 3 event instruction issuing unit (holding means, event instruction issuing means, writing means) 4 selector (switching means) FI fetch instruction (instruction)

Claims (4)

[Claims] 1. An arithmetic unit for outputting an instruction address and executing an instruction corresponding to the instruction address, a bus event monitoring unit for monitoring a bus event, and holding a series of a plurality of instructions related to a plurality of bus events. An event instruction issuing unit that, when a bus event is detected by the bus event monitoring unit, outputs a series of plural instructions corresponding to the detected bus event to the arithmetic unit when the bus event is detected by the bus event monitoring unit. And an information processing apparatus. 2. The method according to claim 1, wherein the series of instructions change an instruction address of the arithmetic unit, and store an address of a processing routine to be executed by the arithmetic unit in response to a detected bus event, in an address register of the arithmetic unit. 2. The information processing apparatus according to claim 1, wherein the set of instructions is a set of instructions. 3. The information processing apparatus according to claim 1, further comprising a writing unit that writes a series of a plurality of instructions related to the bus event into the holding unit before the occurrence of the bus event. 4. An instruction output means for outputting an instruction corresponding to an instruction address output by said arithmetic means, and an instruction output from said instruction output means when no bus event is detected by said bus event monitoring means. Selectively supplying the arithmetic means, and when a bus event is detected by the bus event monitoring means,
2. The information processing apparatus according to claim 1, further comprising: a switching unit that selectively supplies a series of plural instructions output from the event instruction issuing unit to the arithmetic unit.