JPH11231288A - Matrix type color liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent color slurring caused by the use of antiferrodielectric liquid crystal by correcting display colors in addition to the colors of input video data for each of R, G and B so as to match the colors of input video data in pite of a change in lightness. SOLUTION: Respective voltages corresponding to the respective colors R, G and B of input video data are set by regulating the refraction factor anisotropy of antiferroelectric liquid crystal and the R, G and B of respective transmission factors so as to eliminate the color slurring in the input video data. This device is provided with a video data correcting means (frame memory circuit 20 and video data correcting circuit 30) for correcting the video data so as not to generate color slurring corresponding to the change of refractive index anisotropy. Then, an electrode driving control means (control circuit 40, signal electrode driving circuit 50 and scanning electrode driving circuit 60) outputs both the corrected video data due to the video data correcting means as two pieces of video data while containing them in impression voltages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type color liquid crystal display device using a liquid crystal such as an antiferroelectric liquid crystal whose brightness is changed by a refractive index anisotropy.

[0002]

2. Description of the Related Art Conventionally, in a matrix type color liquid crystal display device using a liquid crystal panel having a built-in antiferroelectric liquid crystal, the voltage applied to the liquid crystal panel is changed to red (R),
The modulation is performed in accordance with the input video data of green (G) and blue (B), and by controlling the ratio of the area corresponding to the bright state and the area corresponding to the dark state of the antiferroelectric liquid crystal, the halftone is controlled. There is one that is displayed (for example, see Japanese Patent No. 2502879).

[0003]

In the above color liquid crystal display device, the bright state of the antiferroelectric liquid crystal is a ferroelectric state, and the dark state of the antiferroelectric liquid crystal is an antiferroelectric state. By controlling the mixing ratio of these regions in the ferroelectric state and the antiferroelectric state, halftone display is performed.

However, the antiferroelectric liquid crystal has a unique property that the refractive index anisotropy is different between the antiferroelectric state and the ferroelectric state. For this reason, the wavelength dependence of the light transmittance changes due to a change in the mixing ratio between the region in the antiferroelectric state and the region in the ferroelectric state. Therefore, there is a problem that the display color is shifted from the color required for the input video data depending on the brightness.

Therefore, the present inventors have examined this point in detail. In an antiferroelectric liquid crystal, the difference between the long-axis direction refractive index and the short-axis direction refractive index of the liquid crystal molecules corresponds to the refractive index anisotropy. Here, the liquid crystal molecule arrangement in the antiferroelectric state of the antiferroelectric liquid crystal generally has a zigzag shape. On the other hand, the liquid crystal molecule arrangement in the ferroelectric state of the antiferroelectric liquid crystal is generally aligned in the same direction.
Therefore, it is considered that the refractive index anisotropy of the antiferroelectric liquid crystal takes a larger value in the ferroelectric state than in the antiferroelectric state.

Also, the refractive index anisotropy of the antiferroelectric liquid crystal in the case of halftone is considered to be determined by the mixed state of the ferroelectric state and the antiferroelectric state. It takes a value between the refractive index anisotropy in the dielectric state and the refractive index anisotropy in the ferroelectric state. The refractive index anisotropy is
It is also determined by a transition state from an antiferroelectric state that is not clearly divided into regions to a ferroelectric state.

[0007] When a study was made on how each of the spectral transmittances of R, G, and B changes due to a change in the wavelength of light, a plurality of graphs L1 to L5 as shown in FIG. 10 are obtained. Was. Each of these graphs was obtained by using the following equation (1) and using the optical path length in the antiferroelectric liquid crystal as a parameter.

[0008]

T = (sin ² 2θ) sin ² (πΔn · d / λ) Here, T represents a spectral transmittance. θ represents the angle of the exit-side polarizing plate of the liquid crystal panel with respect to the optical axis of the antiferroelectric liquid crystal (the liquid crystal molecule long axis). Λ represents the wavelength of light incident on the liquid crystal panel. Further, Δn represents the refractive index anisotropy of the antiferroelectric liquid crystal, d represents the thickness of the antiferroelectric liquid crystal (the cell gap of the liquid crystal panel), and Δn · d represents the antiferroelectricity with respect to the cell gap. It represents the optical path length in the crystalline liquid crystal.

In FIG. 10, each of graphs L1 to L5
Are Δn · d = 0.20 μm and 0.25 μm, respectively.
m, 0.30 μm, 0.35 μm, and 0.40 μm are obtained as parameters. According to these, R,
Each of the spectral transmittances T of G and B, that is, the wavelength dependence is Δn ·
d, in other words, it depends on the brightness. FIG. 11 shows this point using a chromaticity diagram. In this figure, points P1 to P5, which are the results when the C light source is the incident light, are respectively Δn · d = 0.20
μm, 0.25 μm, 0.30 μm, 0.35 μm,
The chromaticity is obtained by using 0.40 μm as a parameter. According to this, it can be seen that the chromaticity changes from blue to yellow as Δn · d, that is, the brightness increases.

This means that the chromaticity changes from blue to yellow because the spectral transmittances of R, G, and B light change with Δn · d, in other words, as the brightness increases. Means to do. Note that the point P0 represents the chromaticity of the C light source that is the incident light. As described above, when the antiferroelectric liquid crystal is used, the display colors of the liquid crystal panel are changed because the respective spectral transmittances of R, G, and B change with the change in the refractive index anisotropy.
Depending on the change in the brightness of the halftone, which is determined by the mixing ratio between the region in the antiferroelectric state and the region in the ferroelectric state, the color required for the input video data cannot be maintained. It is understood that color shift occurs.

On the other hand, the present inventors have further studied various measures for eliminating the above-described color shift. As a result, attention is paid to the fact that one of a plurality of pixels in a matrix of a liquid crystal panel incorporating an antiferroelectric liquid crystal constitutes a minimum unit of an image composed of R, G and B, and the antiferroelectric liquid crystal is used. Is corrected in consideration of the color of the input video data for each of R, G, and B such that the display color matches the color of the input video data regardless of the change in brightness. It has been conceived that the occurrence of the above-described color shift can be prevented.

In view of this, the present invention is based on such a viewpoint, and the display color of a liquid crystal panel having a built-in liquid crystal of which brightness changes due to refractive index anisotropy such as antiferroelectric liquid crystal is changed from the color of input video data. An object of the present invention is to provide a matrix type color liquid crystal display device in which at least one of R, G, and B is corrected so as not to shift.

[0013]

In order to solve the above problems, according to the first to third aspects of the present invention, the matrix type color liquid crystal display device comprises a plurality of scanning electrodes (Y1 to Yn) and a plurality of scanning electrodes (Y1 to Yn). And a liquid crystal interposed between the scanning electrodes and the signal electrodes so as to form a plurality of matrix-shaped pixels. A liquid crystal panel (10) including a liquid crystal (10c) that changes according to a voltage applied between the scanning electrode and the signal electrode;
Electrode drive control means (40, 50, 6) for driving and controlling the scan electrodes and the signal electrodes by including at least one of the video data of B in the applied voltage and outputting the same.
0), and the plurality of pixels perform a matrix display in accordance with the drive control of the electrode drive control means.

The color liquid crystal display device includes image data correction means (20, 30) for correcting the image data for each pixel so as not to cause a color shift according to the change in the refractive index anisotropy. The electrode drive control means outputs both the corrected video data by the video data correction means as the two video data included in the applied voltage. Thereby, even if the liquid crystal changes the refractive index anisotropy during halftone, the video data is corrected for each pixel according to the change in the refractive index anisotropy so that color shift does not occur. Become. Therefore, the display of the liquid crystal panel can favorably maintain the color required for the color of the video data.

Here, as in the second aspect of the present invention,
The image data correction means includes a frame memory means (20) for receiving and storing the image data, and a correction means for correcting the image data stored in the frame memory means for a color shift caused by a change in the refractive index anisotropy. A correction means (30) for correcting each pixel in accordance with the change in the refractive index anisotropy using data may be provided.

[0016] Thereby, the function and effect of the invention described in claim 1 can be further satisfactorily ensured. According to the third aspect of the invention, the correction data is formed so that there is no difference between the video data and reference data determined to display a predetermined color. Thereby, the operation and effect of the invention described in claim 2 can be further improved.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall circuit configuration of a matrix type color liquid crystal display device according to the present invention.

This color liquid crystal display device is shown in FIGS.
As shown in the figure, a liquid crystal panel 10 is provided. This liquid crystal panel 10 has an antiferroelectric liquid crystal 10c sealed between the two electrode substrates 10a and 10b, and has the two electrode substrates 10a and 10b.
The polarizers 10d and 10e are attached to the outer surfaces of a and 10b. The electrode substrate 10 a has a transparent glass substrate 11. On the inner surface of the glass substrate 11, there are m color filter layers 12 (made of R, G, B) and m transparent conductive films 13. And an alignment film 14 are sequentially formed. On the other hand, the electrode substrate 10b has a transparent glass substrate 15, and on the inner surface of the glass substrate 15, an n-row transparent conductive film 16 and an alignment film 17 are sequentially formed.

Here, m transparent conductive films 13 and n transparent conductive films 16 are formed together with the antiferroelectric liquid crystal 10c as shown in FIG.
Are arranged so as to intersect with each other so as to form m × n pixels Gmn. The m transparent conductive films 13 correspond to the m signal electrodes X1 to Xm shown in FIG. 1, while the n transparent conductive films 16 correspond to the n scan electrodes Y1 shown in FIG. To Yn.

The two polarizing plates 10d and 10e are attached so that their optical axes are set at the positions of crossed Nicols. Thereby, the antiferroelectric liquid crystal 10c is extinguished in its antiferroelectric state. In addition, both electrode substrates 10
The interval between a and 10b is maintained uniformly at, for example, 2 μm by a large number of spacers (not shown). The color liquid crystal display device has a control circuit E as shown in FIG.
It has.

The control circuit E includes a frame memory circuit 2
0, the video data correction circuit 30, and the control circuit 4
0. The control circuit 40 receives a horizontal synchronization signal and a vertical synchronization signal from outside. Then, the control circuit 40 repeatedly generates the clock signals CL1 to CL7 in this order. Further, the control circuit 40 generates the address signals AD1 to AD3 in this order. Further, the control circuit 40 generates a write signal WEN, a read signal REN, and a write / read signal EN. Further, the control circuit 40 generates a field signal FI for selecting the polarity of the voltage. The control circuit 40 has five types of voltage levels (V1, V2, -V2, V
3, -V3) corresponding to three-bit scanning signals D1, D
2. Generate D3.

As shown in FIG. 3, the frame memory circuit 20 includes an R frame memory 21, a G frame memory 22, and a B frame memory 23. When the write signal WEN from the control circuit 40 is at a high level, the frame memory 21 receives a video signal (hereinafter, referred to as an R video signal) representing R video data (hereinafter, referred to as video data R) from the outside, and performs control. Circuit 4
The video data R for one screen is stored in an area specified by the address signal AD1 from the control circuit 40 in synchronization with the clock signal CL4 from 0.

When the write signal WEN from the control circuit 40 is at a high level, the frame memory 22 receives a video signal (hereinafter, referred to as G video signal) representing G video data (hereinafter, referred to as video data G) from the outside. The address signal AD1 from the control circuit 40 is synchronized with the clock signal CL4 from the control circuit 40.
The video data G for one screen is stored in the area specified by.

When the write signal WEN from the control circuit 40 is at a high level, the frame memory 23
Receives a video signal (hereinafter, referred to as B video signal) representing the video data of B (hereinafter, referred to as video data B) from the outside, and synchronizes with the clock signal CL4 from the control circuit 40 to receive the video signal. The video data B for one screen is stored in the area specified by the address signal AD1.

When the read signal REN from the control circuit 40 is at a high level, the frame memory 21
Outputs one horizontal line of video data R for one screen from an area designated by the address signal AD2 from the control circuit 40 in synchronization with the clock signal CL5 from the control circuit 40. Control circuit 40
When the read signal REN from the control circuit 40 is at a high level, the frame memory 22 synchronizes with the clock signal CL4 from the control circuit 40 and reads the video data G for one screen from the area specified by the address signal AD2 from the control circuit 40. Is output for one horizontal line.

When the read signal REN from the control circuit 40 is at a high level, the frame memory 23
Outputs one horizontal line of video data B for one screen from an area designated by the address signal AD2 from the control circuit 40 in synchronization with the clock signal CL4 from the control circuit 40. Video data correction circuit 3
0 has a correction ROM 31 for R, a correction ROM 32 for G, and a correction ROM 33 for B as shown in FIG.

[0027] Correction ROM31, the video signal level correction data A _R of FIG. 7 are stored in advance. The correction R
The OM 32 stores the video signal level correction data _{AG of} FIG. 7 in advance. Further, the correction ROM33, the video signal level correction data A _B 7 are stored in advance. The correction ROM 31 stores the control circuit 40
Synchronization of the clock signal CL6, (hereinafter referred to as output data R) output data based on the output data of the frame memory 21 from the video signal level correction data A _R determined.

The correction ROM 32 includes a control circuit 40
In synchronization with the clock signal CL6, output data (hereinafter referred to as output data G) is determined from the video signal level correction data _AG based on the output data of the frame memory 22.
The correction ROM33 is synchronized with the clock signal CL6 control circuit 40 determines the output data based on the video signal level correction data A _B output data of the frame memory 23 (hereinafter referred to as output data B).

Here, the basis for deriving each of the video signal level correction data A _R , A _G , and A _B will be described. As can be seen from the description at the beginning of this specification, even if the brightness of the display of the liquid crystal panel, that is, the luminance changes, the color shift of the display color from the color of the input video data, that is, the chromaticity In order to eliminate the change, the ratio of R, G, B may be kept constant even if the brightness changes.

Specifically, a graph L1 (Δn ·
d = 0.2 μm), the spectral transmittance T
Becomes larger in the order of R, G, and B. Therefore, for example, when the color of the input video data is white and R, G,
If it is assumed that white is obtained when the spectral transmittances of B are equal to each other, the spectral transmittance of B at Δn · d = 0.2 μm is used as it is, and the spectral transmittances of G and B What is necessary is just to correct each Δn · d and transmittance of G and B so as to match the spectral transmittance at Δn · d = 0.2 μm. With this correction, even if the refractive index anisotropy of the antiferroelectric liquid crystal changes depending on the brightness, the display color of the liquid crystal panel can be made to match the color required by the input video data.

Therefore, in this embodiment, the voltage of each pixel is changed to the color of the input video data (that is, R, G, B
Of the input video data, and the voltages corresponding to the R, G, and B of the input video data are adjusted for each pixel without deviation from the color of the input video data. The refractive index anisotropy of the antiferroelectric liquid crystal and the transmittance of each of R, G, and B are adjusted as described above.

Therefore, first, under the above-mentioned configuration of the liquid crystal panel, the level of the input video signal and the output relative luminance in one pixel are not corrected for the change in the refractive index anisotropy of the antiferroelectric liquid crystal. The relationship was measured as data for each of R, G, and B. FIG. 8 illustrates the relationship between the level of the input video signal and the output relative luminance in the case of R. The output relative luminance indicates the relative luminance when viewing the display surface of the liquid crystal panel, and corresponds to the voltage specifying θ and Δn · d in Expression (1).

Then, data representing the relationship between the level of the input video signal and the output relative luminance for each of R, G, and B is referred to as reference data S (FIG. 9) showing the relationship between the level of the input video signal and the reference output relative luminance. ) To derive the respective video signal level correction data A _R , A _G , and A _B. For example,
In FIG. 8, the level 128 at R of the input video signal is Δ Δ
Unless affected by the change of n · d, the output relative luminance 50
%, The level 128 becomes 30% due to the change of Δn · d. Therefore, in order to eliminate the color shift, the level of the input video signal at R is increased to a level corresponding to the output relative luminance of 50%, for example, 150. In other words, the actual transmittance of the antiferroelectric liquid crystal is corrected until the level 150 at R of the input video signal corresponds to the output relative luminance of 50%.

Then, the spectral transmittance determined by the thus corrected refractive index anisotropy, that is, the output relative luminance is obtained. As a result, for example, the data indicating the relationship between the level of the input video signal and the output relative luminance in FIG. 8 is matched with the reference data S in FIG. 9 as a result. Hereinafter, such a process is repeated for each of _R , _G , and _B to derive the video signal level correction data A _R , A _G , and A _B.

When the write / read signal EN from the control circuit 40 is at a high level, the line memory 31a
The output data R of the correction ROM 31 is synchronized with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as the head address.
Is stored. When the write / read signal EN from the control circuit 40 is at a high level, the line memory 32b
The output data G of the correction ROM 32 is synchronized with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as the head address.
Is stored.

When the write / read signal EN from the control circuit 40 is at a high level, the line memory 33a
The output data B of the correction ROM 33 is synchronized with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as the head address.
Is stored. When the write / read signal EN from the control circuit 40 is at a low level, the line memory 31a
Outputs the output data R to the DA converter 3 in synchronization with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as the head address.
1b.

When the write / read signal EN from the control circuit 40 is at a low level, the line memory 32a
Outputs the output data G in synchronization with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as the head address.
2b. When the write / read signal EN from the control circuit 40 is at a low level, the line memory 33a outputs the output data B in synchronization with the clock signal CL7 from the control circuit 40, using the address signal AD3 from the control circuit 40 as the head address. D-
Output to the A converter 33b.

The DA converter 31b includes a line memory 31
The output data a is converted into an analog signal and output to the polarity switching circuit 31c as analog data (hereinafter, analog data R). The DA converter 31b converts the output data of the line memory 32b into analog data and outputs the analog data (hereinafter referred to as analog data G) to the polarity switching circuit 32c. Also, the DA converter 33b is
The output data of the line memory 33a is converted into an analog signal and output to the polarity switching circuit 33c as analog data (hereinafter, analog data B).

When the field signal FI from the control circuit 40 is at a high level, the polarity switching circuit 31c
Outputs the analog data R of the DA converter 31b to the signal electrode drive circuit 50 with its polarity maintained. On the other hand, when the field signal FI from the control circuit 40 is at a low level, the polarity switching circuit 31c operates the DA converter 31
The polarity of the analog data R of b is inverted and output to the signal electrode drive circuit 50.

When the field signal FI from the control circuit 40 is at a high level, the polarity switching circuit 32c
Outputs the analog data G of the DA converter 32b to the signal electrode drive circuit 50 with its polarity maintained. On the other hand, when the field signal FI from the control circuit 40 is at a low level, the polarity switching circuit 32c operates the DA converter 32
The polarity of the analog data G of b is inverted and output to the signal electrode drive circuit 50.

When the field signal FI from the control circuit 40 is at a high level, the polarity switching circuit 33c
Outputs the analog data B of the DA converter 33b to the signal electrode drive circuit 50 with its polarity maintained. On the other hand, when the field signal FI from the control circuit 40 is at a low level, the polarity switching circuit 33 c
The polarity of the analog data B of b is inverted and output to the signal electrode drive circuit 50.

As shown in FIGS. 1 and 5, the signal electrode drive circuit 50 includes a shift register circuit 50a and an analog data latch circuit 50b. The shift register circuit 50a is configured by m shift registers. The analog data latch circuit 50b includes two-stage sample-hold circuits 51 and 52.

Here, the first stage sample and hold circuit 51
Are m sample-and-hold circuits SH11 to SH1m
The sample-and-hold circuit 52 at the subsequent stage includes m
Sample and hold circuits SH21 to SH2m. In the first stage sample and hold circuit 51,
m sample and hold circuits SH11 to SH1m
The analog data R, G,
B is the clock signal CL1 from the control circuit 40.
Are sequentially latched in response to the switching signal of the shift register circuit 50a generated in synchronism with. Then, the m sample and hold circuits SH11 to SH1m latch and hold data of one line.

In the sample-and-hold circuit 52 at the subsequent stage, m sample-and-hold circuits SH21 to SH2m
However, the data held by the first-stage sample-hold circuit 51 are sequentially latched in synchronization with the clock signal CL2 from the control circuit 40, and output as data signals to the signal electrodes X1 to Xm. The signal electrode drive circuit 50 repeats the above operation to generate a signal having a predetermined drive waveform and outputs the signal to each of the signal electrodes X1 to Xm.

As shown in FIG. 1, the scan electrode drive circuit 60 includes a shift register circuit 60a and a decoder switch circuit 60b. The shift register circuit 60a includes three stages of shift registers 61 to 63, as shown in FIG. Each of the shift registers 61 to 63 performs the following processing in synchronization with the clock signal CL3 from the control circuit 40. That is, the shift register 61 takes in the scanning signal D1 from the control circuit 40, the shift register 62 takes in the scanning signal D2 from the control circuit 40, and the shift register 63 takes in the scanning signal D3 from the control circuit 40.

The decoder switch circuit 60b includes n decoders DY1 to DYn and n switch circuits SY1
To SYn, and each switch circuit S
Y1 to SYn include five analog switches. The decoders DY1 to DYn decode the scanning signals D1 to D3 captured by the shift register circuit 60a, and scan voltage levels (V1 and V3) corresponding to the decoded data.
2, -V2, V3, -V2) corresponding to the respective switch circuits SY1 to SYn are closed. As a result, each of the switch circuits SY1 to SYn outputs the scan voltage level to each of the scan electrodes Y1 to Yn as a scan signal for erasing, selecting, and holding through the closed analog switch.

The scan electrode drive circuit 60 repeats the above operation to generate a signal having a predetermined drive waveform and output the signal to each of the scan electrodes Y1 to Ym. In the present embodiment configured as described above, when the R, G, and B video signals are input from outside, the frame memory circuit 20 receives the frame memories 21 to 23 of the frame memory circuit 20.
When the write signal WEN from the control circuit 40 is at a high level, the respective video data R, G,... Are stored in an area specified by the address signal AD1 from the control circuit 40 in synchronization with the clock signal CL4 from the control circuit 40. B is stored for one screen.

Next, when the read signal REN from the control circuit 40 goes high, each of the frame memories 21 to 23 is specified by the address signal AD2 from the control circuit 40 in synchronization with the clock signal CL5 from the control circuit 40. One horizontal line of video data R, G, B for one screen is output from the region to be processed.

Then, in the video data correction circuit 30, each of the correction ROMs 31 to 33 is stored in the control circuit 4
0, the respective video signal level correction data A _R , A _G , and A _B are synchronized with the clock signal CL 6 of the respective frame memories 21.
Output data R, G, B based on the output data of
To determine. After this determination, when the write / read signal EN from the control circuit 40 becomes high level, each of the line memories 31a to 33a
The output data R, G, and B of each of the correction ROMs 31 to 33 are stored in synchronization with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as a start address.

When the write / read signal EN from the control circuit 40 goes low, each of the line memories 31a to 33a synchronizes with the clock signal CL7 from the control circuit 40 using the address signal AD3 from the control circuit 40 as the head address. Then, each output data R, G, B is converted into each of the DA converters 31b to 33
b.

Accordingly, the DA converters 31b to 33b convert the output data of the line memories 31a to 33a into analog data and output the analog data R, G, and B to the polarity switching circuits 31c to 33c. Here, if the field signal FI from the control circuit 40 is at a high level, the polarity switching circuits 31c to 33c
c outputs the analog data R, G, and B of the DA converters 31b to 33b to the signal electrode drive circuit 50 while maintaining their polarities. On the other hand, if the field signal FI from the control circuit 40 is at a low level, the polarity switching circuit 3
1c to 33c invert the polarities of the analog data R, G, and B of the DA converters 31b to 33b and output the inverted data to the signal electrode driving circuit 50.

In the signal electrode driving circuit 50, m sample-and-hold circuits SH11 to SH1m in the sample-and-hold circuit 51 of the analog data latch circuit 50b are used.
Are analog data R from the video data correction circuit 30,
G and B are the clock signals C from the control circuit 40.
In response to the switching signal of the shift register circuit 50a generated in synchronization with L1, the data is sequentially latched, and data for one line is latched and held.

In the sample-and-hold circuit 52 at the subsequent stage, m sample-and-hold circuits SH21 to SH2m
Is used to transfer the data held by the sample and hold circuit 51 to the clock signal CL2 from the control circuit 40.
, And sequentially latch and output as data signals to each of the signal electrodes X1 to Xm. The signal electrode drive circuit 50 repeats the above operation to generate a signal having a predetermined drive waveform and outputs the signal to each of the signal electrodes X1 to Xm.

On the other hand, in the scan electrode driving circuit 60, the shift registers 61 to 63 of the shift register circuit 60a are
In synchronization with the clock signal CL3 from the control circuit 40, the scanning signals D1, D
2. Import D3. Then, the decoder switch circuit 6
0b decodes the scanning signals D1 to D3 taken into the shift register circuit 60a, and scans the scanning voltage levels (V1, V3) according to the decoded data.
2, -V2, V3, -V2) corresponding to the respective switch circuits SY1 to SYn are closed. As a result, each of the switch circuits SY1 to SYn outputs the scan voltage level to each of the scan electrodes Y1 to Yn as a scan signal for erasing, selecting, and holding through the closed analog switch.

The scan electrode drive circuit 60 repeats the above operation to generate a signal having a predetermined drive waveform and output the signal to each of the scan electrodes Y1 to Ym. As described above, the signal electrode drive circuit 50 outputs a signal of a predetermined drive waveform to each of the signal electrodes X1 to Xm, and the scan electrode drive circuit 60 outputs a signal of a predetermined drive waveform to each of the scan electrodes Y1 to Ym. Then, the content specified by each of the video data R, G, and B is displayed on the display surface of the liquid crystal panel 10.

Here, when the display content is displayed in halftone, the levels of the video signals R, G, and B are adjusted to the reference data based on the video signal level correction data A _R , A _G , and A _B in FIG. Correction is made so as not to deviate from S. Therefore, the output voltage level from the signal electrode driving circuit 50 to each of the signal electrodes X1 to Xm is adjusted so as to substantially correspond to the color specified by the level of each of the R, G, and B video signals. Becomes

Therefore, even if the refractive index anisotropy Δn of the antiferroelectric liquid crystal 10c is changed according to the change in the brightness of the halftone display, the display color of the liquid crystal panel 10 is not changed by the image data R, G,
It can be maintained well without deviating from the color required for B. In implementing the present invention, the liquid crystal panel 1
The liquid crystal used for 0 is not limited to an antiferroelectric liquid crystal, and a liquid crystal whose refractive index anisotropy changes depending on brightness may be used.

In practicing the present invention, the reference data S may be changed as needed and implemented. For example, video data R, G, and B may be used as the reference data S. In implementing the present invention, R, G, B
The present invention is not limited to a matrix type color display device that performs full-color display using three colors of R, G, and B, and may be applied to a matrix type color display device that performs color display using two colors among R, G, and B. .

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of a matrix type color liquid crystal display device according to the present invention.

FIG. 2 is a schematic sectional view of the liquid crystal panel of FIG.

FIG. 3 is a detailed block diagram of the frame memory circuit of FIG. 1;

FIG. 4 is a detailed block diagram of the video data correction circuit of FIG. 1;

FIG. 5 is a detailed block diagram of the signal electrode driving circuit of FIG. 1;

FIG. 6 is a detailed block diagram of a scan electrode driving circuit of FIG. 1;

FIG. 7 is a video signal level correction data diagram showing a relationship between an output for each of R, G, and B to a signal electrode driving circuit and a video signal level for each of R, G, and B;

FIG. 8 is a measurement data diagram showing a relationship between an output relative luminance and an R video signal level when correction by refractive index anisotropy is not taken into account.

FIG. 9 is a graph showing a relationship between a reference output relative luminance common to R, G, and B and a video signal level.

FIG. 10 is a graph showing the relationship between the spectral transmittance and the wavelength of light using Δn · d as a parameter.

FIG. 11 is a chromaticity diagram showing chromaticity determined by the spectral transmittance at each Δn · d in FIG. 10;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal panel, 10c ... Anti-ferroelectric liquid crystal, 20 ... Frame memory circuit, 30 ... Video data correction circuit, 40 ...
Control circuits, X1 to Xm: signal electrodes, Y1 to Yn: scanning electrodes.

Claims (3)

[Claims] A plurality of scanning electrodes (Y1 to Yn);
A liquid crystal interposed between a plurality of signal electrodes (X1 to Xm) and the plurality of scanning electrodes and the signal electrodes so as to form a plurality of matrix-shaped pixels. A liquid crystal panel (1) including a liquid crystal (10c) that changes according to a voltage applied between the scanning electrode and the signal electrode.
0), while driving the scan electrodes and the signal electrodes by outputting at least one of R, G, and B image data in the applied voltage while scanning the plurality of scan electrodes. A matrix-type color liquid crystal display device comprising electrode drive control means (40, 50, 60), wherein the plurality of pixels perform a matrix display in accordance with the drive control of the electrode drive control means; Video data correction means (20, 30) for correcting for each pixel so as not to cause a color shift according to the change in the refractive index anisotropy; A matrix type color liquid crystal display device, wherein corrected video data is output as the video data included in the applied voltage. 2. The image data correction means includes: a frame memory means (20) for receiving and storing the image data; and storing the image data stored in the frame memory means in accordance with a change in the refractive index anisotropy. 2. A matrix type color liquid crystal display according to claim 1, further comprising a correction unit (30) for correcting each pixel in accordance with a change in the refractive index anisotropy with correction data for correcting a color shift. Display device. 3. The matrix according to claim 2, wherein the correction data is formed so that there is no difference between the video data and reference data determined to display a predetermined color. Type color liquid crystal display device.