JPH11223930A - Phase shift mask for transmission type exposure and production of semiconductor integrated circuit device using this shift mask - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the occupying area of shared gate transistors(TRs). SOLUTION: The phase shift mask for transmission type exposure for production of semiconductor integrated circuit devices having the plural shared sense amplifies SA1 to SAn arrayed alone one direction and the plural shared gate TRs S1 to S2n arranged on both sides thereof has a mask substrate and a shading film having apertures transparent to light for exposure. The apertures of the shading film have gate wiring patterns for the shared gate TRs and auxiliary patterns arranged on both sides thereof. The phase of the light transmitting through the auxiliary patterns and the phase of the light transmitting through the gate wiring patterns are antiphases. The gate wiring patterns are transferred to fine patterns with small dimensional variations by the effect of the auxiliary patterns. The gate width of the shared gate TRs may, consequently, be shortened while the low leak current is maintained and, therefore, the occupying area of the shared gate TRs may be drastically reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift mask for transmission type exposure and a method for manufacturing a semiconductor integrated circuit device using the shift mask.

[0002]

2. Description of the Related Art With the improvement in the degree of integration of semiconductor integrated circuit devices, the size of circuit elements has been increasingly miniaturized. In the case of dynamic RAM (DRAM), as of 1997,
64-Mbit (Mbit) DRAMs designed based on the 0.25 μm rule have been mass-produced.
In 2000, production of 1 gigabit (Gbit) DRAM based on the 0.18 μm rule is scheduled to start.

FIG. 1 shows an example of an arrangement of a memory cell array and a sense amplifier. In the example shown in FIG. 1, the sense amplifier SA ₁ -SA _n and the sense amplifier SA ₁ on both sides of the memory cell array 1 '-SA _n' is arranged, the data line D ₁ to D _n and D ₁ 'to D _n' Is connected to the memory cells in the memory cell array via In the case of a 1 Gbit DRAM, since the area of one memory cell is about 0.3 μm ² , the arrangement pitch (cell pitch P) of the memory cells is required to be 0.4 μm or less. In FIG. 1, 4
The number of memory cells M _{1 to} M ₄ is schematically shown. As the cell pitch P decreases, the size H1 of _one sense amplifier measured along the Y direction also needs to be reduced.
If the sense amplifiers are arranged in a line only on one side of the memory cell array 1, the size H1 of _one sense amplifier measured along the Y direction is twice the cell pitch P (=
0.8 μm) or less, but it is difficult to form such a small sense amplifier. For this reason, as shown in FIG. 1, it is preferable to arrange sense amplifiers SA _{1 to} SA _n and sense amplifiers SA ₁ ′ to SA _n ′ on both sides of the memory cell array 1. As shown in FIG. 1, sense amplifiers SA _{1 to} SA _n and sense amplifiers SA ₁ ′ to SA _n ′
Are arranged in a line along the Y direction, respectively.
The size H _{1 of} one sense amplifier measured along the direction
Should be less than or equal to four times (= 1.6 μm) the cell pitch P.

On the other hand, in order to reduce the total number of sense amplifiers, as shown in FIG. 2, an arrangement method in which sense amplifiers are shared by two memory cell arrays is employed. Such a sense amplifier is called a “shared sense amplifier” or a “shared sense amplifier”. In the example of FIG. 2, each of shared sense amplifiers SA _{1 to} SA _n receives an output signal from the memory cells in memory cell arrays 1 and 2 arranged on both sides thereof and amplifies it. In a region 3 between the shared sense amplifiers SA _{1 to} SA _n and the memory cell array 1, shared gate transistors S _{1 to} S _2n are arranged, and a region 4 between the shared sense amplifiers SA _{1 to} SA _n and the memory cell array 2 , A shared gate transistor and S ₁ ′ to S _2n ′ are arranged.
On each side of each shared sense amplifier, two shared gate transistors are arranged.

When the shared gate transistors S _{1 to} S _2n in the region 3 are turned on, the shared gate transistors S ₁ ′ to S _2n ′ in the region 4 are turned off. On the other hand, when the shared gate transistors S _{1 to} S _2n in the region 3 are turned off, the shared gate transistors and S ₁ ′ to S _2n ′ in the region 4 are turned on. As described above, the shared gate transistors S _{1 to} S _2n and S ₁ ′ to S _2n ′ function as switching elements, so that one shared sense amplifier can amplify output signals from the two memory cell arrays, The total number of amplifiers is reduced.

[0006]

The shared sense amplifier system has the following problems.

The signal propagation speed between the memory cell array and the sense amplifier depends on the shared gate transistors S ₁ to S ₁ .
It largely depends on the driving ability of S _2n and S ₁ ′ to S _2n ′. Therefore, the shared gate transistors S _{1 to} S
There is a limit in reducing the channel width of _2n and S ₁ ′ to S _2n ′, and it is difficult to reduce the area occupied by regions 3 and 4. This will be described below.

FIG. 3 shows a planar arrangement of sense amplifiers SA ₁ and SA ₂ used in a ₁ Gbit DRAM and shared gate transistors S _{1 to} S ₄ in region 3. In the figure, shared gate transistors S ₁ to
The gate wiring 5 of the S ₄ hatched is applied.

In order to give each of the shared gate transistors S _{1 to} S ₄ a sufficiently large driving capability, the channel width H of each of the shared gate transistors S _{1 to} S ₄ is set.
₂ is the size H ₁ of each of the sense amplifiers SA ₁ and SA ₂
Is set to be larger than half. As a result, the shared gate transistors S _{1 to} S ₄ cannot be arranged in a line along the Y direction, but are arranged in a staggered manner in two lines as shown in FIG. Such a two-row arrangement is based on shared gate transistors S ₁ to S ₁ .
The S ₄ as compared to the case of arranging in a row along the Y direction,
This significantly increases the size of the region 3 in the X direction, which is inconvenient for improving the degree of integration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to manufacture a semiconductor integrated circuit device in which a plurality of shared gate transistors are compactly arranged on both sides of a shared sense amplifier. Providing a phase shift mask for transmission exposure,
Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device using the transmission type phase shift mask for exposure.

[0011]

A phase shift mask for transmission type exposure according to the present invention comprises a plurality of shared sense amplifiers arranged along one direction and a plurality of shared sense amplifiers arranged on both sides of the plurality of shared sense amplifiers. A phase shift mask for transmission type exposure for manufacturing a semiconductor integrated circuit device including a shared gate transistor, comprising: a mask substrate; and an opening formed in the mask substrate and transmitting light for exposure. A light-shielding film having a gate wiring pattern for the plurality of shared gate transistors, and auxiliary patterns disposed on both sides of the gate wiring pattern. The phase of the light passing through the pattern and the phase of the light passing through the gate wiring pattern are substantially opposite phases. Phase shifter is formed on the mask substrate.

In an exposure step for transferring the gate wiring pattern to a resist film, light transmitted through the auxiliary pattern gives the resist film an exposure amount less than an exposure amount required for transfer of the gate wiring pattern. The width of the auxiliary pattern is adjusted.

Preferably, the width of the auxiliary pattern is 0.16 μm or less on the resist.

[0014] The phase shifter may be constituted by a concave portion provided in the mask substrate.

[0015] The phase shifter may be constituted by a convex portion provided on the mask substrate.

The projection provided on the mask substrate may include:
It may be constituted by a film formed on the mask substrate.

The width of the gate wiring of the shared gate transistor is preferably 0.25 μm or less.

It is preferable that a main portion of the gate wiring pattern extends linearly along the one direction.

It is preferable that the phase shifter makes a difference between the phase of the exposure light transmitted through the auxiliary pattern and the phase of the exposure light transmitted through the gate wiring pattern 180 degrees.

A method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device using the above-mentioned phase shift mask for transmission type exposure, wherein a gate wiring of a plurality of shared gate transistors is formed on a semiconductor substrate. Depositing a thin film for, a step of forming a resist film on the thin film, using the transmission type phase shift mask for exposure, transferring a pattern for the gate wiring to the resist film, Is included.

Preferably, the step of transferring the pattern for the gate wiring to the resist film is performed under an exposure condition that does not transfer the auxiliary pattern to the resist film.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a phase shift mask for transmission type exposure according to the present invention will be described with reference to the drawings. FIG. 4 is a partial plan view of the phase shift mask of the present embodiment. FIG. 5 is an enlarged sectional view of the phase shift mask. This phase shift mask is used to manufacture a semiconductor integrated circuit device including a plurality of shared sense amplifiers arranged along one direction and a plurality of shared gate transistors arranged on both sides of the plurality of shared sense amplifiers. Used for

FIG. 4 shows four shared gate transistors S _{1 to} S ₄ located on one side of the two sense amplifiers, and the active region 101 of the shared gate transistors S _{1 to} S ₄ is schematically shown for simplicity. Is shown in In a region (not shown) of the phase shift mask, a wiring pattern other than the gate wiring pattern of the shared gate transistor may be formed. The pattern for the active region 101 is not actually formed on this phase shift mask, but is formed on a mask (not shown) for another layer.

The phase shift mask according to the present embodiment
The semiconductor device includes a gate wiring pattern 102 for a shared gate transistor, and auxiliary patterns 103 each having a width of 0.08 μm and arranged on both sides of the gate wiring pattern 102. The gate wiring pattern 102 has a region extending linearly in one direction, and a contact branch region 102a projecting vertically from the region. The gate wiring pattern 102 and the auxiliary pattern 103 are shown in FIG.
As shown in FIG. 2, the opening is defined by a light-shielding layer 51 made of chromium or the like formed on a translucent mask substrate (thickness: 0.25 inch, for example) 50. The portion of the mask substrate 50 where the auxiliary pattern 103 is formed is processed to be thinner than other portions of the mask substrate 50, as shown in FIG. As a result, the auxiliary pattern 103 functions as a “phase shifter” that substantially reverses the phase of the exposure light transmitted through the auxiliary pattern 103 and the phase of the exposure light transmitted through the gate wiring pattern 102. In the case of the present embodiment, the depth of the concave portion of the portion where the auxiliary pattern 103 is formed is adjusted so that the phase difference becomes 180 degrees. Specifically, the thickness of the mask substrate 50 is set to 0.25 inch, and the depth of the concave portion where the auxiliary pattern 103 is formed is set to about 244 nm. Instead of making the portion where the auxiliary pattern 103 is formed thinner than the other portions, a transparent thin film functioning as a “phase shifter” may be formed in the portion where the auxiliary pattern 103 is to be formed. The important point is that an optical path difference occurs between the gate wiring pattern 102 and the auxiliary pattern 103, and the gate wiring pattern 1
That is, the mask is provided with a structure that causes interference between the light transmitted through the second pattern 02 and the light transmitted through the auxiliary pattern 103.

FIG. 6 shows the relative transmission intensity distribution of the exposure light transmitted through the phase shift mask of FIG. 4 (this embodiment) and the relative transmission intensity distribution of the exposure light transmitted through the mask without the auxiliary pattern 103 (comparison). Example) is shown. These transmission intensity distributions correspond to light (wavelength: 248 n) from a KrF laser light source.
m) was determined by a light intensity simulator (ARIES) under the condition of using m) as exposure light. In order to perform quarter reduction projection exposure, the size of each pattern on the mask substrate is four times the size of the pattern to be transferred onto the semiconductor substrate. The width of the gate wiring pattern 102 in the phase shift mask of the embodiment is 0.22 μm × 4 = 0.8
8 μm, and the width of the gate wiring pattern in the mask of the comparative example is 0.25 μm × 4 = 1.0 μm.

As can be seen from FIG. 6, according to the phase shift mask of the present embodiment, light transmitted through the gate wiring pattern 102 is distributed in a narrower area than in the comparative example, and the absolute value of the slope of the intensity curve is relatively small. Large. This is because the light transmitted through the gate wiring pattern 102 and the light transmitted through the auxiliary pattern 103 interfere with each other, so that the pattern edge contrast is enhanced. In the case of the present embodiment, the distance between the gate wiring pattern 102 and the auxiliary pattern 103 is preferably 80 to 150 nm.

When the phase shift mask of this embodiment is used, the gate wiring pattern 10 transferred onto the semiconductor substrate
The dimensional variation of No. 2 was ± 20 nm. This is much smaller than the case where the dimensional variation when using the mask of the comparative example is ± 50 nm. As described above, according to the phase shift mask of the present invention, it is possible to reduce the size of the transfer pattern while reducing the dimensional variation.

The width of the auxiliary pattern 103 is 0.08 μm × 4 = 0.32 μm on the mask substrate.
It has a narrow width of 08 μm. For this reason,
Under the exposure conditions optimized for the gate wiring pattern 102, the light transmitted through the auxiliary pattern 103 does not sufficiently expose the resist and does not form a corresponding resist pattern. Auxiliary pattern 1 for light from KrF laser light source
In order to avoid the transfer of the resist 03, the width of the auxiliary pattern on the resist may be set to 0.16 μm or less.

Next, a method of manufacturing a semiconductor device using the phase shift mask will be described with reference to FIGS.

First, as shown in FIG. 7A, a gate insulating film 61 and a polycrystalline silicon film 62 are sequentially deposited on a semiconductor substrate 60 made of silicon or the like. Semiconductor substrate 60
, An impurity diffusion layer and an element isolation structure (not shown) are formed. Next, as shown in FIG. 7B, after forming a resist film (a negative resist having a thickness of 500 nm) 63 on the polycrystalline silicon film 62, a lithography process is performed using the mask substrate 50 including the pattern of FIG. I do. By this lithography step, a resist pattern 64 as shown in FIG. 7C is formed. Since the amount of light transmitted through the auxiliary pattern 103 is smaller than the required exposure value “threshold”, a resist pattern corresponding to the auxiliary pattern 103 is not formed after exposure and development. The exposure condition was 30 mJ / cm ² . FIG.
In (b), the transmission pattern on the mask substrate 50 and the exposure pattern of the resist 63 are described at the same magnification.
Actually, a quarter reduction projection exposure is performed. next,
The polycrystalline silicon film 62 is patterned using a dry etching method, thereby forming a gate wiring 65. At this time, the resist pattern 64 functions as an etching mask. After the resist pattern 64 is removed, impurity doping for source / drain formation is performed.

FIG. 8 shows the gate length dependence (short channel effect characteristics) of the threshold voltage (V _t ) of the gate transistor. When a transistor is formed using the mask of the comparative example, a target value (center value A) of the gate length is set to 0.
When the thickness is 25 μm, the minimum size of the gate length is 0.20 μm because the size variation is ± 50 nm.
On the other hand, when the transistor is formed using the phase shift mask of the present embodiment, even if the center value B of the gate length is 0.22 μm, the dimensional variation is ± 20 nm.
, The minimum dimension is suppressed to 0.20 μm. Leakage current of the transistor (subthreshold current), due to the short channel effect, maximized when the gate length is the minimum (threshold voltage V _t is the minimum). In the case of a semiconductor device including a plurality of transistors, if the leakage current of only one transistor exceeds a specified range, the semiconductor device (semiconductor chip) as a whole is defective. For this reason, regarding the leak current, the lower limit value of the dimensional variation of the transistors (the present embodiment) is not only reduced in the central value of the gate length but also so that the leak current of all the transistors falls within the allowable range. In this case, it is necessary to control 0.2 μm).

In the present embodiment and the comparative example, the minimum values of the gate lengths in consideration of the dimensional variation are equal.
There is no difference in (the maximum value of) the leakage current of the transistor. Therefore, according to the present embodiment, the gate length (center value) can be reduced while preventing an increase in leakage current. Since the reduction of the gate length (center value) increases the driving force of the transistor as a whole, according to the present embodiment,
Even if the gate width (channel width) is reduced, a necessary driving force can be secured.

[0033]

[Table 1]

Table 1 shows that the gate length (center value), threshold voltage V _t , saturation current I, and current required for driving (for example, 160 (Microamperes).

As can be seen from Table 1, according to the present embodiment, the gate length (center value) can be shortened and the saturation current can be increased, so that the gate width H ₂ can be reduced from 0.55 μm to 0.44 μm. It becomes possible to reduce. In the case of a DRAM having a cell pitch of 0.4 μm, the size H _{1 of the} sense amplifier (see FIG. 3) is 1.6 μm. For this reason,
When formed by the conventional manufacturing method, it was necessary to arrange a shared gate transistor S ₁ to S ₄ in accordance with the layout shown in FIG. 3, according to the manufacturing method of this embodiment,
As shown in FIG. 4, the shared gate transistor S ₁
To S ₄ can be linearly arranged. As a result, the area of the region for the shared gate transistor can be reduced by about 40% as compared with the related art.

Since the dimensional variation of a pattern formed by using a phase shift mask has a large pattern dependency, it is difficult to form a pattern using a phase shift effect over a wide range. In the present embodiment, the mask substrate 50
In the above, the auxiliary pattern 103 is provided only for the gate wiring pattern 102 for the shared gate transistor.
As a result, the required range of dimensional control due to pattern dependency can be reduced.

[0037]

According to the phase shift mask of the present invention, the size (center value) of the transfer pattern can be reduced by the auxiliary pattern while reducing the size variation. Therefore, when the minimum size of the plurality of transfer patterns defines the lower limit of the performance of the apparatus, the center value of the transfer pattern dimensions can be reduced while maintaining the lower limit of the apparatus performance. Therefore, according to the present invention, the size of the gate wiring pattern can be reduced without increasing the leakage current of the shared gate transistors disposed on both sides of the shared sense amplifier, and as a result, the size of the shared gate transistor can be reduced. , The occupied area can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing an arrangement example of a memory cell array and a sense amplifier.

FIG. 2 is a plan view showing a configuration of a shared sense amplifier or a shared sense amplifier.

3 is a plan view showing the arrangement of shared gate transistor S ₁ to S ₄ of the sense amplifier SA ₁ and SA ₂ and region 3 used 1GbitDRAM.

FIG. 4 is a partial plan view of an embodiment of a phase shift mask according to the present invention.

5 is an enlarged sectional view of the phase shift mask of FIG.

6 is a graph showing a relative transmission intensity distribution of exposure light transmitted through the phase shift mask of FIG. 4 and a relative transmission intensity distribution of exposure light transmitted through a mask obtained by removing an auxiliary pattern from the phase shift mask of FIG. 4; It is.

FIGS. 7A to 7C are process cross-sectional views illustrating a method for manufacturing a semiconductor device using the phase shift mask of the present invention.

FIG. 8 is a graph showing gate length dependence (short channel effect characteristics) of a threshold voltage (Vt) of a gate transistor.

[Explanation of symbols]

SA ₁ -SA _n sense amplifier S ₁ to S _2n shared gate transistor S ₁ 'to S _2n' shared gate transistor D ₁ to D _n data lines D ₁ 'to D _n' data lines 1 memory cell array 2 memory cell array 3 shared gate region where the transistor S ₁ to S _2n are arranged. 4 Area where shared gate transistors S ₁ ′ to S _2n ′ are arranged. Reference Signs List 5 gate wiring 50 mask substrate 51 light shielding film 60 semiconductor substrate 61 gate insulating film 62 polycrystalline silicon film 63 resist film 64 resist pattern 65 gate wiring 101 active region 102 gate wiring 103 auxiliary pattern

Claims (11)

[Claims] 1. A semiconductor integrated circuit device comprising: a plurality of shared sense amplifiers arranged along one direction; and a plurality of shared gate transistors arranged on both sides of the plurality of shared sense amplifiers. A transmission type phase shift mask for exposure, comprising: a mask substrate; and a light shielding film formed on the mask substrate and having an opening for transmitting light for exposure, wherein the opening of the light shielding film is It has a gate wiring pattern for a plurality of shared gate transistors and auxiliary patterns arranged on both sides of the gate wiring pattern, and has a phase of the light passing through the auxiliary pattern and transmitting through the gate wiring pattern. A phase shifter, which is formed on the mask substrate, has a phase shifter for causing the phase of the light to be substantially opposite to the phase of the light. Shift mask. 2. An exposure step for transferring the gate wiring pattern to a resist film, wherein light transmitted through the auxiliary pattern gives the resist film an exposure amount less than an exposure amount required for transferring the gate wiring pattern. 2. The transmission type phase shift mask according to claim 1, wherein the width of the auxiliary pattern is adjusted. 3. The transmission type phase shift mask according to claim 2, wherein the width of the auxiliary pattern is 0.16 μm or less on the resist. 4. The transmission type phase shift mask according to claim 1, wherein the phase shifter is constituted by a concave portion provided in the mask substrate. 5. The transmission type phase shift mask according to claim 1, wherein the phase shifter is constituted by a convex portion provided on the mask substrate. 6. The phase shift mask for transmission type exposure according to claim 5, wherein the projection provided on the mask substrate is constituted by a film formed on the mask substrate. 7. The phase shift mask according to claim 1, wherein the width of the gate line of the shared gate transistor is 0.25 μm or less. 8. The transmission type phase shift mask according to claim 1, wherein a main part of the gate wiring pattern extends linearly along the one direction. 9. The phase shifter according to claim 1, wherein a difference between a phase of the exposure light transmitted through the auxiliary pattern and a phase of the exposure light transmitted through the gate wiring pattern is 180 degrees.
3. The phase shift mask for transmission type exposure according to 1.). 10. A method of manufacturing a semiconductor integrated circuit device using the phase shift mask for transmission type exposure according to claim 1, wherein a gate wiring of a plurality of shared gate transistors is formed on a semiconductor substrate. Depositing a thin film for forming, a step of forming a resist film on the thin film, a step of transferring a pattern for the gate wiring to the resist film using the transmission type phase shift mask for exposure, A method for manufacturing a semiconductor integrated circuit device including: 11. The manufacturing of the semiconductor integrated circuit device according to claim 10, wherein the step of transferring the pattern for the gate wiring to the resist film is performed under exposure conditions that do not transfer the auxiliary pattern to the resist film. Method.