JPH11220142A - Manufacture of micro-device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the difference between the etching characteristics of a multilayer structure board and Si substrate by electrically connecting a structure film and support board during etching using at least electrically charged gas chemical species. SOLUTION: An oxide film 401 on a main surface of a first Si substrate 400 is patterned to form openings 406, a polysilicon film 402 is formed on a main surface of this structure, the polysilicon film 402 and a main surface of a second Si substrate 403 are laminated mutually and heat treated in an oxygen atmosphere to bond them, and the first Si substrate 400 is ground and polished into an SOI layer 404. On the SOI substrate, the SOI layer 404 is electrically connected to the second Si substrate 403 to be a support board by a polysilicon film 407 filled in the openings 406 of the oxide film 401. Thus the structure film is not electrically charged during etching using an electrically charged gas chemical species and the etching cam be made, the same as a usual Si substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a mechanical microdevice formed on a substrate material such as a semiconductor substrate.

[0002]

2. Description of the Related Art An example of a conventional method for manufacturing a microdevice using an SOI substrate (a thick polysilicon substrate is also possible) will be briefly described with reference to FIG. In the figures, (A) to (D) are cross-sectional views of the substrate, and (E) is a plan view of the main surface of the substrate. (A) Support substrate 100, embedded insulating film 101, and SOI
The SOI substrate 902 including the layer 102 is used, and the S
A high concentration impurity diffusion layer 900 is formed in a part of the OI layer 102 by an impurity diffusion or ion implantation technique. The buried insulating film 101 is a thermal oxide film in the case of a bonded SOI substrate.

(B) A PAD 903 is formed by sequentially forming a chromium film and a gold film on the main surface of the above-mentioned structure by a vapor deposition method, and patterning the chromium film and the gold film by a dry etching method. Note that the chromium film is a film provided to improve the adhesion of the gold film.

(C) An oxide film is formed on the main surface of
The oxide film mask 90 which is formed by the VD method and is patterned by the photo and dry etching methods to serve as an etching mask in the next step (D)
5 is formed. (D) A vertical opening 103 that penetrates the SOI layer 102 of the above structure and reaches the buried insulating film 101 is formed by RIE (reactive ion etching) using the oxide film mask 905 as an etching mask. (E) is a plan view of a main surface of the structure formed in the steps (A) to (D). The (a) cross-sectional view of (E) corresponds to the above (D). Note that 104 of the openings are etching holes.

Next, the above structure is immersed in an etching solution containing hydrofluoric acid such as buffered hydrofluoric acid for a long time, and the etching solution is made to penetrate through the opening 103 to form the buried insulating film 1.
01 is partially removed by sacrificial etching to obtain a microdevice having a free-standing structure. The oxide film mask 905 for trench etching is dissolved and removed at the same time as the sacrificial etching of the buried insulating film.

The structure after sacrificial etching will be described with reference to FIG. (A) is a plan view, (B) is (A).
Bb cross-sectional view, (C) is a cc cross-sectional view of (A),
(D) is a dd sectional view of (A). The buried insulating film immediately below the portion having the large area remains after the sacrificial etching, and becomes the fixing portions 120 and 121 or the frame portion 122. Reference numeral 113 denotes a thin portion whose both ends are connected to the fixing portions 120 and 121, and is a doubly supported beam. Reference numeral 115 denotes a thin portion having one end connected to the fixing portion 120, which is a cantilever. Further, a portion 114 is a movable weight, which is etched from the internal etching hole 104 to remove all the buried insulating film immediately therebelow, and is connected to the fixed portion 120 via the beam 116.

[0007] As described above, the microdevice has a doubly supported beam 11.
3, weight 114, cantilever 115, fixing parts 120, 12
Design is made by combining these with 1 as a main component. Examples of applications of such microdevices include:
For example, a so-called acceleration sensor that detects a vertical acceleration of the substrate by measuring a change in capacitance between the weight 114 and the support substrate 100 is realized.

For a similar manufacturing method, see, for example, a document (Yo
shinori Matsumoto, Moritaka Iwakiri, Hidekazu Tanak
a, “A Capacitive Accelerometer Using SDB-SOI Struc
ture ”, The 8th International Conference on Solid-
State Sensors and Actuators, and Eurosensors IX. S
tockholm Sweden, June 25-29, 1995, pp550-553).

As described above, in the conventional method for manufacturing a microdevice, a vertical opening reaching the buried insulating film of the SOI substrate is formed by RIE (for example, step D in FIG. 8). Since the etching characteristics of the RIE, that is, the etching selectivity between the mask material and silicon, the cross-sectional shape of the trench, etc. greatly depend on the master pattern, it is necessary to determine the conditions for each type of product to be manufactured and for each pattern improvement. In addition, since the parameters of the etching are various, a large number of silicon substrates are required for setting a large number of conditions. Note that it is difficult to form a vertical opening by etching with a normal etching solution, and it is not possible to form a minute device having an accurate shape and dimensions.

[0010]

However, the etching characteristics are different between a standard silicon substrate and a multi-layered substrate such as an SOI substrate, and even if the optimum conditions for performing the conditions performed using the silicon substrate are used. In addition, there is a problem that it is difficult to perform an optimum etching on a multilayer structure substrate such as an SOI substrate. In particular, as the thickness of the SOI layer increases, the difference in the cross-sectional shape of the trench increases. This is because the capacitance between the comb electrodes cannot be manufactured as designed, or the spring characteristics of the beam, that is, the microstructure. There was a problem that the vibration characteristics of the body could not be manufactured as designed. It is also conceivable to determine the etching conditions using the SOI substrate itself. However, the cost of the SOI substrate is about 10 times the price of the silicon substrate, and nearly 20 times depending on the structure. Is greatly increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and eliminates the difference between the etching characteristics of a multilayer structure substrate such as an SOI substrate and the etching characteristics of a silicon substrate. It is an object of the present invention to provide a method for manufacturing a microdevice that realizes optimal etching of a multilayer structure substrate using optimized etching parameter optimization conditions.

[0012]

According to the studies and experiments conducted by the present inventors, in a multilayer structure film having an intermediate insulating film such as an SOI substrate, the structural film (SOI layer) is moved from the supporting substrate to the insulating film. Is electrically insulated by
In etching using charged gaseous chemical species such as IE, it was discovered that the biggest cause was that the structural film was charged during etching and the potential of the portion being etched changed. . The present invention has been made based on the above findings, and basically, at least during etching using a charged gaseous species, by electrically connecting the structural film and the support substrate. Thus, the optimization condition of the etching parameter obtained by using the silicon substrate can be favorably applied to the multilayer substrate.

First, in the first aspect of the present invention,
Using a multilayer structure substrate in which at least a support substrate, an insulating film, and a structural film are laminated, an opening that penetrates the structural film and reaches the insulating film is formed by using a charged gaseous species.
Forming by the etching of the
Etching at least a part of the insulating film by etching.
The structure film is electrically connected to the support substrate at the time of etching. The first etching using the charged gaseous species refers to, for example, RI
Etching like E. Note that the above configuration corresponds to, for example, first, second, and third embodiments described later.

[0014] With the above configuration, since the structural film and the supporting substrate are electrically connected, the structural film is charged during the first etching using the charged gaseous species. Therefore, the etching is performed in the same manner as a normal silicon substrate. Therefore, it is possible to eliminate the difference between the etching characteristics of the multi-layer substrate such as the SOI substrate and the etching characteristics of the silicon substrate, and to optimize the multi-layer substrate using the etching parameters optimized using the silicon substrate. Optimum etching can be performed.

According to a second aspect of the present invention, the means for electrically connecting the structural film and the supporting substrate is formed inside the multilayer structure substrate in the step of forming the multilayer structure substrate. is there. This configuration corresponds to, for example, a first embodiment described later. The invention according to claim 3 shows a specific step in the manufacturing method according to claim 1 or 2.

According to a fourth aspect of the present invention, the portion for electrically connecting the structural film and the supporting substrate is formed at the die sink line of the multilayer structure substrate, and the dicing after forming the microdevice is performed. The part for electrically connecting the structural film and the support substrate is removed. As a result, there is no electrical connection between the structural film and the supporting substrate. This configuration corresponds to, for example, a first embodiment described later.

According to a fifth aspect of the present invention, the portion for electrically connecting the structural film and the supporting substrate is formed outside the dicing line on the outer peripheral portion of the multi-layer structure substrate, and after the formation of the micro device, Is separated from each chip by dicing. This configuration corresponds to, for example, a third embodiment described later.

According to a sixth aspect of the present invention, a part of the portion for electrically connecting the structural film and the supporting substrate is removed by dicing after forming the microdevice, and the other part is left as it is. In some cases, the electrical connection between the structural film and the supporting substrate is left. According to this configuration, the terminals connected to the support substrate can be provided on the front surface side of the multilayer structure substrate. This configuration corresponds to, for example, a second embodiment described later.

According to a seventh aspect of the present invention, after forming the multilayer structure substrate, a part of the structural film and the insulating film is removed to expose the surface of the support substrate, and the structural film is exposed from the exposed portion. A portion for electrically connecting the structure film and the support substrate is formed on the surface of the multilayer structure substrate by forming a conductive film over the substrate. This configuration corresponds to, for example, a third embodiment described later.

According to the invention described in claim 8, the portion for electrically connecting the structural film and the support substrate is formed on an etching jig provided outside the multilayer structure substrate. . This configuration corresponds to, for example, the matter described at the end of the detailed description of the invention.

[0021]

According to the present invention, the structure film and the supporting substrate are electrically connected to each other to eliminate the charge of the structure film.
It is possible to eliminate the difference between the etching characteristics of a multi-layer substrate such as an SOI substrate and the etching characteristics of a silicon substrate, and to optimize the multi-layer substrate using the etching parameter optimization conditions performed using the silicon substrate. Etching can be performed. Therefore, there is an effect that a microdevice as designed can be manufactured without increasing the process cost.

Further, if a portion for electrically connecting the structural film and the supporting substrate is provided in a region where a micro device is not formed, such as a dicing line or a peripheral portion of a wafer, a chip area does not increase and a rise in cost can be suppressed. Can be obtained.

Further, the buried insulating film has a large thermal resistance (about 200 times), so that the substrate temperature also rises during etching. However, since the connection portion provided in the present invention has good heat conduction,
There is also an advantage that a temperature rise can be avoided. According to the sixth aspect, in addition to the above effects, the electrodes of the support substrate can be taken out from the main surface side of the multilayer structure substrate, so that the electrodes on the back surface of the substrate become unnecessary and the mounting becomes easy. Is obtained.

According to the seventh and eighth aspects, in addition to the above-described effects, a multilayered substrate having a standard and simple structure (for example, an ordinary SOI substrate) can be used, and a buried structure can be used. Since there is no alignment of the pattern with the above, there is obtained an effect that the entire manufacturing process of manufacturing the microdevice becomes easy.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described first with reference to FIG.
1A to 1F are cross-sectional views. The dashed line in the figure (indicated at both ends of the figure) means the center of the dicing line, and the pattern in the figure is repeatedly formed in the wafer. (A) An oxide film 401 is formed on a main surface of a first silicon substrate 400.
Is formed to a thickness of 2 μm by a technique such as thermal oxidation, and the thermal oxide film 4 is formed by a photo and dry etching technique.
An opening 406 is provided by patterning 01.

(B) A polysilicon film 402 is formed on the main surface of the structure by a thickness of 10 μm by LP-CVD and normal pressure CVD, and the surface of the polysilicon film 402 is ground and polished. To make a flat mirror surface. Further, when the polysilicon film 402 is formed, an impurity gas is caused to flow simultaneously to introduce impurities into the polysilicon film 402. Alternatively, after forming the polysilicon film 402,
The impurity may be introduced by a technique such as impurity diffusion or ion implantation.

(C) The polysilicon film 402 on the main surface of the structure is superimposed on the main surface of the second silicon substrate 403, and is subjected to a heat treatment at 1100 ° C. for 1 hour in an oxygen atmosphere to be joined. I do. In (C), the structure of (B) is turned upside down. Then, the first silicon substrate 40
By grinding and polishing 0, the first silicon substrate 400 is formed into a 20 μm-thick SOI layer 404. The second silicon substrate 403 is a so-called support substrate of the SOI substrate, and the thermal oxide film 401 is a so-called buried insulating film of the SOI substrate.

Note that a thermal oxide film is formed on the back surface of the second silicon substrate by the above-described heat treatment in an oxygen atmosphere, and the thermal oxide film is removed with an etchant containing hydrofluoric acid.

Through the above steps (A) to (C), a bonded SOI substrate is formed. In this bonded SOI substrate, the SOI layer 404 is electrically connected to the second silicon substrate 403 as a support substrate by the polysilicon film 407 filling the opening 406 of the oxide film 401.

(D) SOI layer 404 on the main surface of the above structure
A high-concentration impurity diffusion layer 408 is formed in a part of the substrate by impurity diffusion or ion implantation. (E) A PAD 409 is formed by forming a chromium film and a gold film on the main surface of the structure by vapor deposition and patterning by photo and dry etching.

(F) An oxide film is formed on the main surface of
The oxide film mask 410 serving as an etching mask in the following etching process is formed by forming the film by the VD method and patterning by the photo and dry etching methods.

The description will be continued with reference to FIG. (A) is a sectional view and (B) is a plan view. (A) A vertical opening 411 that penetrates the SOI film 404 of the above structure and reaches the oxide film 401 that is a buried insulating film.
Is formed by RIE (reactive ion etching) using the oxide film mask 410 as an etching mask (first etching). The SOI layer 404 is formed of the polysilicon film 4 filled in the opening 406 of the oxide film 401.
07, the second silicon substrate 40 as a support substrate
Since it is electrically connected to No. 3, it is not charged during the etching process. Therefore, the optimum etching of the SOI substrate is realized under the optimum etching conditions obtained by using the silicon substrate.

When the opening formed by the etching reaches the buried insulating film, some parts may be electrically insulated from the supporting substrate depending on the pattern. However, the charging after the etching reaction of the SOI layer is completed. Therefore, it does not affect the etching characteristics such as the sectional shape of the opening. (B) It is a top view of the main surface of the above-mentioned structure. The cross section aa corresponds to the above (A). 412 of the openings are etching holes.

Next, the above structure is immersed in an etching solution containing hydrofluoric acid such as buffered hydrofluoric acid for a long time, and the etching solution penetrates through the opening 411 to form the buried insulating film 4.
02 is partially removed by sacrificial etching (second etching) to obtain a microdevice having a free-standing structure. The oxide film mask 410 for trench etching is dissolved and removed at the same time as the sacrificial etching of the buried insulating film.

Next, the structure after sacrificial etching and after dicing will be described with reference to FIG. FIG. 2A is a plan view, FIG. 2B is a cross-sectional view taken along line bb of FIG.
(C) is a cc cross-sectional view of (A), and (D) is d- of (A).
It is d sectional drawing. The buried insulating film immediately below the portion having the large area remains after the sacrificial etching, and the fixing portion 420 is formed.
421 or the frame part 422. 4
Reference numeral 23 denotes a thin portion having both ends connected to the fixing portions 420 and 421, and serves as a doubly supported beam. Reference numeral 424 denotes a thin portion having one end connected to the fixing portion 420, which is a cantilever. The portion 425 is a movable weight, and is etched from the internal etching hole 412 to remove all the buried insulating film immediately therebelow.
20.

The polysilicon film 407 filling the opening 406 of the oxide film 401 is removed as a shaving allowance during dicing. Accordingly, the electrical connection between the SOI layer 404 and the second silicon substrate 403 serving as the support substrate is released.

In this embodiment, a polysilicon layer is used as a portion for electrically connecting the SOI layer to the support substrate, and is provided along the dicing line inside the SOI substrate. Is also connected thermally. Therefore, there is also an effect of suppressing a rise in temperature of the SOI layer during etching, which contributes to reproducing the etching characteristics of a standard silicon substrate as it is in the SOI substrate of this embodiment.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. 4A to 4F are cross-sectional views. A dashed line (shown at the end of the figure) in the figure indicates the center of the dicing line, and the pattern shown in the figure is repeatedly formed in the wafer. This embodiment is the same as the first embodiment except that the pattern used is different from that of the first embodiment.

(A) An oxide film 501 is formed on the main surface of the first silicon substrate 500 by a method such as thermal oxidation to a thickness of 2 μm, and the thermal oxide film 501 is patterned by photo and dry etching. , An opening 506 is formed.

(B) On the main surface of the structure, a polysilicon film 502 is formed to a thickness of 10 μm by LP-CVD and normal pressure CVD, and the surface of the polysilicon film 502 is ground and polished. To make a flat mirror surface. When the polysilicon film 502 is formed, an impurity gas is caused to flow simultaneously to introduce impurities into the polysilicon film 502. Alternatively, after the polysilicon film 502 is formed, an impurity may be introduced by a technique of impurity diffusion or ion implantation.

(C) The polysilicon film 502 on the main surface of the structure is superimposed on the main surface of the second silicon substrate 503, and is subjected to a heat treatment at 1100 ° C. for 1 hour in an oxygen atmosphere to be joined. I do. After that, the first silicon substrate 50
0 is ground and polished, so that the first silicon substrate 500 is an SOI layer 504 having a thickness of 20 μm. The second silicon substrate 503 is a so-called support substrate of the SOI substrate, and the thermal oxide film 501 is a so-called buried insulating film of the SOI substrate. The heat treatment in an oxygen atmosphere causes the second
Since a thermal oxide film is formed on the back surface of the silicon substrate, it is removed with an etching solution containing hydrofluoric acid.

Through the above steps (A) to (C), a bonded SOI substrate is formed. In the bonded SOI substrate, the SOI layer 504 is electrically connected to the second silicon substrate 503 as a support substrate by the polysilicon film 507 filling the opening 606 of the oxide film 501.

(D) SOI layer 504 on the main surface of the above structure
A high-concentration impurity diffusion layer 508 is formed in part of the substrate by impurity diffusion or ion implantation.

(E) A chromium film and a gold film are sequentially formed on the main surface of the above structure by a vapor deposition method, and are patterned by photo and dry etching to form PAD 509 and PAD 530.

(F) An oxide film is formed on the main surface of
An oxide film mask 510 serving as an etching mask in the following etching step is formed by forming the film by the VD method and patterning by the photo and dry etching methods.

The description will be continued with reference to FIG. (A) is a sectional view and (B) is a plan view. (A) A vertical opening 511 that penetrates the SOI layer 504 of the above structure and reaches the oxide film 501 that is a buried insulating film.
Is formed by RIE using the oxide film mask 510 as an etching mask. The SOI layer 504 is
Since the polysilicon film 507 filled in the opening 506 of the oxide film 501 is electrically connected to the second silicon substrate 503 serving as a support substrate, it is not charged during an etching step. Therefore, the optimum etching of the SOI substrate is realized under the optimum etching conditions obtained by using the silicon substrate.

When the opening formed by etching reaches the buried insulating film 501, a part of the pattern may be electrically insulated from the supporting substrate.
Due to charging after the etching reaction of the OI layer is completed,
It does not affect the etching characteristics such as the cross-sectional shape of the opening. (B) It is a top view of the main surface of the above-mentioned structure. The cross section aa corresponds to the above (A). 512 of the openings are etching holes.

Next, the above-mentioned structure is immersed in an etching solution containing hydrofluoric acid such as buffered hydrofluoric acid for a long time to allow the etching solution to penetrate through the opening 511 and to bury the insulating film 5.
01 is partially removed by sacrificial etching to obtain a microdevice having a free-standing structure. The oxide film mask 510 for the trench etching is dissolved and removed at the same time as the sacrificial etching of the buried insulating film.

The structure after sacrificial etching and after dicing will be described with reference to FIG. 2A is a plan view, FIG. 2B is a cross-sectional view taken along line bb of FIG. 1A, and FIG.
(D) is a dd cross-sectional view of (A). The buried insulating film immediately below the portion having the large area remains after the sacrificial etching, and the fixing portions 520 and 52
1 or the frame part 522. Numeral 523 denotes a thin portion whose both ends are connected to the fixing portions 520 and 521, and serves as a doubly supported beam. 524 is a fixed part 520 at one end.
Is a thin part connected to a cantilever. 525
Is a movable weight, is etched from the internal etching hole 511 to remove all the buried insulating film immediately below, and is connected to the fixed part 520 via the beam 526.

The portion corresponding to the dicing line in the polysilicon film 507 filled in the opening 506 of the oxide film 501 is removed as a shaving allowance at the time of dicing. Therefore, of the electrical connection between the SOI layer 504 and the second silicon substrate 503 serving as the support substrate, a portion provided in the dicing line is released.

On the other hand, the polysilicon film 50 filled in the opening of the oxide film 501 in the region where the PAD 530 is formed
7 'remains without being removed, and the PAD 530 is electrically connected to the second silicon substrate 503. Therefore, PAD 530 is the second silicon substrate 5 serving as a support substrate.
It becomes a PAD for taking out the electrode 03. And PA
Since D509 is a PAD for taking out the electrode of the weight 525, measuring a change in capacitance between the PAD509 and the PAD530 realizes an acceleration sensor that detects acceleration applied in the vertical direction of the substrate. At this time,
It is not necessary to take out the electrode from the back surface of the substrate, such as forming a back electrode on the back surface of the support substrate.

In the present embodiment, similarly to the first embodiment, a portion for electrically connecting the SOI layer to the support substrate is formed of polysilicon by a dicing line and an electrode of the support substrate inside the SOI substrate. Since the SOI layer is provided in the take-out portion, the SOI layer is also thermally conductively connected to the supporting substrate, and has an effect of suppressing a temperature rise of the SOI layer during etching. Therefore, the etching characteristics of the standard silicon substrate are directly reproduced in the SOI substrate of the present embodiment.

(Third Embodiment) A third embodiment of the present invention will be described. In the first embodiment and the second embodiment, a portion for electrically connecting the SOI layer to the supporting substrate is provided in the step of forming the SOI substrate in the step of forming the SOI substrate.
It was formed by burying it inside the I substrate. However, in this embodiment mode, a normal SOI substrate in which the SOI layer is electrically separated from the supporting substrate is used, and a portion for electrically connecting the SOI layer to the supporting substrate is formed in a step of forming the SOI substrate. After that, an example is shown.

The operation will be described below with reference to FIG. Figure (A)
(D) is a sectional view. Although the step of forming the SOI substrate is omitted, the supporting substrate, the buried insulating film, and the SOI substrate are formed.
An ordinary SOI substrate on which an I layer is stacked can be used. (A) The SOI substrate 600 has an SOI
The layer and the buried insulating film 603 are partially chamfered, and the support substrate 604 is exposed. A high-concentration impurity diffusion layer 602 is formed on a part of the SOI layer 601 on the main surface of the SOI substrate 600,
S in a region 605 of the outer peripheral portion of the wafer (the portion outside the portion removed by the dicing line shown by the broken line)
A high-concentration impurity diffusion layer 606 is formed on the OI layer (601), and a high-concentration impurity diffusion layer 611 is formed on the support substrate 604 where the chamfered region 605 on the outer periphery of the wafer is exposed. Is formed. A portion 609 is a region where a microdevice is formed, and is repeatedly formed in the wafer surface. In addition, a chain line means a dicing line.

(B) A chromium film and a gold film are sequentially formed on the main surface of the above-mentioned structure by a vapor deposition method, and are patterned by photo and dry etching to form a PAD 607 on the high concentration impurity diffusion layer 602. And a wiring 608 for connecting the high-concentration impurity diffusion layers 606 and 611 in the chamfered region 605 on the outer peripheral portion of the wafer is formed. With this wiring 608, SOI
The layer 601 is electrically connected to the supporting substrate 604. Note that the chromium film is a film for improving the adhesion of the gold film as in the other embodiments.

(C) An oxide film is formed on the main surface of
An oxide film mask 61 serving as an etching mask in the following step (D) is formed by a VD technique and patterned by a photo and dry etching technique.
Form 2

(D) A vertical opening 613 penetrating through the SOI layer 601 of the above structure and reaching the buried insulating film 603
Is formed by RIE using the oxide film mask 612 as an etching mask. The SOI layer 601 is
Since it is electrically connected to the supporting substrate 604 by the wiring 608 provided in the chamfered region 605 on the outer peripheral portion of the wafer, it is not charged during the etching process.
Therefore, the optimum etching of the SOI substrate is realized under the optimum etching conditions obtained by using the silicon substrate.

When the opening formed by the etching reaches the buried insulating film, some portions may be electrically insulated from the supporting substrate depending on the pattern. However, the charge after the etching reaction of the SOI layer is completed. Therefore, it does not affect the etching characteristics such as the sectional shape of the opening.

Next, as in the first and second embodiments, the above structure is immersed in an etching solution containing hydrofluoric acid such as buffered hydrofluoric acid for a long time, and the etching solution enters through the opening 613. Then, the embedded insulating film 603 is partially removed by sacrificial etching to obtain a micro device having a free-standing structure.

Thereafter, the portion shown by the broken line in the figure is cut by dicing. As a result, the wiring 608 provided in the chamfered region 605 on the outer peripheral portion of the wafer is separated from each chip by dicing, and the electrical connection between the SOI layer 601 and the support substrate 604 is released. The structure of the formed micro device is the same as that of the first embodiment.

In the description of the first to third embodiments, specific examples have been described. However, the present invention is not limited to these numerical values and words, such as film thickness and film forming method, or figures. Not necessarily. Hereinafter, an example thereof will be described. First, the first
In the third embodiment, an SOI substrate in which the SOI layer is made of silicon has been described as an example. However, the present invention is not limited to this. The SOI layer is made of another semiconductor material, and in some cases, a metal material. Is also good.

Further, the support substrate is made of SOI
Although the substrate has been described as an example, the present invention is not limited to this, and the supporting substrate may be another semiconductor material, and in some cases, a metal material. Further, the material is not limited to a single structural material, and may be a composite material made of a semiconductor material, a metal material, or an insulating material.

In the case of forming an SOI substrate, the bonding of a polysilicon film and a silicon substrate has been described as an example. However, the present invention is not limited to this. May be bonded to a supporting substrate having the above-mentioned portion.

Although a thermal oxide film has been described as an example of the sacrificial layer, the present invention is not limited to this. Other sacrificial layer materials, for example, a buried oxide film formed by ion implantation, boron glass, boron Phosphor glass may be used.

The first etching method using a charged gaseous chemical species has been described by taking RIE as an example, but is not limited to this. Etching is performed by colliding ions with the SOI substrate. If the etching method
The present invention is effective in suppressing a change in etching characteristics due to charging during the process. Alternatively, not only in the etching step, but also in the implantation or film formation step such as ion implantation, ion plating, cluster ion beam evaporation, or the like, in which ions collide with the SOI substrate, fluctuation in characteristics due to charging during the step is suppressed. In this regard, the present invention is effective.

In the third embodiment, when the supporting substrate does not function as a conductive supporting material, for example, in the case of an SOI substrate using a glass substrate as the supporting substrate,
The wiring provided on the outer peripheral portion of the wafer may be formed up to the back surface of the SOI substrate.

In the third embodiment, the SOI
Although the example in which the wiring for electrically connecting the layer and the supporting substrate is provided on the SOI substrate has been described, if the restrictions on the RIE apparatus, for example, the transfer or the mounting to the etching chamber are permitted, the conductive A jig may be attached, and the jig may be used to electrically connect the SOI layer and the support substrate only during the RIE process.

In each of the embodiments, a PAD (for example, 40 in FIG. 1) is used as an electronic component formed on the structural film.
Although 9) is exemplified, the same effect can be obtained when other electronic components such as transistors are formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view and a plan view showing another part of the manufacturing process according to the first embodiment of the present invention.

FIGS. 3A and 3B are a cross-sectional view and a plan view illustrating a structure of a microdevice formed in a manufacturing process according to the first embodiment of the present invention. FIGS.

FIG. 4 is a sectional view showing a part of a manufacturing process according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view and a plan view illustrating another part of the manufacturing process according to the second embodiment of the present invention.

FIGS. 6A and 6B are a cross-sectional view and a plan view illustrating a structure of a microdevice formed in a manufacturing process according to a second embodiment of the present invention. FIGS.

FIG. 7 is a sectional view showing a part of the manufacturing process according to the third embodiment of the present invention.

FIG. 8 is a cross-sectional view and a plan view showing a part of a manufacturing process in a conventional example.

FIG. 9 is a cross-sectional view and a plan view showing another part of the manufacturing process in the conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 support substrate 101 embedded insulating film 102 SOI layer 103 opening 104 etching hole 113 doubly supported beam 114 weight 150 cantilever 116 beam 120, 121
... Fixed part 122 ... Frame part 900 ... High-concentration impurity diffusion layer 902 ... SOI substrate 903 ... PAD 905 ... Oxide film mask 400 ... First silicon substrate 401 ... Oxide film 406 ... Opening 402 ... Polysilicon film 403 ... Second Silicon substrate 404 SOI layer 407 polysilicon film filling opening 406 408 high-concentration impurity diffusion layer 409 PAD 410 oxide mask 411 opening 412 etching holes 420 and 421
... Fixed part 422... Frame part 423... Doubly supported beam 424... Cantilever 425.
Layers 506, 506 'Opening 507 Polysilicon film filling opening 506 507' Polysilicon film filling opening 506 '509 PAD 510 Oxide mask 511 Opening 512 Etching hole 520, 521: Fixed part 522: Frame part 523: Doubly supported beam 524: Cantilever beam 525: Weight 526: Beam 530: PAD 600: SOI
Substrate 601 SOI layer 602 high-concentration impurity diffusion layer 603 buried insulating film 604 support substrate 605 region around the wafer 606 high-concentration impurity diffusion layer 607 PAD 608 wiring 609 micro-device formation region 611 … High concentration impurity diffusion layer 612… Oxide mask 613… Opening

Claims (8)

[Claims] 1. A multi-layer substrate having at least a support substrate, an insulating film and a structural film laminated thereon, and at least a part of the insulating film is removed by etching, so that the structural film has a small distance from the support substrate. A method for manufacturing a microdevice for forming a structure facing away from one another, wherein an opening reaching the insulating film through the structural film is formed by first etching using a charged gaseous chemical species. Performing a second etching through the opening to remove at least a portion of the insulating film, and electrically connecting the structural film and the support substrate at least during the first etching. A method for manufacturing a microdevice, comprising connecting. 2. The method according to claim 1, wherein said means for electrically connecting said structural film and said support substrate is formed inside said multilayer structure substrate in a step of forming said multilayer structure substrate. Item 2. A method for manufacturing a microdevice according to Item 1. 3. The method for manufacturing a micro device according to claim 1, comprising the following steps. (A) a step of forming and patterning an insulating film on the main surface of the first substrate, removing a part of the insulating film, and exposing the portion of the first substrate main surface; (B) a step of forming a conductive film on the main surface of the structural substrate described in (A) above, including the portion where the first substrate main surface is exposed, and polishing and flattening the surface; (C) By joining the main surface of the structural substrate of (B) and the main surface of the second substrate, the conductive film formed on the portion where the main surface of the first substrate is exposed is formed. Electrically connecting the structural film and the second substrate. (D) The first etching using the charged gaseous chemical species forms an opening that penetrates the first substrate or the second substrate of the structural substrate (C) and reaches the insulating film. Process. (E) performing a second etching from the opening to remove at least a part of the insulating film. 4. A portion for electrically connecting the structural film and the support substrate is formed at a die sink line portion of the multilayer structure substrate, and the structural film and the support film are formed by dicing after forming a micro device. 4. The method for manufacturing a micro device according to claim 1, wherein a portion electrically connecting to the supporting substrate is removed. 5. A portion for electrically connecting the structure film and the support substrate is formed outside a dicing line on an outer peripheral portion of the multilayer structure substrate. The method for manufacturing a microdevice according to claim 1, wherein the microdevice is separated. 6. A part of a portion for electrically connecting the structural film and the support substrate is removed by dicing after forming a microdevice, and another part is left as it is, so that a part of the structural film is left. 4. The method for manufacturing a microdevice according to claim 1, wherein an electrical connection between the microdevice and the supporting substrate is left. 7. After forming the multilayer structure substrate, a part of the structure film and the insulating film is removed to expose a surface of the support substrate, and a conductive film is formed from the exposed portion to the structure film. The micro device according to claim 1 or 5, wherein a portion for electrically connecting the structural film and the support substrate is formed on a surface of the multilayer structure substrate by forming. Production method. 8. The method according to claim 1, wherein a portion for electrically connecting said structural film and said support substrate is formed on an etching jig provided outside said multilayer structure substrate. A manufacturing method of the microdevice according to the above.