JPH11219380A - Timing degradation simulation device and simulation method for lsi and lsi net list - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simulate an operation after the degradation of an LSI by predicting the actual secular degradation of the LSI in a design stage by taking the effect of coupling noise between wires into consideration so as to evade excessive specifications to reliability in the design of the LSI. SOLUTION: A reliability library generator 1 drives a circuit reliability simulator 4 and generates a reliability library 6 for indicating the dependency to prescribed operation conditions of the characteristic degradation degree of respective circuit cells. A cell delay degradation estimation means 2 estimates the secular degradation degree 11 of the delay of the respective circuit cells of the LSI while referring to the reliability library 6 while taking the effect of the coupling noise between the wires into considerations. An LSI timing degradation estimation means 18 estimates the delay of the respective circuit cells in the LSI after the degradation based on the cell delay degradation degree 11 and generates an LSI timing 14 after the degradation. A logical simulator 15 simulates the operation after the degradation of the LSI based on the LSI timing 14 after the degradation. Thus, by a simulation, the degradation of the timing of the respective signal paths of the LSI is accurately expressed based on the actual operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention predicts the deterioration of LSI characteristics over time due to the hot carrier phenomenon and the like in consideration of the influence of coupling noise between wirings.
The technology relates to a timing simulation.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (hereinafter abbreviated as LSI) has a lifetime, and after a certain period of operation, a failure or malfunction occurs. The main causes of LSI failure and malfunction are:
There are characteristic deterioration due to the hot carrier phenomenon and disconnection of wiring due to electromigration. In particular, the hot carrier phenomenon degrades the driving capability of the transistor, which causes the operation timing of the LSI to change with the passage of time, and eventually leads to malfunction.

In recent LSIs, device miniaturization has rapidly progressed with the development of manufacturing technology, and hot carriers, which are high-energy electrons, are likely to be generated by a high electric field generated in the device. It is becoming increasingly difficult to secure.

In order to ensure the reliability of LSI, for example,
In order to ensure a certain period of operation, a method of uniformly providing an appropriate margin to the operation timings of all circuits is conceivable in order to provide a sufficient margin for temporal changes in operation timing. However, in this method, since the margin is set in consideration of the worst case, the LSI is likely to fall into excessive specifications. Normally, there is a trade-off between the reliability and the performance of an LSI, and providing excessive reliability is
The result is a reduction in SI performance. Therefore, it has been difficult to develop a high-performance LSI using such a method.

In order to solve such a problem, the following method has been conventionally used. That is, L
For each circuit cell (for example, a cell such as an inverter belonging to a standard cell library used for an application-specific integrated circuit (ASIC)) constituting a SI, a value of a predetermined operating condition at the time of operating the LSI is checked. Then, for each circuit cell, it is verified whether or not the value of the checked operating condition is in a range necessary for the amount of deterioration and the life to satisfy a predetermined target value. Then, a circuit cell whose deterioration amount or lifetime does not satisfy the target values is recognized as a circuit cell having a problem in terms of LSI reliability, and measures such as design change are taken.

[0006]

However, in the above-described conventional method, only the amount of deterioration and the life of each circuit cell constituting the LSI are verified, and the reliability of the entire LSI is excessive with respect to the reliability. Often the specifications are This will be described.

[0007] Usually, an LSI operates according to a predetermined operating frequency. In other words, a predetermined cycle determined from the predetermined operation frequency is a unit of the processing time in the LSI. On the other hand, in an LSI, a signal flows through a signal path including several circuit cells during the predetermined cycle. At this time, if the signal propagation delay in the signal path is prolonged due to deterioration and exceeds a predetermined period, the operation timing of the LSI becomes erratic, resulting in malfunction. Conversely, if the signal propagation delay in the signal path becomes longer due to deterioration but does not exceed a predetermined period, the operation timing of the LSI remains normal, and no malfunction occurs.

Here, assuming signal paths A and B, the signal propagation delay in signal path A is substantially the same as a predetermined period (that is, weak in delay deterioration), while the signal propagation delay in signal path B is predetermined. Is considerably smaller than the period (i.e., resistant to delay deterioration). Further, it is assumed that both the signal paths A and B include circuit cells having the same operating condition value, and the operating condition value is not in a range required for the deterioration amount and the life to meet the target.

At this time, according to the above-described conventional method, both the circuit cells included in the signal path A and the circuit cells included in the signal path B are recognized as the circuit cells that pose a problem in terms of LSI reliability. In other words, it is subject to design changes. However, actually, the signal path A which is weak to the delay deterioration
Should be considered as a problem in terms of the reliability of the LSI, but this circuit cell included in the signal path B which is resistant to delay deterioration is judged to have no problem in terms of the reliability of the LSI. Is appropriate.

As described above, whether or not a circuit cell poses a problem from the viewpoint of the reliability of an LSI differs depending on each circuit cell even under the same operating conditions. This is because the permissible deterioration amount and the range of the life for each circuit cell differ depending on the position of the circuit cell in the signal flow of the LSI.

Further, hot carrier deterioration depends on a voltage applied to a transistor. Normally, the output voltage of the circuit cell changes in a range where the power supply potential is maximum and the ground potential is minimum. Due to recent miniaturization, wirings connecting circuit cells are densely arranged, and as a result, capacitive coupling with adjacent signals is likely to occur. If capacitive coupling is strengthened, coupling noise (noise due to capacitive coupling) during transition of adjacent signals
Which causes the potential of the output signal of the circuit cell to be higher than the power supply voltage or lower than the ground voltage. Normally, the output signal is connected to the drain of the transistor, and the voltage applied between the source and the drain of the transistor increases due to this noise, and the hot carrier deterioration increases. Heretofore, there has been no effective solution to this problem.

An object of the present invention is to provide an apparatus and a method for predicting the deterioration over time of an LSI at the design stage in consideration of the influence of coupling noise between wirings and simulating the operation after the deterioration of the LSI. And

[0013]

In order to solve the above-mentioned problem, a solution taken by the invention of claim 1 is to predict deterioration over time of an LSI at a design stage and simulate an operation after the deterioration of the LSI. As an LSI timing deterioration simulation apparatus, the degree of deterioration over time of the delay of each circuit cell constituting the target LSI is referred to by referring to a reliability library representing the dependence of the degree of deterioration of the characteristic of the circuit cell on predetermined operating conditions. While, based on the value of the predetermined operating condition of the circuit cell during the operation of the LSI,
Cell delay deterioration estimating means for estimating, and LSI timing deterioration estimating for estimating a delay of each circuit cell in the LSI deteriorated with time based on the delay deterioration degree of each circuit cell estimated by the cell delay deterioration estimating means Means for simulating the operation of the LSI after deterioration based on the delay of each circuit cell in the deteriorated LSI estimated by the LSI timing deterioration estimating means. Means are
The degree of deterioration of the delay of each circuit cell over time is estimated in consideration of the influence of coupling noise between wirings.

According to the first aspect of the present invention, the cell delay deterioration estimating means refers to the reliability library indicating the dependence of the degree of characteristic deterioration of the circuit cell on the predetermined operation condition, and refers to the circuit during the operation of the LSI. Since the estimation is performed based on the value of the predetermined operation condition of the cell, the degree of delay deterioration of each circuit cell reflecting the actual operation of the LSI is obtained. Further, the degree of delay deterioration of each circuit cell constituting the target LSI is estimated in consideration of the influence of coupling noise between wirings. Based on the degree of delay deterioration of the circuit cell, the LSI timing deterioration estimating means estimates the delay of each circuit cell in the LSI that has deteriorated with time. Then, the L
Based on the delay of each circuit cell in the SI, the LSI
Is simulated. For this reason, the deterioration of the timing of each signal path of the LSI is accurately expressed in accordance with the actual operation by the simulation in consideration of the influence of the coupling noise between the wirings. Therefore, in the design of the LSI, L
Excessive specifications for reliability due to unpredictable deterioration of the SI over time can be avoided, and an appropriate LSI can be designed in terms of both reliability and performance.

According to a second aspect of the present invention, there is provided the LSI timing degradation simulation apparatus according to the first aspect,
For each circuit cell, the degree of characteristic deterioration of a transistor constituting the circuit cell is obtained by a circuit reliability simulator, and from the obtained degree of characteristic deterioration of each transistor, the dependence of the degree of characteristic deterioration of the circuit cell on the predetermined operating condition is determined. It is assumed that a reliability library generation device that generates the reliability library by the request is provided.

According to the third aspect of the present invention, in the first aspect,
An LSI timing deterioration simulation apparatus includes a delay calculator for estimating a delay of each circuit cell in the LSI before deterioration, and based on a delay of each circuit cell in the LSI before deterioration estimated by the delay calculator, It is assumed that the operation before the deterioration of the LSI is simulated.

According to a fourth aspect of the present invention, the LSI timing degradation estimating means in the LSI timing degradation simulation apparatus according to the third aspect is provided in the delay computer.

Furthermore, in the invention of claim 5, the cell delay deterioration estimating means and the LSI timing deterioration estimating means in the LSI timing deterioration simulation apparatus of claim 3 are both provided in the delay calculator. .

According to the sixth aspect of the present invention, the first aspect is provided.
The reliability library in the LSI timing deterioration simulation apparatus uses the deterioration degree of the signal propagation delay between the input terminal and the output terminal as the characteristic deterioration degree of the circuit cell.

According to a seventh aspect of the present invention, the reliability library in the apparatus for simulating timing deterioration of an LSI according to the sixth aspect includes a condition that a rising and falling time of an input signal and an output load of a circuit cell are set as predetermined operating conditions. It is assumed that the capacitance, the number of times of switching of the input signal, and the variation of the output signal voltage from the power supply voltage or the ground voltage due to coupling noise are used.

Further, in the invention according to claim 8, the reliability library in the timing degradation simulation apparatus for an LSI according to claim 7 includes a circuit for determining whether a circuit cell having a plurality of input terminals has one input terminal and one output terminal. With respect to the degree of deterioration of the signal propagation delay, the number of times of switching an input signal to another input terminal and the rise and fall times are used as predetermined operating conditions.

According to the ninth aspect of the present invention, the seventh aspect is provided.
The reliability library in the LSI timing degradation simulation apparatus uses a power supply voltage applied to a circuit cell as a predetermined operating condition.

According to a tenth aspect of the present invention, the reliability library in the LSI timing degradation simulation apparatus of the seventh aspect uses the temperature of a circuit cell as a predetermined operating condition.

According to the eleventh aspect of the present invention, the reliability library in the apparatus for simulating timing degradation of an LSI according to the sixth aspect uses the degree of deterioration of the rise / fall time of the output signal as the degree of characteristic deterioration of the circuit cell. And

In the twelfth aspect of the present invention, the reliability library in the timing degradation simulation apparatus for an LSI according to the first aspect of the present invention includes the reliability library of the timing check value including at least the setup time and the hold time of the circuit cell. The timing degradation simulation apparatus for the LSI determines the degree of deterioration of the timing check value of a circuit cell constituting the target LSI during the operation of the LSI while referring to the reliability library. And a timing check value deterioration estimating means for estimating based on the value of the predetermined operating condition of the circuit cell in the above, and the LSI timing deterioration estimating means comprises a circuit which is estimated by the timing check value deterioration estimating means. Degradation of cell timing check value A timing check value of the circuit cell in the LSI that has deteriorated over time based on the timing check value of the circuit cell estimated based on the timing check value of the circuit cell estimated by the LSI timing deterioration estimating means. It is assumed that whether or not the circuit cell operates normally in the LSI.

According to a thirteenth aspect of the present invention, the reliability library in the apparatus for simulating the timing deterioration of an LSI according to the first aspect is characterized in that the dependency of a characteristic deterioration degree of a circuit cell on a predetermined operating condition is represented in a table format. I do.

According to a fourteenth aspect of the present invention, the reliability library in the apparatus for simulating timing degradation of an LSI according to the first aspect expresses the dependence of the degree of characteristic deterioration of a circuit cell on predetermined operating conditions as a function. .

Further, in the invention according to claim 15, the reliability library in the timing deterioration simulation apparatus for an LSI according to claim 1 further comprises:
The cell delay deterioration estimating means calculates the degree of delay deterioration of each circuit cell by the difference between the delay before deterioration and the delay after deterioration. Shall be represented.

Further, in the invention of claim 16, the reliability library in the timing deterioration simulation apparatus for an LSI of claim 1 further comprises:
The cell delay deterioration estimating means expresses the degree of delay deterioration of each circuit cell by the ratio between the delay before deterioration and the delay after deterioration. Shall be.

[0030] Further, in the invention of claim 17, in the LSI timing deterioration simulation apparatus of claim 1, the cell delay deterioration estimating means includes at least a part of the circuit cells constituting the LSI.
It is assumed that the degree of delay deterioration is estimated in units of a signal path composed of a plurality of circuit cells, and the LSI timing deterioration estimating means performs time-lapse based on the degree of delay deterioration of the signal path estimated by the cell delay deterioration estimating means. The delay of the signal path in the LSI which has been deteriorated is estimated, and the timing deterioration simulation device for the LSI estimates the delay of the signal path in the LSI after deterioration estimated by the LSI timing deterioration estimating means. Based on this, the operation of the LSI after deterioration is simulated.

In the invention according to claim 18, the reliability library generation device in the LSI timing degradation simulation device according to claim 2 connects to the output signal of the circuit cell when performing the simulation by the circuit reliability simulator. It is assumed that the forward current of the junction diode formed at the drain of the transistor is cut off or suppressed.

In the invention according to claim 19, the cell delay deterioration estimating means in the LSI timing deterioration simulation apparatus according to claim 1 is characterized in that the noise other than the coupling noise between wirings is compared with the coupling noise between wirings. The coupling wiring, the degree of capacitive coupling, and the amount of signal voltage fluctuation are determined by the noise source, the degree to which the noise affects the circuit cells,
In addition, it is assumed that the processing is equivalent to the coupling noise between the wirings by regarding the signal voltage fluctuation amount.

A solution taken by the twentieth aspect of the present invention is to predict LSI deterioration over time at the design stage,
As a method for simulating the timing degradation of an LSI for simulating the operation after the degradation of the SI, the degree of time-dependent degradation of the delay of each circuit cell constituting the target LSI depends on the predetermined operating condition of the degree of characteristic degradation of the circuit cell. While referring to the reliability library representing the
A cell delay deterioration estimating step of estimating based on the value of the predetermined operating condition of the circuit cell during the operation of I, and a time elapse based on the degree of delay deterioration of each circuit cell estimated in the cell delay deterioration estimating step. The LSI which has deteriorated
And an operation after the deterioration of the LSI is simulated based on the LSI timing deterioration estimating step of estimating the delay of each circuit cell and the delay of each circuit cell in the LSI after the deterioration estimated in the LSI timing deterioration estimating step. And a simulation step for estimating the degree of deterioration over time of the delay of each circuit cell in consideration of the influence of coupling noise between wirings.

According to a twentieth aspect of the present invention, in the cell delay deterioration estimating step, the circuit is operated at the time of the operation of the LSI while referring to a reliability library representing the dependence of the degree of characteristic deterioration of the circuit cell on a predetermined operating condition. Since the estimation is performed based on the value of the predetermined operation condition of the cell, the degree of delay deterioration of each circuit cell reflecting the actual operation of the LSI is obtained. Further, the degree of delay deterioration of each circuit cell constituting the target LSI is estimated in consideration of the influence of coupling noise between wirings. In the LSI timing deterioration estimation step, the delay of each circuit cell in the LSI that has deteriorated with time is estimated based on the degree of delay deterioration of the circuit cell. The LS after the deterioration
In the simulation step, the operation of the LSI after deterioration is simulated based on the delay of each circuit cell in I. Therefore, by simulation,
The deterioration of the timing of each signal path of the LSI is accurately expressed in accordance with the actual operation, taking into account the influence of coupling noise between wirings. Therefore, in the design of the LSI, it is possible to avoid an excessive specification for reliability due to unpredictable deterioration of the LSI over time, and to design the LSI appropriately in terms of both reliability and performance. it can.

According to a twenty-first aspect of the present invention, in the method for simulating timing deterioration of an LSI according to the twentieth aspect, for each circuit cell, a degree of characteristic deterioration of a transistor constituting the circuit cell is determined by driving a circuit reliability simulator. A reliability library generating step of generating the reliability library by determining the dependence of the degree of characteristic deterioration of the circuit cell on the predetermined operating condition from the determined degree of characteristic deterioration of each transistor. I do.

In the invention according to claim 22, the reliability library in the method for simulating timing deterioration of an LSI according to claim 20 includes a signal propagation delay between an input terminal and an output terminal as a characteristic deterioration degree of a circuit cell. The degree of deterioration shall be used.

According to a twenty-third aspect of the present invention, the reliability library in the method for simulating timing degradation of an LSI according to the twenty-second aspect includes the following:
It is assumed that the rise time and fall time of the input signal, the output load capacitance, the number of switching times of the input signal, and the amount of fluctuation of the output signal voltage from the power supply voltage or the ground voltage due to coupling noise are used.

Further, in the invention according to claim 24, the reliability library in the method for simulating timing deterioration of an LSI according to claim 23, wherein the reliability library for a circuit cell having a plurality of input terminals is connected between one input terminal and an output terminal. With respect to the degree of deterioration of the signal propagation delay, the number of times of switching an input signal to another input terminal and the rise and fall times are used as predetermined operating conditions.

According to a twenty-fifth aspect of the present invention, the reliability library in the method for simulating timing degradation of an LSI according to the twenty-third aspect uses a power supply voltage applied to a circuit cell as a predetermined operating condition.

Further, in the invention according to claim 26, the reliability library in the method for simulating timing deterioration of an LSI according to claim 23 uses the temperature of a circuit cell as a predetermined operating condition.

According to a twenty-seventh aspect of the present invention, the reliability library in the method for simulating timing deterioration of an LSI according to the twenty-second aspect uses the degree of deterioration of the rise and fall times of the output signal as the degree of characteristic deterioration of the circuit cell. And

According to a twenty-eighth aspect of the present invention, in the method for simulating timing degradation of an LSI according to the twentieth aspect, the cell delay degradation estimating step may be performed for at least a part of the circuit cells constituting the LSI.
Assume that the degree of delay deterioration is estimated in units of a signal path composed of a plurality of circuit cells, and the LSI timing deterioration estimating step is based on the degree of delay deterioration of the signal path estimated in the cell delay deterioration estimating step. And estimating the delay of the signal path in the LSI that has deteriorated.
I based on the delay of the signal path
Is simulated after the deterioration.

Further, the invention of claim 29 is the first invention.
In the LSI netlist referred to by the LSI timing degradation simulation apparatus, the wiring capacitance element can be recognized as a grounding capacitance when calculating the timing of the LSI, and when calculating the coupling noise between the wirings, the wiring and the wiring are coupled with the wiring. It is assumed to be described so that it can be recognized as a wiring capacitance between the wiring and the wiring.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of an LSI timing deterioration simulation apparatus according to a first embodiment of the present invention. As shown in FIG. 1, the LSI timing degradation simulation apparatus according to the present embodiment drives a circuit reliability simulator 4 to represent a reliability library representing the dependence of the degree of characteristic degradation of each circuit cell on predetermined operating conditions. And a cell for estimating the time-dependent deterioration degree (cell delay deterioration degree 11) of the delay of each circuit cell constituting the target LSI with reference to the reliability library 6. A delay deterioration estimating unit, a delay calculator for calculating a delay of each circuit cell in a target LSI, and a logic simulator for simulating an operation of the LSI based on an LSI timing including a delay of each circuit cell; ing. The delay calculator 12 includes an LSI timing deterioration estimating means 18 for estimating the delay of each circuit cell in the LSI that has deteriorated with time based on the cell delay deterioration degree 11. The logic simulator 15 is an LSI before deterioration.
Based on the pre-deterioration LSI timing 8 including the delay of each circuit cell in the above, the operation before the deterioration of the LSI is simulated to generate the pre-deterioration result 10, while the LS
Based on the post-deterioration LSI timing 14 including the delay of each circuit cell in I, the post-deterioration result 17 is generated by simulating the operation of the LSI after deterioration.

The operation of the LSI timing degradation simulation apparatus according to this embodiment shown in FIG. 1 will be described.

(Reliability Library Generation Step) FIG. 2 is a diagram conceptually showing a general configuration of a circuit cell. As shown in FIG. 2, in most cases, the circuit cell 20 is connected to the input terminal 2
1, an output terminal 22, a power supply terminal 23, and a ground terminal 24. The cell netlist 7 stores netlists of various circuit cells. ASICs in circuit cells
There are inverters, NAND gates, NOR gates, flip-flops, and the like generally prepared in the standard cell library. In addition to the above-mentioned general-purpose circuit cells, it is also possible to create circuit cells necessary for configuring an LSI and to use the circuit cells for generating the reliability library 6. As the net list stored in the cell net list 7, for example, a SPICE format is used. The cell netlist 7 includes information on the size and connection of transistors in each circuit cell, information on the values and connections of passive elements and parasitic elements, and the like. The process parameter 5 stores SPICE parameters, parameters for representing deterioration, parameters for manufacturing an LSI, and the like. SPICE format and SP
The ICE parameter is, for example, HSP issued by META-SOFTWARE.
It is described in ICE USER'S MANUAL (issued in 1996).

The reliability library generation device 1 first determines the type of the target circuit cell, and reads the netlist of the circuit cell from the cell netlist 7. Then, the circuit reliability simulator 4 is driven to determine the dependency of the degree of deterioration of the propagation delay between the input and output terminals of the target circuit cell on predetermined operating conditions while referring to the reliability model 3. The circuit reliability simulator 4 refers to the process parameters 5 and estimates deterioration of transistor characteristics by simulation. For example, Robert H. Tu e
t al. "Berkeley Reliability Tools-BERT" (IEEE Tran
sactions on Computer-Aided Design of Integrated Ci
rcuits and Systems, 1993, P1524-1534).

FIGS. 3 and 4 are diagrams schematically showing fluctuations in the output signal voltage caused by coupling noise. FIG. 3 shows a case where the output signal of the target circuit cell becomes higher than the power supply voltage VDD by ΔV. FIG. 4 shows a case where the output signal of the target circuit cell is lower than the ground voltage GND by ΔV. In FIGS. 3 and 4, an inverter is taken as an example of a target circuit cell. It is assumed that a signal (coupling signal) of a signal line having capacitive coupling with an output signal line of the inverter transits shortly before a transition of an input signal. Is shown.

In FIG. 3, since the coupling signal rises shortly before the output signal falls with the rise of the input signal, coupling noise occurs in the output signal and the output signal voltage becomes lower than the power supply voltage V.
It becomes higher than DD by ΔV. As a result, the output signal of the inverter changes from the voltage (VDD + ΔV) to the ground voltage GND. In this case, the output signal is the power supply voltage VDD.
The deterioration is greater than when the voltage changes from the voltage to the ground voltage GND.

Similarly, in FIG. 4, since the coupling signal falls shortly before the output signal rises with the fall of the input signal, coupling noise occurs in the output signal, and the output signal voltage is ΔV higher than the ground voltage GND. Only lower. As a result, the output signal of the inverter changes from the voltage (GND-ΔV) to the power supply voltage V
It changes to DD. In this case, the deterioration is greater than when the output signal changes from the ground voltage GND to the power supply voltage VDD.

Here, ΔV shown in FIGS. 3 and 4 is referred to as a variation (signal voltage variation) of the output signal voltage from the power supply voltage or the ground voltage due to coupling noise.

In the present embodiment, as the predetermined operating conditions,
It is assumed that the output load capacitance of the circuit cell, the rise and fall times of the input signal, and the amount of fluctuation of the output signal voltage from the power supply voltage or the ground voltage due to coupling noise are used. Further, in order to estimate a change in the degree of deterioration with the passage of time, the number of times of switching of the input signal is also used as an operating condition.

The degree of deterioration of the propagation delay is represented by the difference between the delay after deterioration and the delay before deterioration. 3 and 4, a solid line shows a signal waveform before deterioration, and a broken line shows a signal waveform after deterioration. As shown in FIGS. 3 and 4, assuming that a delay before deterioration is t1 and a delay after deterioration is t2,
Delay t2 after deterioration and delay t1 before deterioration as shown in equation (1).
The degree of deterioration of the propagation delay is represented by the difference Δt from This difference Δt is called a delay deterioration amount. Δt = t2−t1 (1)

The reliability library generating device 1 sets the values of the four operating conditions to certain values, and transfers the values to the circuit reliability simulator 4 together with the information of the netlist of the target circuit cell which has been read and outputs the circuit condition. The reliability simulator 4 is driven. The circuit reliability simulator 4
The degree of characteristic deterioration of each transistor of the circuit cell is obtained. The reliability library generation device 1 receives the degree of characteristic deterioration of each transistor of the circuit cell from the circuit reliability simulator 4 and obtains the delay deterioration amount of the circuit cell with reference to the reliability model 3. By performing such an operation while changing the values of the four operating conditions within an appropriate range, the dependence of the delay deterioration amount of the circuit cell on the four operating conditions is obtained. The dependence of the delay deterioration amount on the operating condition is represented by a function or a table.
Is output to The above operation is sequentially performed for all types of circuit cells stored in the cell netlist 7.

At this time, an approximated signal waveform as shown in FIG. 5 is used to change the signal voltage variation ΔV, which is one of the operating conditions. Of course, an actual signal waveform including coupling noise may be used. However, since the simulation is complicated, the simulation is simplified by using a signal waveform as shown in FIG. The signal waveform shown in FIG. 5 can be easily obtained by setting the initial value of the output signal at the time of the simulation to the voltage (VDD + ΔV). Further, when the potential is lower than the ground potential GND as shown in FIG. 4, the initial value of the output signal at the time of the simulation may be set to the voltage (GND-ΔV).

In this simulation, when the initial value of the output signal is set to the voltage (VDD + ΔV), the drain of the transistor connected to the output signal line of the circuit cell is connected to the substrate or the well (usually, the power supply voltage VDD or the ground). (Becomes voltage GND), and a forward current flows in this state, and the initial value of the output signal drops from the voltage (VDD + ΔV) to the power supply voltage VDD. Also, the initial value of the output signal is set to a voltage (GND-ΔV).
Is set, the forward current flows, and the initial value of the output signal changes from the voltage (GND-ΔV) to the ground voltage G.
It will rise to ND. In order to avoid such an operation, when simulating with the circuit reliability simulator 4, the initial value of the output signal is set to the voltage (VDD + Δ
V) or (GND-ΔV), a method of temporarily cutting off (off) or suppressing (reducing) the forward current of the junction diode of the drain of the transistor connected to the output signal line is used. Take.

As a result, the reliability library 6 representing the dependence of the degree of deterioration of the characteristics of the circuit cell on the predetermined operating conditions.
Is generated. In the reliability library 6 according to the present embodiment, the deterioration degree of the signal propagation delay between the input terminal and the output terminal is used as the characteristic deterioration degree of the circuit cell, and the input of the circuit cell is determined as a predetermined operating condition. The rise and fall times of the signal, the output load capacitance, the number of times the input signal is switched, and the amount of change in the output signal voltage from the power supply voltage or the ground voltage due to coupling noise are used.

FIG. 6 is a diagram showing information indicating the operating condition dependency of the amount of delay deterioration of a circuit cell, which is included in the reliability library 6 according to the present embodiment. FIG. 9 is a diagram illustrating an example of operating condition dependency of a delay deterioration amount when an input signal rises between output terminals. As shown in FIG. 4, with respect to each of the four operating conditions, that is, the number of times of switching of the input signal [times], the rise time of the input signal [ns], the output load capacitance [fF], and the signal voltage variation [V]. , The delay deterioration amount [nS].

In the reliability library 6, information as shown in FIG. 6 can be represented by a function. In this case, an expression of a function including an unknown number is stored in the reliability model 3, and the function is matched by curve fitting so that the function matches, for example, the relationship between each operating condition and the amount of delay deterioration in the table of FIG. What is necessary is just to determine an unknown number.

The delay calculator 12 includes an LSI netlist 9 in which connection information of each circuit cell constituting the target LSI is described, and a delay library in which the dependence of the delay of each circuit cell on a predetermined operation condition is described. 13 to calculate delays of all circuit cells constituting the LSI.

The LSI netlist 9 is composed of DSPF (Deta
iled Standard Parasitic File, e.g. Cadence Design
Systems, Inc. Cadence Standard Parasitic Format (1
993) described on page 8-20). In the present embodiment, it is assumed that capacitance coupling information for each wiring is added to the LSI netlist 9 in advance.

The LSI netlist 9 generally includes information on parasitic elements such as a parasitic capacitance and a parasitic resistance of a wiring between circuit cells in order to improve accuracy. Parasitic capacitance usually includes the capacitance component between the wiring of interest and ground,
A component of the coupling capacitance between the wiring of interest and the wiring adjacent thereto is included. In a format such as DSPF, these components cannot be described separately, and all components are described as a capacitance to ground, that is, a capacitance element between a wiring of interest and ground.

FIG. 7 is a diagram showing an example of the parasitic capacitance component of the output signal line of the inverter. In FIG. 7, Ca, Cb,
Cc, Cd, and Cg are capacitance components between the wiring 36 of interest and the adjacent wirings a, b, c, d, and the ground GND. In a format such as a normal DSPF, the capacitance components Ca, Cb, Cc, Cd, and Cg are all connected to wiring and ground GND.
However, in order to determine the effect of the coupling capacitance, wiring information of the coupling destination of each of the capacitance components Ca, Cb, Cc, Cd, and Cg is added to the LSI netlist 9 in advance. That is, the capacitance component Ca,
The fact that Cb, Cc, and Cd are coupling capacities with the wirings a, b, c, and d, respectively, is recorded in the LSI netlist 9.

FIG. 29 is a diagram showing an example of a normal DSPF netlist for a circuit in which two stages of inverters are connected in series. In FIG. 29, the line in which the first character is C indicates the capacity. As shown in FIG.
In F, each capacitor is connected to a ground terminal ("0" in FIG. 29) as a grounding capacitor.

Here, when there is a coupling capacity among the capacities, information on the actual connection destination may be additionally described as shown in FIG. In FIG. 30, (a) to (c)
Is a line indicating information added to the DSPF netlist shown in FIG. * Indicates a comment line in the DSPF format.
There is no negative effect on the function of the file. For example, line (a)
The capacitance C2inp is originally a node inp: 1 in the signal wiring of interest and a node net_ of the coupling destination wiring.
a. Therefore, the coupling relationship can be understood by referring to this additional information.

The delay library 13 is provided with output load capacitances of circuit cells and rise and fall times of input signals as predetermined operating conditions. That is, the delay library 13 stores the operating condition dependency of the delay of each circuit cell when it has not deteriorated.

Here, as an example, a case where the propagation delay between the input and output terminals of the inverter 31 in the signal path shown in FIG. 8 is calculated will be considered. The signal path as shown in FIG.
This is described in the netlist 9. First, the inverter 31
The load capacity connected to the output terminal 36 is determined. In this case, the load capacitance is the sum of the capacitance of the wiring parasitic element 34 and the input capacitance of the inverter 32 connected to the output terminal 36 of the inverter 31. Next, the rise and fall times of the input signal to the input terminal 35 are determined. For this purpose, the rise and fall time of the output signal of the two-input NAND gate 30 may be obtained when the load capacitance is the sum of the capacitance of the wiring parasitic element 33 and the input capacitance of the inverter 31. In this way, the output load capacitance and the input signal rise / fall time are obtained for the inverter 31. Based on these, the propagation delay between the input / output terminals of the inverter 31 is calculated with reference to the delay library 13.

The delay calculator 12 performs the above processing in L
This is performed for all circuit cells constituting the SI, and the result is output to the pre-deterioration LSI timing 8. The LSI timing 8 before deterioration is SDF (Standard Delay Format, for example, Op
Standard Delay Forma published by en Verilog International
t Specification Version 3.0, described in 1995).

The input vector 16 is an LSI input signal pattern described in time series, which is necessary for performing a logic simulation of the LSI. Logic simulator 1
5 reads the input vector 16, the pre-deterioration LSI timing 8, and other necessary data, executes a logic simulation in consideration of the operation timing before the deterioration of the LSI, and outputs the simulation result to the pre-deterioration result 10.

(Cell delay deterioration estimating step) The cell delay deterioration estimating means 2 first determines a target circuit cell from the circuit cells constituting the target LSI, and determines the target circuit cell during the operation of the LSI. The value of the operating condition in is extracted. More specifically, the output load capacitance 9a is extracted from the LSI netlist 9, the rise / fall time 8a of the input signal is extracted from the pre-deterioration LSI timing 8, and the input signal switching frequency 10a is extracted from the pre-deterioration result 10.

Further, the cell delay deterioration estimating means 2 comprises an LSI
The capacity coupling degree 9b is extracted from the netlist 9.

The degree of capacitive coupling will be described. For example, in FIG. 7, the degree of capacitance coupling between the wiring 36 and the wiring a is determined by the coupling capacitance Ca between the wiring 36 and the wiring a.
6 divided by the sum of the parasitic capacitances, ie, Ca
/ (Ca + Cb + Cc + Cd + Cg). Similarly,
The degree of capacitive coupling with the wiring b is obtained by dividing the coupling capacitance Cb between the wiring 36 and the wiring b by the total parasitic capacitance of the wiring 36, that is, Cb / (Ca + Cb + Cc + Cd).
+ Cg). Note that the degree of capacitive coupling with the ground GND is zero.

As described above, the information about the wiring of the other party having the capacitive coupling is added to the LSI netlist 9 in advance, so that referring to this information, all the wirings constituting the LSI have the capacitive coupling. The degree of capacitive coupling with the other party's wiring is determined.

Next, a table showing the relationship between the degree of capacitive coupling and the variation ΔV from the power supply voltage or the ground voltage of the output signal voltage due to the coupling noise is prepared in advance as shown in FIG. For the wiring, a signal voltage variation ΔV for each coupling capacitance is obtained. When the table as shown in FIG. 9 is used, the signal voltage variation ΔV
Ask for. FIG. 10 is a diagram showing an example of the calculation result of the signal voltage variation ΔV for the wiring 36 in FIG.

The relationship between the degree of capacitive coupling and the output signal variation ΔV as shown in FIG. 9 can be expressed by a function. In this case, an equation of a function including the unknown number is prepared, and the function is determined by curve fitting so that the function matches, for example, the relationship between the degree of capacitance coupling and the output signal voltage variation ΔV in the table shown in FIG. Should be determined. The information as shown in FIG. 9 may be directly incorporated in the cell delay deterioration estimating means 2 or may be in a form that the cell delay deterioration estimating means 2 can refer to as in the case of the reliability model 3.

Further, the cell delay deterioration estimating means 2 extracts the signal transition information 10b from the pre-deterioration result 10. The signal transition information refers to information indicating the presence or absence of a transition of a coupling signal in a wiring that is capacitively coupled to an output signal wiring, which influences deterioration. Specifically, a predetermined time range is arbitrarily set before and after the input signal transition, and the presence or absence of a signal transition of the combined signal within the predetermined time range is extracted as signal transition information.

FIG. 11 is a diagram showing an example of the signal transition of the combined signal which does not affect the deterioration. The signal transition of the combined signal when the input signal does not transition as shown in FIG.
Even if coupling noise occurs, it is ignored because it does not affect the deterioration. The cell delay deterioration estimating means 2 extracts such signal transition information for all wirings.

FIG. 12 is a diagram showing an example of the result of extracting the signal transition information for the output signal line 36 of the inverter in FIG. In FIG. 12, when the signal voltage is present, the signal voltage variation ΔV obtained as shown in FIG. 10 is used as it is. When there is no signal voltage variation amount ΔV is 0 (V). Note that there is no information on the presence / absence of a signal transition since the transition of the capacitance between the wiring and the ground GND is not considered originally.

Next, referring to the reliability library 6, the amount of delay deterioration of the target circuit cell is estimated based on the extracted value of the operating condition. In the reliability library 6, when the operating condition dependency of the delay deterioration amount of the circuit cell is represented by a function, the value of the extracted operating condition is substituted into the function to obtain the delay deterioration amount of the target circuit cell. . On the other hand, when the reliability library 6 shows the operating condition dependency of the delay deterioration amount of the circuit cell in a table, interpolation is appropriately performed according to the value of the extracted operating condition, and the delay of the target circuit cell is determined. What is necessary is just to obtain the deterioration amount. The result of performing such processing for all the circuit cells constituting the target LSI is represented by the cell delay deterioration degree 11
Output as

(LSI Timing Degradation Estimation Step) The delay calculator 12 is now provided with an LSI timing degradation estimation means 18.
Thus, the cell delay deterioration degree 11 is read in addition to the LSI netlist 9 and the delay library 13, and the delay of each circuit cell in the LSI that has deteriorated with time is calculated. LSI netlist 9 and delay library 13
Since the delay of each circuit cell in the LSI before deterioration is obtained from, the cell delay deterioration degree 11 represented by the difference is added to this. This result is output as the LSI timing 14 after deterioration. LSI timing 14 after deterioration is also L before deterioration.
Like the SI timing 8, it is described in a format such as SDF.

The logic simulator 15 is an LSI before deterioration.
, The input vector 16 and the degraded L
Read SI timing 14 and other necessary data,
A logic simulation is performed in consideration of the operation timing after the deterioration of the LSI, and the simulation result is output as a post-deterioration result 17.

As described above, according to the present embodiment, the degree of delay deterioration of the circuit cells of the target LSI is individually obtained with reference to the reliability library 6, and based on the degree of delay deterioration of each circuit cell, Since the operation of the LSI after the deterioration is simulated after estimating the delay of each circuit cell in the LSI which has been deteriorated, the simulation can be performed in consideration of the delay deterioration phenomenon of the signal path in the actual operation of the LSI. Thereby, in the design of the LSI, it is possible to avoid an excessive specification for reliability.

Further, according to the present embodiment, the time-dependent deterioration of the LSI is predicted at the design stage in consideration of the influence of the coupling noise between the wirings, and the operation after the deterioration of the LSI is simulated. Optimized design can be realized.

In the present embodiment, the rise and fall time of the input signal of the circuit cell is obtained only from the output load capacitance of the preceding circuit cell. However, the effect of changing the signal waveform due to the wiring parasitic resistance is taken in. You may ask. In this case, a more accurate rise and fall time of the input signal can be obtained.

In this embodiment, the reliability model 3 is
The function library is defined outside the reliability library generation device 1 to define a function formula for representing the operating condition dependency of the degree of delay deterioration of the circuit cell. , An arbitrary function formula can be selected on the reliability library generation device 1 side. On the other hand, in order to simplify the apparatus, the reliability model 3 may be incorporated in the reliability library generation apparatus 1.

In this embodiment, an inverter having one input and one output has been described as an example of a circuit cell. However, a circuit cell having at least one of an input terminal and an output terminal may also have a similar delay. The degree of deterioration can be estimated. In this case, it is necessary to estimate the degree of deterioration of the delay between each input terminal and each output terminal, that is, the delay of the number of combinations of the input terminal and the output terminal.

In this embodiment, the cell delay deterioration degree 1
In order to estimate 1, the number of input signal switching times 10 a
In this case, in order to estimate the deterioration after 10 years of operation, for example, an input vector 16 representing 10 years of operation must be provided to the logic simulator 15. This is unrealistic, and in fact represents a certain period of operation by the input vector 16,
The deterioration estimation period may be regarded as a repetition of the certain period, and the number of input signal switching times 10a may be obtained by an approximate calculation. Assuming that a fixed period represented by the input vector 16 is T1, an input signal switching count within the fixed period T1 represented by the input vector 16 is N1, and a degradation estimation period is T2, the input signal within the degradation estimation period T2 is calculated according to the following equation. The switching frequency N2 can be obtained. N2 = (T2 / T1) · N1 (2)

Further, a logic simulation is executed by using the input vector 16 representing the operation within the fixed period T1, and the input signal switching probability P is extracted from the pre-deterioration result 10 at this time, and from the operating frequency f and the deterioration estimation period T2, The input signal switching frequency N2 within the deterioration estimation period T2 may be obtained according to the following equation. N2 = T2 · f · P (3)

In this embodiment, the cell delay deterioration estimating means 2 extracts the output load capacitance 9a, which is the sum of the wiring capacitance and the input capacitance of the cell, from the LSI netlist 9. In addition to extracting from the list 9, the input capacity of the cell is stored in the delay library 13 in advance, extracted from the delay library 13, and the cell delay deterioration estimating means 2 adds the two to obtain the output load capacity. Is also good.

In this embodiment, the pre-deterioration LSI timing 8 and the post-deterioration LSI timing 14 include the delay of only the circuit cells. However, the embodiment may also include a wiring delay between the circuit cells. In this case, the delay calculator 12
Reads the information of the parasitic elements such as the wiring resistance and the wiring capacitance from the LSI netlist 9, reads the drive characteristics (eg, output impedance and output current) of the output terminal from the delay library 13, and reads the output characteristics of the output terminal of the circuit cell from both. Calculates the delay of the connected wiring and calculates the LSI before deterioration
What is necessary is just to output to the timing 8 or the LSI timing 14 after deterioration. As a result, it is possible to further improve the accuracy of the logic simulation.

Further, the reliability library 6 is made to have the operating condition dependency of the amount of change in the driving characteristic of the output terminal of the circuit cell.
The cell delay deterioration estimating means 2 and the LSI timing deterioration estimating means 18 calculate the driving characteristic deterioration amount in the same manner as the calculation of the delay deterioration amount, obtain the wiring delay based on the driving characteristic after the deterioration, and output the wiring delay to the LSI timing 14 after the deterioration. By doing so, it is possible to consider the effect that the wiring delay changes due to the change in the characteristics of the circuit cell after deterioration.

In the case where the circuit cell is CMOS, N-type M
Although it is composed of an OS transistor and a P-type MOS transistor, the hot carrier deterioration is remarkable in the N-type and occurs in the P-type, but generally much smaller than in the N-type. Therefore, the analysis may be performed by the circuit reliability simulator 4 on the assumption that the deterioration occurs only in the N-type.

In the present embodiment, when the cell delay deterioration estimating means 2 extracts the signal transition information 10b from the pre-deterioration result 10, the signal of the wiring capacitively coupled to the output signal line, that is, the transition of the coupled signal, It is checked whether or not the signal occurs within an arbitrarily set time range before and after the signal transition. The time range set at this time may be set to one value per LSI, or may be set to a plurality of values. May be set.

In the present embodiment, the transition of the input signal of the target circuit cell and the transition of the signal capacitively coupled to the output signal are within one time range before and after the transition of the input signal. Although it is assumed that noise from one combined signal is received, noise from a plurality of combined signals may be received. In this case, a simultaneous (almost simultaneous) transition of a plurality of combined signals within a set time range may be detected, and a corresponding change amount ΔV may be obtained.

In FIG. 12, when there is a transition within the time range for a plurality of wirings, since the individual variation amounts ΔV are known from FIG. 10, for example, the influence of the transition of a plurality of coupled signals is simply obtained by summing them. Can be considered as a method of expressing the variation ΔV obtained by integrating For example, if there is a transition within the time range between the wiring a and the wiring c, the respective variation amounts ΔV are 0.15 [V] and 0.45 [V] from FIG. = 0.15 + 0.4
5) may be used as ΔV.

In this embodiment, the output signal voltage of the circuit cell becomes higher than the power supply voltage VDD, ie, the voltage (VDD + ΔV), and lower than the ground voltage GND, ie, the voltage ( GN
D−ΔV). Of course, depending on the direction of the transition of the coupling signal, the output signal voltage may be lower than the power supply voltage VDD (voltage (VDD-Δ
V)) or becomes higher than the ground voltage GND (the voltage (G
ND + ΔV)). These cases are not considered in the present embodiment because deterioration tends to be weakened. However, if high-precision analysis is required, these cases may be handled. In this case, the reliability library 6 is generated by the reliability library generation device 1 in consideration of the signal voltage fluctuation amount ΔV, including the sign thereof, and the transition direction of the combined signal is detected in correspondence with the transition direction of the output signal. What is necessary is just to obtain the signal voltage fluctuation amount ΔV including its sign.

In this embodiment, the delay library 13
Has given the output load capacitance of the circuit cell and the rise and fall times of the input signal as predetermined operating conditions, but the power supply voltage or the ground voltage of the output signal voltage caused by coupling noise May be added to the operating conditions.

(Second Embodiment) FIG. 13 shows a second embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of an LSI timing degradation simulation apparatus according to an embodiment. 13, the same components as those in the LSI timing degradation simulation apparatus according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals as those in FIG.

As shown in FIG. 13, in this embodiment, the delay calculator 12A does not include the LSI timing degradation estimating means 18, and the LSI timing degradation estimating means 18 is provided separately from the delay calculator 12A. This is different from the first embodiment. LSI timing deterioration estimating means 18
Is itself the same as that of the first embodiment, and the cell delay deterioration degree 11 estimated by the cell delay deterioration estimating means 2
, The post-deterioration LSI timing 14 is obtained.
The operation of the entire LSI timing degradation simulation apparatus according to the present embodiment is the same as that of the first embodiment, and a detailed description thereof will be omitted.

As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained, and in addition, there is an effect that a conventional delay calculator 12A can be used.

(Third Embodiment) FIG. 14 shows a third embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of an LSI timing degradation simulation apparatus according to an embodiment. 14, the same components as those of the LSI timing degradation simulation apparatus according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals as those in FIG.

As shown in FIG. 14, in the present embodiment, the delay calculator 12B has the cell delay deterioration estimating means 2 in addition to the LSI timing deterioration estimating means 18, and the delay calculator 12B directly stores the reliability library 6 The difference from the first embodiment is that the post-degradation LSI timing 14 is obtained while referring to the timing. The operation of the entire LSI timing degradation simulation apparatus according to this embodiment is the same as that of the first embodiment, and a detailed description thereof will be omitted.

As described above, according to the present embodiment, the same effect as that of the first embodiment can be obtained, and in addition, since the cell delay deterioration estimating means 2 is incorporated in the delay calculator 12B, the overall configuration is reduced. Become simple.

(Fourth Embodiment) An LSI timing degradation simulation apparatus according to a fourth embodiment of the present invention has a configuration as shown in FIG. 1 as in the first embodiment. 6 also has information on the dependency of the degree of deterioration of the rise / fall time of the output signal of the circuit cell on predetermined operating conditions. That is, in the present embodiment, the reliability library generation device 1
Regarding the degree of deterioration of the rise and fall times of the output signals of the circuit cells, the dependence on the predetermined operating conditions is determined by driving the circuit reliability simulator 4 based on the cell netlist 7.

The operation of the LSI timing degradation simulation apparatus according to this embodiment will be described. Here, only the points different from the first embodiment will be described, and the description of the other points will be omitted.

FIG. 15 is a diagram showing waveforms before and after deterioration of the input signal and the output signal of the inverter. FIG.
5, the solid line is the signal waveform before deterioration, and the broken line is the signal waveform after deterioration. As shown in FIG. 15, when the inverter is deteriorated, the propagation delay between the input terminal and the output terminal changes from t1 to t2 as described with reference to FIGS.
Further, since the driving capability of the output transistor deteriorates, the fall time of the output signal also changes from ts1 to ts2. Here, the fall time of the output signal is represented by the time when the output signal voltage changes from 90% to 10% of the power supply voltage VDD.

Therefore, in the present embodiment, the reliability library 6 determines the degree of deterioration of the rise and fall times of the output signal of the circuit cell as the degree of characteristic deterioration of the circuit cell and indicates the dependence on a predetermined operating condition. I do. As the predetermined operating condition, as in the first embodiment,
The rise and fall time of the input signal, the output load capacitance, the number of times the input signal is switched, and the amount of change in the output signal voltage from the power supply voltage or the ground voltage due to coupling noise are used. Further, in the present embodiment, similarly to the degree of deterioration of the propagation delay, the degree of deterioration of the rise and fall times of the output signal of the circuit cell is calculated by the following equation using the rise and fall times ts2 after deterioration and the rise and fall times before deterioration. Difference Δt from falling time ts1
s, ie, the amount of deterioration. Δts = ts2−ts1 (4)

The reliability library generation device 1 obtains, in addition to the delay deterioration amount, the dependency of the rise and fall time of the output signal on the predetermined operating condition in the same manner as the case of the delay deterioration amount. That is, the values of the above-mentioned four operating conditions are set to certain values, respectively, and are passed to the circuit reliability simulator 4 together with the information of the netlist of the target circuit cell which has already been read, and the circuit reliability simulator 4 is driven. The circuit reliability simulator 4 obtains the degree of characteristic deterioration of each transistor of the circuit cell. The reliability library generation device 1 includes a circuit reliability simulator 4
, The degree of deterioration of the rise and fall times of the output signal of the circuit cell is obtained with reference to the reliability model 3 by receiving the degree of characteristic deterioration of each transistor of the circuit cell. By performing such an operation while changing the values of the four operating conditions in an appropriate range, the dependence of the deterioration amount of the rise / fall time of the output signal on the four operating conditions is obtained. The dependency of the rise / fall time of the output signal on the operating condition is represented by a function or a table and output to the reliability library 6. The above operation is sequentially performed for all types of circuit cells stored in the cell netlist 7.

FIG. 16 is a diagram showing information, which the reliability library 6 according to the present embodiment has, showing the operating condition dependency of the deterioration amount of the rise and fall times of the output signal of the circuit cell.
FIG. 7 is a diagram illustrating an example of the operating condition dependency of the amount of deterioration of the fall time of the output signal at one output terminal of one circuit cell when represented in a table. As shown in FIG. 16, with respect to each of the four operating conditions, that is, the number of times of switching of the input signal [times], the rise time of the input signal [ns], the output load capacitance [fF], and the signal voltage variation [V]. , The fall time degradation amount [nS] of the output signal. As in the first embodiment, information as shown in FIG. 16 can be represented by a function.

The cell delay deterioration estimating means 2 refers to the reliability library 6 representing the dependence of the amount of delay deterioration and the amount of deterioration of the rise / fall time of the output signal on the operating conditions, and determines the amount of delay deterioration of the target circuit cell. Is estimated.

Here, as an example, it is assumed that the delay deterioration amount of the inverter 31 in the signal path shown in FIG. 8 is estimated. The cell delay deterioration estimating means 2 first specifies a target circuit cell, that is, an inverter 31 and a preceding circuit cell 30 connected to an input terminal 35 thereof, and extracts a value of an operation condition thereof. For the inverter 31 and the preceding circuit cell 30, the output load capacitance 9a and the degree of capacitive coupling 9b from the LSI netlist 9, the input signal rise / fall time 8a from the pre-degradation LSI timing 8, the pre-deterioration result 1
From 0, the input signal switching frequency 10a and the signal transition information 10b are respectively extracted.

Next, based on the extracted operating condition values, the output signal rise / fall time degradation amount of the preceding circuit cell 30 is first calculated with reference to the reliability library 6. This deterioration amount is added to the already-extracted input signal rise / fall time of the inverter 31 and the input signal rise / fall time after deterioration. Then, the reliability library 6 of the inverter 31 is determined on the basis of the obtained input signal rise / fall time after deterioration, the output load capacitance 9a, the degree of capacitive coupling 9b, the input signal switching frequency 10a, and the signal transition information 10b which have already been extracted. The delay deterioration amount is calculated while referring to the delay deterioration amount. The above processing is performed for all the cells in the LSI.

As described above, according to the present embodiment, the amount of delay deterioration of a circuit cell is estimated with reference to the reliability library representing the operating condition dependence of the amount of delay deterioration and the amount of deterioration of the rise and fall times of an output signal. Therefore, it is possible to execute a simulation in which a phenomenon that an output signal waveform changes due to deterioration is also taken into consideration. Therefore, compared to the first embodiment in which the delay deterioration amount of the circuit cell is estimated by referring to the reliability library representing the operating condition dependence of only the delay deterioration amount without considering the change of the output signal waveform due to the deterioration. A more accurate simulation can be performed.

(Fifth Embodiment) An LSI timing deterioration simulation apparatus according to a fifth embodiment of the present invention has the same structure as that of the fourth embodiment except that the reliability library 6 has the circuit cell shown in FIG. Has information on the degree of deterioration of the rise / fall time of the output signal waveform. However, the present embodiment is characterized in that the degree of deterioration is represented by a ratio between a characteristic value before deterioration and a characteristic value after deterioration.

That is, the degree of deterioration of the circuit cell delay is represented by the ratio of the post-deterioration delay to the pre-deterioration delay, and the degree of deterioration of the output signal rise / fall time of the circuit cell is expressed as a function of the output signal rise / fall time before deterioration. It is represented by the ratio of the output signal rise and fall times after deterioration.

The operation of the LSI timing degradation simulation apparatus according to this embodiment will be described. Here, only the points different from the fourth embodiment will be described, and the description of the other points will be omitted.

In the fourth embodiment, as shown in equations (1) and (4), both the degree of deterioration of the delay and the degree of deterioration of the rise and fall times of the output signal are represented by differences. In the present embodiment, as shown in the following equation, the degree of delay deterioration is:
It is represented by the ratio R of the post-deterioration delay t2 to the pre-deterioration delay t1, and the degree of deterioration of the output signal rise / fall time is the ratio of the output signal rise / fall time ts2 after deterioration to the output signal rise / fall time ts1 before deterioration. It is represented by the ratio Rs. R = t2 / t1 (5) Rs = ts2 / ts1 (6)

The reliability library generation device 1 obtains the degree of delay deterioration represented by the ratio, similarly to the case of obtaining the degree of delay deterioration represented by the difference. That is, similarly to the first embodiment, the circuit reliability simulator 4 is driven while changing the values of the four operating conditions within an appropriate range, and the four deterioration rates of the delay ratio of the target circuit cell are reduced. Find dependencies on operating conditions. Similarly, the dependence of the deterioration ratio of the output signal rise / fall time of the target circuit cell on the four operating conditions is determined.

FIG. 17 is a diagram showing information indicating the operating condition dependency of the delay deterioration ratio of a circuit cell, which is included in the reliability library 6 according to the present embodiment. FIG. 6 is a diagram illustrating an example of operating condition dependence of a delay deterioration ratio when an input signal rises between output terminals. As shown in FIG. 17, with respect to each of the four operating conditions, namely, the number of times of switching of the input signal [times], the rise time of the input signal [ns], the output load capacitance [fF], and the signal voltage variation [V], , And the delay deterioration ratio. The operation dependency of the deterioration ratio of the output signal rise / fall time can be similarly expressed. As in the first embodiment, information as shown in FIG. 17 can be represented by a function.

The cell delay deterioration estimating means 2 refers to the reliability library 6 representing the operating condition dependence of the delay deterioration ratio and the deterioration ratio of the rise and fall times of the output signal, and determines the delay deterioration ratio of the target circuit cell. Is estimated.

Here, as an example, it is assumed that the delay deterioration ratio of inverter 31 in the signal path shown in FIG. 8 is estimated. The cell delay deterioration estimating means 2 first specifies a target circuit cell, that is, an inverter 31 and a preceding circuit cell 30 connected to an input terminal 35 thereof, and extracts a value of an operation condition thereof. For the inverter 31 and the preceding circuit cell 30, the output load capacitance 9a and the degree of capacitive coupling 9b from the LSI netlist 9, the input signal rise / fall time 8a from the pre-degradation LSI timing 8, the pre-deterioration result 1
From 0, the input signal switching frequency 10a and the signal transition information 10b are respectively extracted.

Next, based on the extracted values of the operating conditions, the output signal rise / fall time degradation ratio of the preceding circuit cell 30 is first calculated with reference to the reliability library 6. This deterioration ratio is multiplied by the input signal rising and falling time of the inverter 31 already extracted to obtain the input signal rising and falling time after deterioration. The reliability library 6 of the inverter 31 is determined based on the input signal rise / fall time obtained after the deterioration, the output load capacitance 9a and the capacitance coupling degree 9b, the input signal switching frequency 10a and the signal transition information 10b which have already been extracted. , The delay deterioration ratio is calculated.

The LSI timing deterioration estimating means 18 calculates L
Read the SI netlist 9, the delay library 13, and the cell delay deterioration degree 11 expressed by the delay deterioration ratio,
The delay of each circuit cell in the LSI that has deteriorated with time is calculated. LSI netlist 9 and delay library 1
Since the delay in the LSI before deterioration is obtained from 3, the cell delay deterioration degree 11 expressed by the ratio is multiplied by this. This result is output as the LSI timing 14 after deterioration. The post-deterioration LSI timing 14 is also described in a format such as SDF similarly to the pre-deterioration LSI timing 8.

As described above, according to the present embodiment, in the cell delay deterioration degree 11, the delay deterioration degree is represented by the relative information of the ratio, so that, for example, the delay library 13 and the reliability library 6 have different process parameters. , It is possible to perform a simulation with high accuracy.

(Sixth Embodiment) FIG. 18 shows a sixth embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of an LSI timing degradation simulation apparatus according to the embodiment. LS according to the present embodiment
The I timing deterioration simulation apparatus has the same configuration as that of the first embodiment, but the reliability library 6
However, they differ in that they also have information on the dependence of the degree of delay deterioration of each circuit cell on the power supply voltage and temperature applied to the circuit cell. That is, in the present embodiment, the reliability library generation device 1 determines the dependence of the signal propagation delay of the circuit cell and the degree of deterioration of the rise and fall times of the output signal on the predetermined operating conditions at various power supply voltages and temperatures. ,
It is obtained by the circuit reliability simulator 4 based on the cell netlist 7.

The operation of the LSI timing degradation simulation apparatus according to this embodiment will be described. Here, only the points different from the first embodiment will be described, and the description of the other points will be omitted.

The reliability library generating apparatus 1 changes the power supply voltage and the temperature applied to the circuit cell within an appropriate range, and changes the power supply voltage and the temperature at four times in the same manner as in the first embodiment. The operating condition dependency of the delay deterioration amount is obtained while changing the operating condition within an appropriate range.
The dependence of the obtained delay deterioration amount on the operating condition for each power supply voltage or each temperature is represented by a function or a table and output to the reliability library 6. Such processing is sequentially performed for all types of circuit cells.

FIG. 19 is a diagram showing information on the degree of delay deterioration of a circuit cell included in the reliability library 6 according to the present embodiment. An input signal between one input / output terminal of one circuit cell and a table is shown. FIG. 7 is a diagram illustrating an example of the dependence of the amount of delay deterioration at the rise on operating conditions for each power supply voltage.

When given power supply voltage 61 is applied, cell delay deterioration estimating means 2 performs delay deterioration in power supply voltage 61 by interpolation or the like based on information held in reliability library 6 as shown in FIG. Generate a table or function expression that represents the operating condition dependence of the quantity. Subsequent processing is the same as in the first embodiment. However, the delay library 13 also needs to be generated in advance for the predetermined power supply voltage 61.

FIG. 20 is a diagram showing information on the degree of delay deterioration of circuit cells included in the reliability library 6 according to the present embodiment. FIG. 9 is a diagram illustrating an example of the operating condition dependence of the amount of delay deterioration at the time of signal rise for each temperature.

The cell delay deterioration estimating means 2 calculates a predetermined temperature 6
When 2 is given, a table or a functional expression representing the operating condition dependency of the delay deterioration amount at the temperature 62 is generated by a method such as interpolation based on the information held in the reliability library 6 as shown in FIG. Subsequent processing is the same as in the first embodiment. However, the delay library 13 also needs to be generated in advance for the predetermined temperature 62.

As described above, according to the present embodiment, it is possible to consider the dependency of the deterioration of the LSI on the power supply voltage and the temperature. Therefore, the operation of the LSI after the deterioration can be performed within the range of the operating power supply voltage and the operating temperature. Be able to analyze.

In this embodiment, the dependency of the power supply voltage and the temperature on the deterioration of the LSI are individually considered, but both may be considered together. In this case, the reliability library 6
In this case, information as shown in FIG. 20 may be prepared for each power supply voltage. Also, the predetermined power supply voltage or temperature is
One value may be set for each of the LSIs, or one of various values may be set for each circuit cell.

(Seventh Embodiment) The seventh embodiment of the present invention relates to a case where deterioration of signal propagation delay between one input terminal and an output terminal is determined for a circuit cell having a plurality of input terminals. , The rise and fall times of input signals to other input terminals and the number of times of switching. An LSI timing degradation simulation apparatus according to the seventh embodiment of the present invention has a configuration as shown in FIG. 1 as in the first embodiment.

Consider a two-input NAND gate as shown in FIG. 21 as a circuit cell. In FIG. 21, A and B are input terminals, and Y is an output terminal. Two-input NA shown in FIG.
The circuit diagram at the transistor level of the ND gate is CMOS
In this case, the result is as shown in FIG.

In the two-input NAND gate shown in FIG. 21, the deterioration of the signal propagation delay between input terminal A and output terminal Y is caused by switching of the input signal to input terminal B (hereinafter referred to as "input signal B"). Depends on history. On the other hand, the deterioration of the signal propagation delay between the input terminal B and the output terminal Y depends on the switching history of the input signal to the input terminal A (hereinafter referred to as “input signal A”). In particular, when the output signal falls, the current mainly flows through the portion where the N-type MOS transistors N1 and N2 in FIG. 22 are connected in series.
1 and N2.

For this reason, in the present embodiment, the reliability library generation device 1 generates the reliability library 6 in consideration of the dependence on the number of times of switching of the input signal A and the number of times of switching of the input signal B.

FIG. 23 is a diagram showing the information held by the reliability library 6 according to the present embodiment with respect to one variation of the output signal voltage from the power supply voltage or the ground voltage due to the coupling. In FIG. 23, Tis is the rise and fall time of the input signal, and Cl is the output load capacity. Table n
(Tis, Cl) (where n = 1 to 9) is used to set the number of times of switching of the input signal A to the value shown above and to set the number of times of switching of the input signal B to the value shown to the left thereof, and to make the rising edge of the input signal Fall time Tis and output load capacity C
11 is a table showing the degree of deterioration of signal propagation delay between an input terminal A and an output terminal Y created by appropriately changing l.

The cell delay deterioration estimating means 2 calculates the result before deterioration 10
From the input signal switching frequency 10a. For example, assuming that the number of times of switching of the input signal A is 10 ¹³ and the number of times of switching of the input signal B is 10 ¹⁵ in the number of times of input signal switching 10a, the cell delay deterioration estimating means 2 selects table 7 as a table. When the number of switching times for which a table is not prepared in the reliability library 6 is extracted, a table for the number of switching times is obtained by interpolation or the like.

As described above, according to the present embodiment, for a circuit cell having a plurality of input terminals, the degree of deterioration of signal propagation delay between one input terminal and output terminal is determined by the rise of an input signal at another input terminal. The fall time and the number of times of switching can be obtained in consideration of the fall time, and the accuracy of the simulation can be improved as compared with the first embodiment.

In this embodiment, the reliability library 6
In the above, the information is represented in a table format, but may be represented by a function.

In the present embodiment, a table is prepared in the reliability library 6 on the assumption that the rise and fall times of the input signals are equal at the input terminals A and B. The table may be prepared as different from the rise and fall time of the signal B. In this case, table n (Tisa, Tisb, C
It is necessary to further increase the dimension of each table as in l). Here, Tisa is the rise and fall time of the input signal A, and Tisb is the rise and fall time of the input signal B.

(Eighth Embodiment) In an eighth embodiment of the present invention, a signal path including a plurality of circuit cells such as a critical path is used as a unit for delay estimation instead of a circuit cell. An LSI timing degradation simulation apparatus according to the eighth embodiment of the present invention has a configuration as shown in FIG. 1 as in the first embodiment.

FIG. 24 shows an example of a signal path used as a unit of delay estimation in this embodiment. The signal path 50 from the input terminal A to the output terminal Y shown in FIG. 24 includes four stages of circuit cells 51, 52, 53, and 54 connected in series. 2
One input terminal of the input NAND gate 51 is the input terminal A.
The inverter 52 has an input terminal connected to the output terminal of the two-input NAND gate 51, and the three-input NAND gate 53 has one input terminal connected to the inverter 52.
The inverter 54 has an input terminal connected to the output terminal of the three-input NAND gate 53,
The output terminal is connected to the output terminal Y.

Two-input NAND gate 51 and three-input NAN
In a circuit cell having a plurality of input terminals, such as a D gate 53, a terminal X which is not related to the signal path 50 of interest.
The logical values of 1, 1, and X3 are fixed so that the signal flows along the signal path 50. In the signal path 50 shown in FIG. 24, the logical value “1” is fixed to the signals of the terminals X1, X2, and X3.

In this embodiment, the signal path 50 as shown in FIG. 24 is treated as one circuit cell having an input terminal A and an output terminal B. Other points are the first
This is the same as the embodiment.

That is, the cell delay deterioration estimating means 2 calculates L
For at least a part of the circuit cells constituting the SI, the degree of delay deterioration is estimated in units of a signal path composed of a plurality of circuit cells, and the LSI timing deterioration estimating means 18 estimates the degree of delay deterioration by the cell delay deterioration estimating means 2. Cell delay deterioration degree 11 including the obtained signal path delay deterioration degree
Is used to estimate the delay of the signal path in the LSI that has deteriorated with time. Then, the degraded LSI timing 1 including the signal path delay in the degraded LSI
4 simulates the operation after deterioration of the LSI. However, the LSI timing deterioration estimating means 18
24, it is necessary to provide the LSI netlist 9 with signal path definition information as shown in FIG. 24 so that the LSI netlist 9 and the cell delay deterioration degree 11 can correspond to each other.

As described above, according to the present embodiment, a signal path including a plurality of stages of circuit cells, such as a critical path, is handled as a unit for delay estimation. Therefore, delay is estimated for all signal paths in an LSI in circuit cell units. Compared to the first embodiment, it can be executed easily, and the total amount of arithmetic processing can be reduced.

In this embodiment, the signals at the terminals X1, X2, and X3, which are not related to the signal path of interest, are fixed. However, the actual number of switching of the signal is reflected in the delay estimation of the signal path. Is also good.

Note that one of the circuit cells in the target LSI is
Two types of methods may be used at the same time, such that a unit is handled in units of signal paths and other circuit cells are handled in units of each circuit cell as in the first embodiment.

In the present embodiment, the signal path 50 is constituted by the minimum unit of circuit cells, but may have a multi-layer structure.

(Ninth Embodiment) A circuit cell for storing data, such as a flip-flop or a latch, has a phase relationship between an input data signal and a clock signal for taking in the input data, an input data signal and a clock signal. Normal operation or malfunction depending on the validity period of the device. For this reason, a limit value at which the circuit cell does not malfunction for the phase relationship, the validity period, and the like is determined in advance,
For each circuit cell in the LSI, whether or not the above-mentioned phase relationship or effective period does not exceed the limit value is checked by, for example, a logic simulator. The predetermined limit values such as the phase relationship and the validity period are referred to as timing check values (timing constraints).

As the timing check value, there are a setup time, a hold time, a minimum pulse width, a recovery time, a removable time, a release time, and the like.

For example, in the case of a flip-flop, the setup time depends on how long before the clock signal becomes valid, the input data signal must be determined.
Is defined. The hold time determines how long after the clock signal becomes valid, the input data signal must be held. The minimum pulse width indicates the minimum value of the effective period (pulse width) of the clock signal during which the circuit cell can operate normally.

Since such a timing check value depends on the signal propagation state in the circuit cell, if the transistor characteristic in the circuit cell deteriorates due to aging, the signal propagation state in the circuit cell also changes. It is necessary to change the timing check value in accordance with this change.

According to the ninth embodiment of the present invention, the degree of deterioration is estimated not only for the delay of a circuit cell but also for the timing check value of a circuit cell, and the deterioration is estimated based on the estimated degree of deterioration of the timing check value of the circuit cell. A later timing check value is obtained to check the operation timing of the LSI.

FIG. 25 is a block diagram of a ninth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an SI timing degradation simulation apparatus. As shown in FIG. 25, the timing deterioration simulation apparatus for an LSI according to the present embodiment estimates the timing check value deterioration degree 72 from the timing check value information (timing check value 6b) of the reliability library 6A. A deterioration estimating means 71 is provided, and the cell delay deterioration estimating means 2 and the timing check value deterioration estimating means 71 constitute a deterioration estimating means 70. Cell delay information (cell delay 6a) of the reliability library 6A is as follows:
It has the same information as the reliability library 6 in the first to eighth embodiments. Further, the delay library 13A includes information of a cell delay (cell delay 13a) and information of a timing check value (timing check value 13b).
The cell delay 13a has the same information as the delay library 13 in the first to eighth embodiments.

First, the generation of the timing check value 13b in the delay library 13A will be described. Here, the case of the setup time of the flip-flop will be described as an example.

With respect to time tc at which the clock signal becomes valid, time td at which the input data signal becomes valid is swept at an appropriate time interval before time tc (that is, the phase difference between the clock and the input data is changed). ), The critical time difference (t
c-td) is determined as the setup time.

The timing check value such as the setup time is calculated based on the rise time and fall time of the clock signal and the input data signal. Does not require a fall time), and is affected by the power supply voltage and temperature of the circuit cell. These are used as operating conditions, and the timing check value is obtained while changing each operating condition within an appropriate range. Determine the operating condition dependency of the timing check value. Normally, the delay library generation device (not shown)
The above-described analysis is performed by driving a circuit simulator (not shown, different from the circuit reliability simulator 4).

In this way, the delay library generation device obtains the operating condition dependency of the timing check value for each of the circuit cells such as flip-flops and latches, together with the information on the operating condition dependency of the delay of the circuit cell. Output to the delay library 13A.

FIG. 26 shows an example of the information held by the timing check value 13b of the delay library 13A, and shows an example of the dependency of the setup time of the flip-flop before deterioration on operating conditions. In FIG. 26, Tisck is the rise time of the clock signal, and Tisd is the rise time of the input data signal. In FIG. 26, it is assumed that the power supply voltage and the temperature are fixed.

Next, generation of the timing check value 6b in the reliability library 6A will be described.

The degree of deterioration of the timing check value is affected by the number of switching of the clock signal and the input data signal in addition to the rise time and the fall time of the clock signal and the input data signal, the power supply voltage and temperature of the circuit cell. Therefore, using these as operating conditions, the timing check value is obtained while changing each operating condition within an appropriate range, and the operating condition dependency of the degree of deterioration of the timing check value is obtained as a whole.

Here, the degree of deterioration of the timing check value is represented by the difference Δtt between the timing check value tt2 after deterioration and the timing check value tt1 before deterioration, that is, the amount of deterioration of the timing check value as shown in the following equation. I do. Δtt = tt2-tt1 (7)

The reliability library generating apparatus 1A sets the value of each operating condition to a certain value, and transfers the value to the circuit reliability simulator 4 together with the information of the netlist 7 of the target circuit cell which has already been read. The sex simulator 4 is driven. The circuit reliability simulator 4 determines the degree of characteristic deterioration of each transistor of the circuit cell. The reliability library generation device 1A receives the degree of characteristic deterioration of each transistor of the circuit cell from the circuit reliability simulator 4, and obtains a timing check value deterioration amount of the circuit cell with reference to the reliability model 3.

Taking the amount of deterioration of the setup time of the flip-flop as an example, before and after the deterioration,
The time td at which the input data signal becomes valid with respect to the time tc at which the clock signal becomes valid is swept at an appropriate time interval before the time tc, and the limit time difference (tc− td) is determined as the setup time. The deterioration amount is obtained from the difference between the time difference before deterioration and the time difference after deterioration.

By performing such an operation while changing the value of each operating condition within an appropriate range, the operating condition dependency of the deterioration amount of the timing check value of the circuit cell is obtained. The operating condition dependency of the timing check value deterioration amount is represented by a function or a table, and the reliability library 6A
Is output as the timing check value 6b. The above operation is sequentially performed on necessary circuit cells stored in the cell netlist 7 (a timing check value is required only for circuit cells such as flip-flops and latches). To be).

FIGS. 27 and 28 are examples of information held by the timing check value 6b of the reliability library 6A, and are diagrams showing information indicating the dependence of the amount of deterioration of the setup time of the flip-flop on the operating conditions. In FIG. 27, Tisck is the rising and falling time of the clock signal, Tisd
Is the rise and fall time of the input data signal. Also tabl
en (Tisck, Tisd) (where n = 1 to 9) sets the number of times of switching of the clock signal to a value shown above it, and sets the number of times of switching of the input data signal to a value shown to the left thereof, and Rise fall time Tis
7 is a table showing the amount of deterioration of the setup time, which is created by appropriately changing ck and the rise / fall time Tisd of the input data signal. In FIG. 28, (a) is a table
1 shows an example, and (b) shows an example of table 2. However, in FIGS. 27 and 28, it is assumed that the power supply voltage and the temperature are fixed.

Timing check value deterioration estimating means 71
Is the timing check value 6b of the reliability library 6A.
, A timing check value deterioration degree 72 is obtained.

First, a circuit cell (flip-flop or latch) for which a timing check value after deterioration needs to be obtained
Is extracted from the LSI netlist 9. Then, with respect to all the extracted circuit cells, the deterioration amount of the timing check value is obtained by the following procedure.

For the extracted circuit cell, the LSI before deterioration
Rise and fall time 8 of input signal included in timing 8
With reference to a, the rise and fall times of the clock signal, the input data signal, and the like, which are necessary for obtaining the deterioration amount of the timing check value, are sequentially extracted. Further, with respect to the extracted circuit cell, the number of switching times of the clock signal, the input data signal, and the like necessary for obtaining the amount of deterioration of the timing check value is referred to by referring to the number of switching times 10a of the input signal included in the pre-deterioration result 10. Extract sequentially.

Next, with reference to the timing check value 6b of the reliability library 6A, that is, the operating condition dependency of the amount of deterioration of the timing check value, the extracted rise and fall times of the clock signal and the input data signal and the number of switching times are calculated. A deterioration amount of the timing check value of the circuit cell is obtained. In this case, when the timing check value 6b is represented in a table, it is obtained by interpolation or the like. The obtained deterioration amount of the timing check value of each circuit cell is output to the timing check value deterioration degree 72.

The LSI timing deterioration estimating means 18A
The timing check value 13b of the delay library 13A, which is the timing check value in the LSI before deterioration,
The timing check value in the degraded LSI is obtained by adding the timing check value degradation degree 72 represented by the difference, and is output to the post-degradation LSI timing 14A.

The logic simulator 15A can estimate the change of the clock signal and the input data signal of the flip-flop and the latch in the LSI after the deterioration by the logic simulation.
It is determined whether or not the circuit cell operates normally in LS after deterioration.
The inspection is performed based on the timing check value included in the I timing 14A.

For example, for the flip-flop, the time difference (tc−td) between the time tc at which the clock signal becomes valid and the time td at which the input data signal becomes valid is 3.0 [ns] before deterioration, and after the deterioration. Is the result of a logic simulation based on the post-degradation LSI timing 14A,
It is assumed that the value is 2.2 [nS]. The setup time as a timing check value is 2.1 [n
S] and 2.5 [nS] after deterioration.
At this time, before the deterioration, the time difference (tc−td) is larger than the setup time, so that it is determined that the flip-flop operates normally, but after the deterioration, the time difference (tc−t) is determined.
d) is 0.3 [nS] (=
2.5-2.2) Since there is not enough, the flip-flop does not satisfy the timing check and is determined to malfunction. The logic simulator 15A outputs such a determination result,
It outputs to the result 17A after deterioration.

In each of the embodiments, the LSI timing degradation simulation apparatus is provided with the reliability library generation apparatus 1, but the reliability library generation apparatuses 1 and 1A are not necessarily essential components in the present invention. . That is, the present invention can also be realized as an LSI timing deterioration simulation apparatus that simulates the operation of the LSI after deterioration with reference to the reliability libraries 6 and 6A created in advance.

The above-described first to ninth embodiments have been described by way of example only, and the present invention is not limited thereto. For this reason, there can be another embodiment within the scope of the present invention or a change from this embodiment.

In the first to ninth embodiments,
We dealt with the coupling noise between wirings. Actual L
In the SI, in addition to the coupling noise between the wirings, various noises such as noise via a power supply line inside the LSI, noise via a substrate such as silicon inside the LSI, and thermal noise are generated. Since these noises also affect the hot carrier deterioration of the transistor, it is important that the noise can be analyzed in the deterioration simulation. In the timing deterioration simulation according to the present invention,
In order to treat these noises in the same way as the coupling noise between wirings, a method of equivalently converting and expressing the influence of these noises into a form that can be processed by the simulation device described in each embodiment can be considered.

A description will be given of an example of noise (hereinafter referred to as "power supply noise") via a power supply line inside the LSI. In FIG. 3, it is assumed that the transition of the coupled signal is the generation timing of power supply noise, and that the power supply noise causes a voltage fluctuation of ΔV in the output signal. That is, regarding the power supply noise, the wiring capacitively coupled to the wiring of interest is regarded as its source, and the degree of capacitive coupling is the power supply noise degree, that is, the proportion of noise that propagates from the noise at the power supply noise generation source to the target circuit cell And the signal voltage variation Δ
V is regarded as an amount of power supply noise generated in a circuit cell due to power supply noise and equivalent in terms of hot carrier deterioration. By processing equivalently in this manner, all processing can be handled in the same manner as in the first to ninth embodiments, so that it is possible to simulate noise other than coupling noise between wirings. .

[0182]

As described above, according to the apparatus for simulating the timing deterioration of an LSI of the present invention, the timing deterioration of the circuit cells constituting the LSI can be reduced individually while considering the influence of the coupling noise between the wirings. It can be calculated under the operating conditions where it is placed, and the degradation of the signal path timing can be handled by simulation with the signal flow according to the LSI operation. This has the effect of not including an excessive design margin. Simultaneously, a simulation of timing deterioration in a large-scale circuit of an LSI scale is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an LSI timing degradation simulation apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram conceptually showing a general configuration of a circuit cell.

FIG. 3 is a diagram schematically showing a change in an output signal voltage caused by coupling noise, wherein the output signal is a power supply voltage VD;
It is a figure which shows the case where it becomes high only by ΔV from D.

FIG. 4 is a diagram schematically illustrating a change in an output signal voltage caused by coupling noise, wherein the output signal is a ground voltage GN;
It is a figure showing the case where it becomes lower by ΔV from D.

FIG. 5 is a diagram showing an approximated signal waveform used in a simulation for generating a reliability library.

FIG. 6 is a diagram illustrating an example of information included in the reliability library according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a parasitic capacitance component of an output signal line of an inverter.

FIG. 8 is a diagram illustrating an example of a signal path of an LSI.

FIG. 9 is a table showing a relationship between a degree of capacitive coupling and a signal voltage variation caused by coupling noise.

10 is a diagram illustrating a relationship between a degree of capacitive coupling for each coupling capacitance and a signal voltage variation caused by coupling noise with respect to an output signal line of the inverter illustrated in FIG. 7;

FIG. 11 is a diagram illustrating signal transition of a combined signal that does not affect deterioration.

12 is a diagram illustrating an example of a result of extracting signal transition information for an output signal line of the inverter illustrated in FIG. 7;

FIG. 13 is a block diagram illustrating a configuration of an LSI timing degradation simulation apparatus according to a second embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration of an LSI timing degradation simulation apparatus according to a third embodiment of the present invention.

FIG. 15 is a diagram showing waveforms of an input signal and an output signal of an inverter before and after deterioration.

FIG. 16 is a diagram illustrating an example of information included in a reliability library according to a fourth embodiment of the present invention.

FIG. 17 is a diagram illustrating an example of information included in a reliability library according to the fifth embodiment of the present invention.

FIG. 18 is a block diagram illustrating a configuration of an LSI timing degradation simulation apparatus according to a sixth embodiment of the present invention.

FIG. 19 is a diagram illustrating an example of information included in a reliability library according to the sixth embodiment of the present invention.

FIG. 20 is a diagram illustrating an example of information included in a reliability library according to the sixth embodiment of the present invention.

FIG. 21 is a diagram illustrating a two-input NAND gate as a circuit cell having a plurality of input terminals according to a seventh embodiment of the present invention.

22 is a transistor level circuit diagram of the two-input NAND gate shown in FIG. 21.

FIG. 23 is a diagram illustrating an example of information included in a reliability library according to the seventh embodiment of the present invention.

FIG. 24 is a diagram illustrating an example of a signal path including a plurality of circuit cells, which is a unit of processing according to the eighth embodiment of the present invention.

FIG. 25 is a block diagram showing a configuration of an LSI timing degradation simulation apparatus according to a ninth embodiment of the present invention.

FIG. 26 is a diagram illustrating an example of information of a timing check value included in a delay library according to a ninth embodiment of the present invention, and illustrating information indicating operating condition dependency of a setup time of a flip-flop before deterioration. It is.

FIG. 27 is a diagram illustrating an example of information of a timing check value included in the reliability library according to the ninth embodiment of the present invention, and illustrates information indicating operating condition dependency of a deterioration amount of a setup time of a flip-flop. FIG.

FIG. 28 is a diagram showing an example of timing check value information held by the reliability library according to the ninth embodiment of the present invention, where (a) shows an example of table 1 in FIG. 27 and (b)
Is an example of table 2 in FIG.

FIG. 29 is an example of a normal DSPF netlist.

FIG. 30 is an example of a DSPF netlist to which information on wiring coupling has been added.

[Explanation of symbols]

 Reference Signs List 1, 1A reliability library generation device 2 cell delay deterioration estimating means 3 reliability model 4 circuit reliability simulator 6, 6A reliability library 8a rise / fall time of input signal 9a output load capacitance 9b degree of capacitive coupling 10a switching of input signal Number of times 10b Signal transition information 11 Cell delay deterioration degree 12, 12A, 12B Delay calculator 15, 15A Logic simulator 18, 18A LSI timing deterioration estimating means 20 Circuit cell 21 Input terminal 22 Output terminal 61 Power supply voltage 62 Temperature 70 Deterioration estimating means 71 Timing Check value deterioration estimating means 72 Timing check value deterioration degree

Claims (29)

[Claims] 1. An LSI timing deterioration simulation apparatus for predicting the time-dependent deterioration of an LSI at a design stage and simulating an operation after the deterioration of the LSI, wherein the time-dependent delay of each circuit cell constituting the target LSI is evaluated. The degree of deterioration is determined based on the value of the predetermined operating condition of the circuit cell during the operation of the LSI while referring to a reliability library indicating the dependence of the characteristic deterioration degree of the circuit cell on the predetermined operating condition. Cell delay deterioration estimating means for estimating, and the L which has deteriorated with time based on the degree of delay deterioration of each circuit cell estimated by the cell delay deterioration estimating means.
An LSI timing degradation estimating means for estimating a delay of each circuit cell in the SI; Wherein the cell delay deterioration estimating means estimates the degree of deterioration over time of the delay of each circuit cell in consideration of the influence of coupling noise between wirings. LSI timing degradation simulation apparatus. 2. The LSI timing degradation simulation apparatus according to claim 1, wherein, for each circuit cell, a characteristic deterioration degree of a transistor constituting the circuit cell is obtained by a circuit reliability simulator, and the obtained characteristic deterioration degree of each transistor is obtained. A reliability library generation device for generating the reliability library by obtaining the dependence of the degree of characteristic deterioration of the circuit cell on the predetermined operating condition from the above. 3. The LSI timing deterioration simulation apparatus according to claim 1, further comprising: a delay calculator for estimating a delay of each circuit cell in the LSI before deterioration, wherein the LSI before deterioration estimated by the delay calculator.
Simulating the operation of the LSI before deterioration based on the delay of each circuit cell in the L.
SI timing degradation simulation device. 4. The LSI timing degradation simulation apparatus according to claim 3, wherein said LSI timing degradation estimation means is provided in said delay computer. 5. The LSI timing degradation simulation apparatus according to claim 3, wherein the cell delay degradation estimation means and the LSI timing degradation estimation means are both provided in the delay computer. Deterioration simulation device. 6. The LSI timing deterioration simulation apparatus according to claim 1, wherein the reliability library uses a deterioration degree of a signal propagation delay between an input terminal and an output terminal as the deterioration degree of the characteristic of the circuit cell. A timing deterioration simulation device for an LSI, characterized in that: 7. The LSI timing deterioration simulation apparatus according to claim 6, wherein the reliability library includes a circuit cell, as a predetermined operation condition, a rise and fall time of an input signal, an output load capacitance, and an input signal. Wherein the number of times of switching and the amount of fluctuation of the output signal voltage from the power supply voltage or the ground voltage due to coupling noise are used. 8. The LSI timing deterioration simulation apparatus according to claim 7, wherein the reliability library is configured to deteriorate a signal propagation delay between one input terminal and an output terminal for a circuit cell having a plurality of input terminals. An apparatus for simulating timing deterioration of an LSI, wherein the number of times of switching of an input signal to another input terminal and the rise and fall times are used as predetermined operating conditions with respect to the degree. 9. The LSI timing degradation simulation apparatus according to claim 7, wherein the reliability library uses a power supply voltage applied to a circuit cell as a predetermined operation condition. Timing degradation simulation device. 10. The LSI timing degradation simulation apparatus according to claim 7, wherein the reliability library uses a temperature of a circuit cell as a predetermined operation condition.
Timing degradation simulation device. 11. The LSI timing deterioration simulation apparatus according to claim 6, wherein the reliability library uses a deterioration degree of a rise / fall time of an output signal as the characteristic deterioration degree of the circuit cell. LSI timing degradation simulation apparatus. 12. The LSI timing degradation simulation apparatus according to claim 1, wherein the reliability library indicates a dependency of a timing check value including at least a setup time and a hold time of a circuit cell on a predetermined operation condition. The LSI timing degradation simulation device is:
The degree of deterioration of the timing check value of the circuit cell constituting the target LSI is estimated based on the value of the predetermined operation condition of the circuit cell during the operation of the LSI while referring to the reliability library. A timing check value deterioration estimating means, and wherein the LSI timing deterioration estimating means has deteriorated with time based on the degree of deterioration of the circuit cell timing check value estimated by the timing check value deterioration estimating means. The circuit cell in the LSI is estimated based on the timing check value of the circuit cell estimated by the LSI timing deterioration estimating means. The circuit cell operates normally in the LSI after deterioration. LSI timing characterized by estimating whether or not Degradation simulation apparatus. 13. The LSI timing degradation simulation apparatus according to claim 1, wherein the reliability library represents the dependence of the degree of characteristic degradation of a circuit cell on a predetermined operating condition in a table format. LSI timing degradation simulation device. 14. The LSI timing degradation simulation apparatus according to claim 1, wherein the reliability library represents a function of a degree of characteristic degradation of a circuit cell with respect to a predetermined operation condition. LSI timing degradation simulation device. 15. The LSI timing deterioration simulation apparatus according to claim 1, wherein the reliability library determines a degree of characteristic deterioration of the circuit cell by:
The cell delay deterioration estimating means calculates the degree of delay deterioration of each circuit cell by the difference between the delay before deterioration and the delay after deterioration. An apparatus for simulating timing deterioration of an LSI, comprising: 16. The LSI timing degradation simulation apparatus according to claim 1, wherein the reliability library determines a degree of characteristic degradation of the circuit cell by:
The cell delay deterioration estimating means expresses the degree of delay deterioration of each circuit cell by the ratio between the delay before deterioration and the delay after deterioration. An apparatus for simulating timing deterioration of an LSI, comprising: 17. The LSI timing deterioration simulation apparatus according to claim 1, wherein said cell delay deterioration estimating means includes a signal path including a plurality of circuit cells for at least a part of circuit cells constituting said LSI. Is used to estimate the degree of delay deterioration. The LSI timing deterioration estimating means estimates the degree of delay deterioration in the LSI which has deteriorated with time based on the signal path deterioration estimating means estimated by the cell delay deterioration estimating means. The signal path delay is estimated, and the timing deterioration simulation device for the LSI is
An LSI timing degradation simulation device for simulating an operation of the LSI after deterioration based on the delay of the signal path in the deteriorated LSI estimated by the LSI timing deterioration estimation means. . 18. The LSI timing degradation simulation device according to claim 2, wherein the reliability library generation device performs a simulation of the transistor connected to the output signal of the circuit cell when performing the simulation by the circuit reliability simulator. LS characterized by interrupting or suppressing the forward current of a junction diode formed at the drain
I timing deterioration simulation device. 19. The LSI timing deterioration simulation apparatus according to claim 1, wherein said cell delay deterioration estimating means includes a coupling wiring and a capacitance for coupling noise between wirings with respect to noise other than coupling noise between wirings. The degree of coupling and the amount of signal voltage fluctuation are regarded as noise sources, the degree of noise affecting circuit cells, and the amount of signal voltage fluctuation, and processing is performed equivalently to coupling noise between wirings. LSI timing degradation simulation apparatus. 20. An LSI timing deterioration simulation method for predicting the time-dependent deterioration of an LSI at a design stage and simulating an operation after the deterioration of the LSI, comprising the steps of: The degree of deterioration is determined based on the value of the predetermined operating condition of the circuit cell during the operation of the LSI while referring to a reliability library indicating the dependence of the characteristic deterioration degree of the circuit cell on the predetermined operating condition. A cell delay deterioration estimating step of estimating, and the LS deteriorated with time based on the delay deterioration degree of each circuit cell estimated in the cell delay deterioration estimating step.
An LSI timing deterioration estimating step of estimating a delay of each circuit cell in I, and simulating an operation of the LSI after deterioration based on the delay of each circuit cell in the LSI after the deterioration estimated in the LSI timing deterioration estimating step. A cell delay deterioration estimating step for estimating a time-dependent deterioration degree of a delay of each circuit cell in consideration of an influence of coupling noise between wirings. An LSI timing degradation simulation method. 21. A method of simulating timing deterioration of an LSI according to claim 20, wherein for each circuit cell, a degree of characteristic deterioration of a transistor constituting the circuit cell is obtained by driving a circuit reliability simulator, and the obtained degree of each transistor is obtained. A reliability library generating step of generating the reliability library by obtaining a dependence of the characteristic deterioration degree of the circuit cell on the predetermined operating condition from the characteristic deterioration degree. Simulation method. 22. The LSI timing deterioration simulation method according to claim 20, wherein the reliability library uses a deterioration degree of a signal propagation delay between an input terminal and an output terminal as the degree of characteristic deterioration of the circuit cell. A timing degradation simulation method for an LSI, characterized in that: 23. The LSI timing deterioration simulation method according to claim 22, wherein the reliability library includes, as predetermined operating conditions, a rise time and a fall time of an input signal, an output load capacitance, and an input signal of a circuit cell. Using the number of times of switching and the amount of fluctuation of an output signal voltage from a power supply voltage or a ground voltage due to coupling noise. 24. The method for simulating timing deterioration of an LSI according to claim 23, wherein the reliability library is configured to deteriorate a signal propagation delay between one input terminal and an output terminal for a circuit cell having a plurality of input terminals. A method for simulating timing deterioration of an LSI, wherein the number of times of switching of an input signal to another input terminal and the rise and fall times are used as predetermined operating conditions with respect to the degree. 25. The LSI timing degradation simulation method according to claim 23, wherein said reliability library uses a power supply voltage applied to a circuit cell as a predetermined operation condition. Timing degradation simulation method. 26. The LSI timing degradation simulation method according to claim 23, wherein the reliability library uses a temperature of a circuit cell as a predetermined operating condition.
Timing degradation simulation method. 27. The method according to claim 22, wherein the reliability library uses the degree of deterioration of the rise / fall time of the output signal as the degree of characteristic deterioration of the circuit cell. LSI timing degradation simulation method. 28. The method for simulating timing deterioration of an LSI according to claim 20, wherein said cell delay deterioration estimating step includes a signal path including a plurality of circuit cells for at least a part of circuit cells constituting said LSI. The LSI timing deterioration estimating step is based on the signal path delay deterioration degree estimated in the cell delay deterioration estimating step. The delay of the signal path is estimated, and the simulation step simulates the operation of the LSI after deterioration based on the signal path delay in the LSI after the deterioration estimated in the LSI timing deterioration estimation step. LSI timing degradation system Simulation method. 29. An LSI netlist referred to by the LSI timing deterioration simulation apparatus according to claim 1, wherein a wiring capacitance element can be recognized as a capacitance to ground when calculating the timing of the LSI, and coupling noise between wirings is obtained. An LSI netlist which is described so that it can be recognized as a wiring capacitance between the wiring and a wiring capacitively coupled to the wiring at the time of calculation.