JPH11218561A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the testing process omissible by frequency-dividing clock signal, passing it through a critical path and inputting it to a signal processing means and connecting the output and the clock signal to a measurement means by way of another signal processing means. SOLUTION: The logical product of an output signal 2A of clock signal frequency divider 21 and an output signal 2B having passed a critical path γconstituted of a plurality of logic gates 22 is calculated by an AND circuit 26 of the first signal processing means. The output signal 2C and a system clock signal 2E from an external system clock input part 24 are input in the NAND circuit 27 of the second signal processing means to perform an operation. The number of pulses obtained by the operation is counted by a binary counter 23 of a measurement means. That is, the difference between the signal 2A and the signal 2B is obtained, and the operating speed is judged by a possible operating speed judgment circuit. By this constitution, an operating speed selection test can be done inside the chip by a self test circuit and test items may be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which the operable speed varies due to variations in operating characteristics caused by variations in the semiconductor manufacturing process. The present invention relates to a configuration in which the operable speed of a circuit is measured and recorded, and used in accordance with each operable speed.

[0002]

2. Description of the Related Art In recent years, the dimensions and arrangement of each element constituting a semiconductor integrated circuit have been miniaturized due to the semiconductor process technology following the trend of miniaturization, and variations in the dimensions and arrangement of actually manufactured elements relative to design values have become relatively large. It is getting bigger. For this reason, even if chips have the same design and the same function,
The operation speed of actually manufactured products varies.

On the other hand, the demand for high-speed operation of systems such as personal computers has been increasing in recent years, and semiconductor chips capable of high-speed operation have added value as compared with ordinary products. On the other hand, there is a strong market demand for supply of inexpensive semiconductor chips even if the speed is not so high.

In order to meet the demands of these various markets, it is necessary to select the speed of chips manufactured in the same manufacturing process, that is, perform speed binding. However, there are two major problems in performing such an operation speed selection test. One is that the number of test steps is increased, resulting in an increase in cost and an increase in manufacturing time.

Another problem is how and where information obtained by the speed selection test is held in a readable state, and how to read it electrically when necessary. This is because, when the semiconductor chip is actually operated at the system level, the system controller needs to refer to the speed selection information for each semiconductor chip in order to operate the system at the optimum speed of the semiconductor chip.

For this reason, for example, as shown in FIG. 10, a conventional SIMM (Single In-line Memory Module) or
In an IMM (Dual In-line Memory Module) or the like, a nonvolatile memory 105 such as an EEPROM is mounted on a system board 107 and semiconductor chips 101 to 104 are mounted thereon.
The speed information for each speed is written and held, and the system controller 106 deals with this by referring to this information.

The conventional technique will be described below with reference to FIG. As shown in FIG. 10, reference numeral 101 denotes an integrated circuit A, 102 denotes an integrated circuit B, 103 denotes an integrated circuit C, and 104 denotes an integrated circuit D arranged on a system board 107.
106, a system system controller;
Are the integrated circuits A, B, C, D and the system controller 10
6 is a non-volatile memory holding operable speed information.

Further, the nonvolatile memory 105 and the system controller 106 can be electrically referred to, and similarly, the nonvolatile memory 105 and the integrated circuits A to D can also be electrically referred to.

As the number of elements mounted on one semiconductor chip has increased remarkably and the number of chips in a system has been reduced as in today, a dedicated non-volatile memory for storing operable speed information on the system board 107 has been proposed. In the case where one is mounted, the cost of the non-volatile memory is relatively high in the entire system, which is disadvantageous in cost as a whole. In addition, there is a problem that the installation area on the system board 107 is reduced, which hinders an increase in the density of the installation area.

[0010]

With the semiconductor process technology following the trend of miniaturization, relative variations in dimensions, arrangements and the like of actually manufactured products increase with the absolute reduction of dimensions and mutual arrangement of elements. In other words, even if the semiconductor chips have the same design and the same function, there is a problem that the operation speed varies among the semiconductor chips. In addition, it is necessary to select a chip that requires high-speed operation and a chip that is inexpensive at the latest, and thus it is necessary to select an operation speed of the chip. For this reason, the number of test steps is increased, and costs are increased due to an increase in manufacturing time, and problems such as a method of retaining sorting information are caused. The present invention has been made in view of the above problems, and provides a semiconductor integrated circuit that can omit a test process and does not need to hold selection information by an external memory.

[0011]

A semiconductor device according to the present invention is a circuit for measuring a signal delay in a predetermined critical path in a signal processing circuit in a semiconductor integrated circuit,
A clock signal divider that divides a system clock signal to generate an input signal to the critical path, and a first signal processing that inputs a comparison signal and a signal after the input signal has passed through the critical path Means, second signal processing means for receiving an output signal from the first signal processing means and the system clock signal as inputs, and measuring means connected to an output of the second signal processing means. A semiconductor integrated circuit including a delay measurement circuit.

The comparison signal is the input signal to the critical path, the first signal processing means is an AND circuit, and the second signal processing means is NAN.
The semiconductor integrated circuit is a D circuit, and the measuring means is a binary counter. Further, in the semiconductor integrated circuit, the predetermined critical path includes a plurality of logic gates. Further, the predetermined critical path is an address decoder circuit of a memory formed in the semiconductor integrated circuit, the first signal processing means is a NAND circuit, and the second signal processing means is an AND circuit A semiconductor integrated circuit characterized by the following.

Further, the critical path includes a CR distributed constant path, and the first signal processing means is a voltage comparison comparator which inputs an output signal from the critical path and a comparison voltage signal. It is a semiconductor integrated circuit. Further, in the semiconductor integrated circuit, the CR distributed constant path is a column selection line or a row selection line of a memory formed in the semiconductor integrated circuit.

A semiconductor integrated circuit having a memory for recording information for selecting an operation speed and an operable speed discrimination circuit for outputting an operation speed judgment signal based on an output signal of the measuring means. It is. The semiconductor integrated circuit further includes a register connected to an output of the operable speed determination circuit. Further, there is provided a semiconductor integrated circuit having an output terminal which enables the output of the register to be electrically referred to within the semiconductor integrated circuit to be processed and from an external circuit.

A semiconductor device according to the present invention is a circuit for measuring a signal delay in a predetermined critical path in a signal processing circuit in a semiconductor integrated circuit. A clock signal divider for generating an input signal, signal processing means for receiving the input signal and the signal after the input signal has passed through the critical path, and outputting a signal related to a signal delay in the critical path, A delay-measurement circuit having time-voltage value conversion means for converting an output signal from the signal processing means into a voltage value and outputting the voltage value, and at least one voltage comparison comparator for comparing the voltage value with at least one predetermined comparison voltage; A semiconductor integrated circuit comprising:

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the following embodiments with reference to the drawings, but the present invention is not limited to the embodiments described here. The following embodiments can be variously changed. An embodiment of the present invention will be described below with reference to FIGS.

First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a diagram illustrating a configuration of a semiconductor integrated circuit according to the present invention. Reference numeral 2 denotes a semiconductor integrated circuit, of which 1 is a circuit function body, 3 is a register, 4 is an operable speed determination circuit, and 5 is an operation speed measurement circuit. FIG. 1B shows a system board 11 on which the semiconductor integrated circuit is mounted, 6 is a system controller,
Reference numerals 7 to 10 denote a plurality of semiconductor integrated circuits A to D having the configuration of the present invention used by the system board 11.

The operating speed measuring circuit 5 is a circuit for measuring a delay in a critical path (a path requiring the shortest time among many paths) of the semiconductor integrated circuit. 1 can be referred to electrically.

The operable speed determining circuit 4 can be electrically referred to by the register 3 and the operating speed measuring circuit 5. The register 3 has an output terminal for electrically referring to the circuit function body 1 of the semiconductor integrated circuit 2, the integrated circuits (excluding the integrated circuits 7 to 10, and the integrated circuit 2) of FIG. 2 and the system board controller 6.

The configuration of the system board 11 is shown in FIG.
As shown in FIG. 1, the system controller 6 and the semiconductor integrated circuits A to D including the circuit function body, the register, the operable speed determination circuit, and the operation speed measurement circuit shown in FIG. Things.
The system board 11 does not require an external non-volatile memory 105 as compared with FIG.

FIG. 2A is a block diagram showing the configuration of the self-test circuit according to the first embodiment of the present invention, that is, the operation speed measurement circuit 5 of FIG. 1, where γ is a factor that determines the operation speed of the circuit. Is the critical path. In FIG. 2A, reference numeral 21 denotes a clock signal divider, and reference numeral 22 denotes a block diagram of a plurality of logic gates forming a critical path. Reference numeral 23 denotes a binary counter which is a means for measuring a delay time, and 24 denotes an input terminal of an external system clock.
E is a system clock signal. The output of 25 is connected to the operable speed determination circuit 4 of FIG.

The circuit of the type shown in FIG. 2A is particularly effective when the circuit of the critical path γ includes a plurality of logic gates. The operable speed information thus measured and held in the register 3 of FIG. 1 is referred to from inside and outside the integrated circuit to determine the operation speed of the entire system.

The operation speed measuring circuit 5 shown in FIG. 2 measures the delay time of the critical path γ, which is a factor for determining the operation speed of the circuit function body 1 shown in FIG. Further, the register 3 can be electrically referenced from a desired component in the semiconductor integrated circuit 2 and an external system controller 6.

As shown in FIG. 2, in this circuit configuration, in order to measure the delay time α of the critical path γ, the signal after passing through the critical path γ by the AND circuit 26 as the first signal processing means is measured. Frequency output signal 2B
And the frequency divider output signal 2A as a comparison signal that does not pass through the critical path γ. Then, the output signal 2C and the system clock signal 2E from the external system clock input section 24 are input to the NAND circuit 27 as the second signal processing means, and are operated. Then, the number of pulses, which is the result of the calculation, is measured by the binary counter 23 as the measuring means. That is, the difference between the two signals 2A and 2B is calculated by the binary counter 23 as the measuring means.

After the number of pulses is counted by the binary counter 23, the information is used to determine the operating speed by, for example, an operable speed determining circuit as shown in FIG. 8 shown in FIG.
Reference numeral 1 denotes a ROM having comparison information for determining the speed, 83 denotes a binary comparator, and 82 outputs an operation speed determination signal. The operation speed determination signal is, for example, a signal indicating the optimum operation speed for the semiconductor integrated circuit. The signal input from 84 is the operating speed information from the terminal 25 in FIG. 2 counted by the operating speed measuring circuit 5 (counted by the binary counter 23 in FIG. 2). Note that the delay time α of the critical path γ can be calculated from the difference from the frequency-divided signal, and the result can be output and held in the register 3 shown in FIG.

FIG. 2B is a timing chart of FIG. 2A, in which the external system clock signal 24, the frequency-divided signal 2
A, a signal 2B obtained by converting the signal 2B passing through the critical path γ and the AND signals 2C and 2C with the system clock signal
The timing of the waveform D is shown.

After the signal 2A becomes HIGH, the signal 2A
The time α until B becomes HIGH indicates the delay time due to the critical path of the circuit. The signal 2C is obtained by ANDing the signal 2A and the signal 2B, and the signal 2D is obtained by NANDing the time when the signal 2C is HIGH and the system clock. As shown in FIG. 2B, when the time during which the signal 2D is HIGH and LOW is β, the HIGH and LOW signals are counted by the binary counter 23 during the time β.

This measurement allows a self-test circuit in the integrated circuit chip to perform a test for selecting operating speed after packaging in a conventional integrated circuit.

FIG. 3 shows an example in which the operating speed measuring circuit 5 of FIG. 2 is specifically applied to an address decoder 39 of a memory. Note that the address decoder 39 in FIG. 3 is a generalized drawing of the address decoder of the memory. In practice, the address does not need to be only 2 bits, but is simplified.

As shown in FIG. 3, 31 is an operation speed discrimination circuit, 32 is a binary counter, 33 is a row or column selection line <3> for measuring delay time, and 34 is a row or column selection line <2.
>, 35 are row or column selection lines <1>, 36 is row or column selection lines <0>, 37 is a frequency divider, 38 is a system clock input unit, 3C is a system clock signal, and 39 is an address decoder. Here, the reason why the term “row” or “column” is used is that the basic operation mechanism is the same for the row address decoder and the column address decoder of the memory, and the same can be applied.

As shown in FIG. 3, first, the system clock signal 3C from the system clock input section 38 is divided by the frequency divider 3
7 to generate a frequency-divided long-period pulse 3A, which is input to the address decoder 39.
As the address, 01 is selected.

Along with this, for example, to measure the delay time, the row or column selection line <3> 33 of the address decoder 39 is selected. Here, a time delay occurs until the row or column selection line <3> 33 corresponding to the input address is selected. The row or column selection line <3> 3 thus generated
The phase difference between the delayed output signal 3B of FIG. 3 and the original signal 3A is calculated by performing a NAND operation in the NAND circuit (40), and the output signal 3E is compared with the system clock signal 3C in the AND circuit (41). Then, it is counted by the binary counter 32. The phase difference corresponds to a delay time of the address decoder 39.

At this time, each part, the divided system clock signal 3A, and the address decoder 3 for measuring the delay time
9 is a logical product signal 3E of the output signals 3B, 3A and 3B, a system clock signal 3C, and a waveform of a signal 3D obtained by converting the logical product signal 3E by the system clock signal 3A. NAND of signal 3A and signal 3B is signal 3E
And is counted by the binary counter 32 as compared with the system clock signal 3E.

Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment of the present invention shown in FIG. 5 has the same basic system configuration as that of FIG. FIG. 5 shows a configuration of a portion corresponding to the configuration of the operation speed measurement circuit of FIG. The clock signal divider 54 divides the frequency of the system clock signal from the system clock input unit 56 and leads to the critical path γ including the CR distributed constant path 53. The delay of the output signal 5C is counted by the system clock signal 5E and the binary counter 52. The signal 51 output from the binary counter 52 is sent to the operable speed determination circuit 4 in FIG. As shown in FIG. 5A, in the configuration of the operation speed measuring circuit in FIG. 5, the pulse 5B passing through the critical path γ causes the delay time of the critical path γ to be equal to the comparison signal Vref (V).
Is defined as τvref, the above-mentioned τvref
To the voltage comparison comparator 55 as the first signal processing means.
To detect. Further, the signal 5C expressing the delay time τvref of the critical path detected therefrom and the system clock signal 5E are transferred to the NAND circuit 56 as the second signal processing means.
And counts the pulse output of the NAND circuit 56 through the binary counter 52 to perform measurement.

FIG. 5B shows an external system clock signal 5E, a divided signal 5A, a voltage signal Vref as a comparison signal, a signal 5B passed through a critical path γ, and an output signal of the voltage comparison comparator 55 in the above circuit. 5C,
And the waveform of a signal 5D obtained by converting this signal with the system clock signal 5E. The time interval 55 is a delay time due to the critical path γ.

The operating speed information of the semiconductor integrated circuit measured by the operating speed measuring circuit is used to determine the operable speed by the operable speed discriminating circuit of FIG. 8 as in the first embodiment. It is held in the register 3 of FIG. 1 so that it can be referred to from the system controller inside and outside the chip.

FIG. 6 shows an example in which the operation speed measurement circuit of FIG. 5 is applied to the measurement of the delay of the WORD line (column selection line) of the memory. In principle, the same method can be used to measure the delay time of the row selection line. In particular, since a large number of select and non-select switch transistors are connected to the WORD line of a general memory, the load capacity becomes very heavy, and the factors that determine the delay time of the operation speed of the memory are as follows. , One of the big ones.

As the load capacitance becomes heavier, the operation speed measuring circuit becomes more effective for measuring the delay time of the WORD line. As shown in FIG. 6, the system clock input unit 6
The signal 6E from 1 is input to the frequency divider 62 to generate a pulse having a long cycle. Next, the signal is input to the WORD line driver 65, and the driver signal 6A is output.

The signal 6A reaches the farthest point of the WORD line driver through the WORD line 68, and the reaching signal 6B is compared with VREF by the comparator 66. 67
Is calculated by The signal 6D output from the NAND circuit 67 is counted by the binary counter 63 and sent to the operation speed determination circuit 64.

Since the WORD line 68 has a heavy load capacitance as described above, the waveform farthest from the WORD line driver 65 has a very rising waveform (FIG. 7).
reference). WAO until this waveform rises almost completely
It is considered as the delay time of the RD line 68. For example, assuming that the voltage rises to 90% of the full swing voltage, the voltage is measured by measuring the voltage VX of the output signal 6B at the far end of the WORD line and the comparison voltage VREF, for example, the full swing voltage VPP. The 90% voltage is compared by a voltage comparison comparator 66, a signal 6C indicating a period of VX <VREF is converted by a system clock signal 6E, and the number of clock pulses is counted by a binary counter 63 and measured as a delay time. .

The method using the above-described second embodiment of the present invention is effective for determining an operable speed in a case where a wiring delay, which is mainly caused by a capacitive delay and a resistive delay, becomes a critical path. is there.

A third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the operability determination circuit of FIG. 8 is modified. As shown in FIG. 9, reference numeral 91 denotes a time-voltage value conversion circuit, 93 denotes a logic circuit that enables selection of a plurality of items, and a judgment output from the logic circuit 93 that enables selection of the plurality of items. The resulting output is 92.

Delay time information (signal 2C of FIG. 2 and FIG. 5
Of the first embodiment of the present invention and the second signal 5C) of the present invention.
As in the embodiment, the pulse width indicating the delay time information is converted into a voltage value by the capacitor 95 without being counted by the system clock and the binary counter, and compared by the voltage comparison comparator 94.

At this time, as shown in FIG. 9, the number of the voltage comparison comparators 94 can be increased as necessary, and can correspond to various reference voltages (Vref 1 to Vref N).

The above-described embodiment in which the time-voltage value conversion circuit 91 converts the pulse width-voltage value and compares it with the reference voltage by the voltage comparison comparator 94 is described in the first embodiment of the present invention and the present invention. This is applicable to the critical path delay determination of the second embodiment.

[0046]

Conventionally, an EEPROM on a system board
The operation speed information of the chip which has been written in the non-volatile memory such as the EEPROM can be held in the chip.
You do not need to use. This has the advantage that the cost can be reduced and the density of the entire system board can be increased.

Further, the test for selecting the operation speed, which has been conventionally performed after packaging, is performed by a self-test circuit in the chip, so that the number of test items can be reduced, thereby reducing the cost of the chip.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an overall image according to an embodiment of the present invention.

FIGS. 2A and 2B are a block diagram showing a configuration of an operation speed measuring circuit according to the first embodiment of the present invention, and a timing diagram showing characteristics, respectively;

FIG. 3 is a diagram showing an embodiment in which the operating speed measuring circuit according to the first embodiment of the present invention is applied to an address decoder of a memory.

FIG. 4 is a timing chart showing characteristics of an address decoder of the memory according to the first embodiment of the present invention.

FIGS. 5A and 5B are a block diagram showing a configuration of an operation speed measuring circuit according to a second embodiment of the present invention, and a timing chart showing characteristics.

FIG. 6 is a diagram showing a form in which an operation speed measurement circuit according to a second embodiment of the present invention is adapted to measurement of a delay of a WORD line (column selection line) of a memory.

FIG. 7 shows a WOR of a memory according to a second embodiment of the present invention;
FIG. 9 is a timing chart showing characteristics of delay measurement of a D line (column selection line).

FIG. 8 is a diagram showing an operable speed determination circuit of the present invention.

FIG. 9 is a diagram showing an operable speed determination circuit according to a third embodiment of the present invention.

FIG. 10 is a schematic diagram showing an example in which a nonvolatile memory element holding operable speed information is mounted on a system board in a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Circuit function main body 2 ... Semiconductor integrated circuit chip according to the present invention 3 ... Register 4 ... Operable speed discriminating circuit 5, 31 ... Operating speed measuring circuit 6 ... System controller 7 ... Integrated circuit A 8 ... Integrated circuit B 9 ... Integrated Circuit C 10 Integrated circuit D 11 System board 21, 54, 62 Clock signal divider 22 Logic gate block 23, 52, 63 Binary counter 24, 38, 56, 61 Input section for external system clock 25 ... Output signal to operable speed determination circuit 26 ... AND circuit 27 ... NAND circuit 32 ... Binary counter 33 ... Row or column selection line <3> 34 ... Row or column selection line <2> 35 ... Row or column selection line <1> 36: Row or column selection line <0> 37 ... Divider 39 ... Address decoder 40 ... NAND circuit 41 ... AND circuit 51 ... Operable Output signal to degree determination circuit 53: Path representing CR distribution constant 55, 66, 94 ... Voltage comparison comparator 56, 67 ... NAND circuit 64 ... Operating speed determination circuit 65 ... WORD line driver 68 ... WORD line 91 ... Time-voltage Value conversion circuit 92 ... determination result output 93 ... logic circuit 95 ... capacitance 101 ... integrated circuit A 102 ... integrated circuit B 103 ... integrated circuit C 104 ... integrated circuit D 105 ... integrated circuits A, B, C, D and system controller Non-volatile storage element holding operable information 106 ... System controller 107 ... System board 108 ... Semiconductor integrated circuit 109 ... Circuit function body 110 ... Operating speed measuring circuit 111 ... Operating speed discriminating circuit 112 ... Register 2A ... Critical path Signal 2B not passing through γ 2B ... Signal 2 passing through critical path γ C: logical product signal of 2A and 2B 2D: NAND circuit output signal 2E: external system clock signal 3A: output signal of frequency divider 37 3B: address decoder output signal 3C: external system clock signal 3D: delay time pulse Signal 5A: Output signal of frequency divider 54 5B: Critical path γ pass signal 5C: Delay time signal 5D: Pulse signal of delay time 5E: External system clock signal 6A: WORD line driver signal 6B: WORD line output signal 6C: Comparison Signal 6D: pulse signal of delay time 6E: external system clock signal α: delay due to critical path of circuit β: signal counted by binary counter γ: critical path to determine operation speed of circuit

Claims (10)

[Claims] 1. A circuit for measuring a signal delay in a predetermined critical path in a signal processing circuit in a semiconductor integrated circuit, wherein the clock signal generates a signal input to the critical path by dividing a system clock signal. A frequency divider; a first signal processing unit that receives a comparison signal and a signal after the input signal has passed through the critical path; an output signal from the first signal processing unit and the system clock signal; A semiconductor integrated circuit, comprising: a delay measuring circuit having a second signal processing unit that receives an input of the second signal processing unit and a measuring unit connected to an output of the second signal processing unit. 2. The method according to claim 1, wherein said comparison signal is said input signal to said critical path, and said first signal processing means is an AND signal.
2. The semiconductor integrated circuit according to claim 1, wherein said second signal processing means is a NAND circuit, and said measuring means is a binary counter. 3. The semiconductor integrated circuit according to claim 1, wherein said predetermined critical path includes a plurality of logic gates. 4. The semiconductor device according to claim 1, wherein the predetermined critical path is an address decoder circuit of a memory formed in the semiconductor integrated circuit, the first signal processing means is a NAND circuit, and the second signal processing means is an AND circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a circuit. 5. A method according to claim 1, wherein said critical path includes a CR distributed constant path, and said first signal processing means is a voltage comparison comparator which receives an output signal from said critical path and a comparison voltage signal. The semiconductor integrated circuit according to claim 1. 6. The semiconductor integrated circuit according to claim 5, wherein said CR distributed constant path is a column selection line or a row selection line of a memory formed in said semiconductor integrated circuit. 7. An operable speed discrimination circuit having a memory for recording information for selecting an operation speed and outputting an operation speed judgment signal based on an output signal of said output means. The semiconductor integrated circuit according to claim 6. 8. The semiconductor integrated circuit according to claim 7, further comprising a register connected to an output of said operable speed discriminating circuit. 9. The semiconductor integrated circuit according to claim 8, wherein said register has an output terminal which enables the output of said register to be electrically referred to within said semiconductor integrated circuit and from an external circuit. 10. A circuit for measuring a signal delay in a predetermined critical path in a signal processing circuit in a semiconductor integrated circuit, wherein the clock signal generates a signal input to the critical path by dividing a system clock signal. A frequency divider; a signal processing unit that receives the input signal and the signal after the input signal has passed through the critical path and outputs a signal related to a signal delay in the critical path; and an output signal from the signal processing unit. And a delay measurement circuit having at least one voltage comparison comparator for comparing the voltage value with at least one predetermined comparison voltage. Semiconductor integrated circuit.