JPH11215380A - Image-processing unit - Google Patents

Image-processing unit

Info

Publication number
JPH11215380A
JPH11215380A JP2771898A JP2771898A JPH11215380A JP H11215380 A JPH11215380 A JP H11215380A JP 2771898 A JP2771898 A JP 2771898A JP 2771898 A JP2771898 A JP 2771898A JP H11215380 A JPH11215380 A JP H11215380A
Authority
JP
Japan
Prior art keywords
processing
image
components
encoding
image processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2771898A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Oizumi
充弘 大泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP2771898A priority Critical patent/JPH11215380A/en
Publication of JPH11215380A publication Critical patent/JPH11215380A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)
  • Color Television Systems (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an image-processing unit where high-speed parallel processing is attained so as to minimize a waiting time in processing by efficiently using a plurality of encoding devices. SOLUTION: Original images R, G, B consisting of a plurality of components (figure A) are divided into a plurality of blocks R0-R3, G0-G3, B0-B3 (figure B), and parallel processing is applied to each component of each block (figure D) by the use of a plurality of encoding devices 11-13 (figure C). The number of the encoding devices 11-13 (number is 3 in the figure) is selected to be an integral multiple of the number of components (3 in the figure). Thus, image processing having no an idle processing time is attained, so that a waiting time of the processing of each coder is eliminated, and highly efficient coding is attained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、画像処理装置、よ
り詳細には、画像処理装置におけるデータの圧縮伸長に
係り、特に、画像データのデータ圧縮伸長に関わるもの
であるが、その他に、プリンタ,FAX,データ通信な
どに応用可能なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to compression and expansion of data in an image processing apparatus, and more particularly to data compression and expansion of image data. , FAX, data communication, etc.

【0002】[0002]

【従来の技術】画像データの圧縮伸長方式として、従
来、国際標準であるJPEGなどが知られている。ま
た、特開平7−135652号公報に記載されているよ
うに、DCT演算と量子化演算を同時に実行することに
より、静止画データの圧縮,伸長処理の高速化を狙った
ものがある。
2. Description of the Related Art As a method for compressing and expanding image data, JPEG, which is an international standard, is conventionally known. Further, as described in Japanese Patent Application Laid-Open No. Hei 7-135652, there is an image processing apparatus that aims to speed up the compression and decompression processing of still image data by simultaneously executing a DCT operation and a quantization operation.

【0003】[0003]

【発明が解決しようとする課題】従来の符号化技術で
は、一つの符号化装置で複数のコンポーネントを処理し
ていたため、1画像の処理に時間がかかっていた。図3
は、従来の符号化装置の一例を説明するための図である
が、従来の符号化処理は、図3(A)に示すような3つ
のコンポーネントR,G,Bから成る原画像の各コンポ
ーネントを、図3(B)に示すように、4個のブロック
(R0,R1,R2,R3:G0,G1,G2,G3:
B0,B1,B2,B3)に分割して符号化することを
考えると、図3(C)に示すような、一つの符号化装置
31を有する画像処理装置30で処理した場合には、各
ブロックをシリアル処理するため、図3(D)に示すよ
うに、R0,G0,B0…R3,G3,B3となり、長
い処理時間を要してしまう。
In the conventional encoding technique, a single encoding device processes a plurality of components, so that it takes time to process one image. FIG.
FIG. 3 is a diagram for explaining an example of a conventional encoding device. In the conventional encoding process, each component of an original image including three components R, G, and B as shown in FIG. As shown in FIG. 3B, four blocks (R0, R1, R2, R3: G0, G1, G2, G3:
B0, B1, B2, and B3), and considering encoding, when the image is processed by the image processing device 30 having one encoding device 31 as shown in FIG. Since the blocks are serially processed, R0, G0, B0,... R3, G3, and B3, as shown in FIG. 3D, require a long processing time.

【0004】また、図4(A)に示すように、2つの符
号化装置41,42を有する画像処理装置40を用いて
処理する場合には、図4(B)に示すように、一つの符
号化装置で処理する場合よりは短い時間で処理を終える
ことができるが、処理時間の空き(空き0,空き1,空
き2,空き3)ができてしまい効率化を妨げてしまう。
As shown in FIG. 4A, when processing is performed using an image processing device 40 having two encoding devices 41 and 42, as shown in FIG. Although the processing can be completed in a shorter time than the case where the processing is performed by the encoding apparatus, the processing time becomes vacant (empty 0, empty 1, empty 2, empty 3), and efficiency is hindered.

【0005】本発明は、上述のごとき実情に鑑みてなさ
れたもので、特に、複数の符号化装置を効率よく用いる
ことにより、処理の待ち時間を極力なくし、高速な並列
処理が可能な画像処理装置を提供することを目的として
なされたものである。
[0005] The present invention has been made in view of the above-mentioned circumstances, and in particular, by using a plurality of encoding devices efficiently, the processing waiting time is minimized and the image processing capable of high-speed parallel processing. It is intended to provide a device.

【0006】[0006]

【課題を解決するための手段】本発明は、複数のコンポ
ーネントから構成される原画像を、複数のブロックに分
割し、複数の符号化装置を用いて各ブロックのコンポー
ネント毎に並列処理を行う画像処理装置において、前記
符号化装置の数を前記コンポーネントの数の整数倍と
し、処理時間に空きのない画像処理を可能にしたことを
特徴とし、もって、各符号化装置の処理の待ち時間を無
くし、高効率の符号化を行うようにしたものである。
SUMMARY OF THE INVENTION The present invention divides an original image composed of a plurality of components into a plurality of blocks, and performs parallel processing for each component of each block using a plurality of encoding devices. In the processing device, the number of the encoding devices is set to an integral multiple of the number of the components to enable image processing with no processing time, thereby eliminating the waiting time of the processing of each encoding device. , Highly efficient encoding is performed.

【0007】[0007]

【発明の実施の形態】図1は、本発明による画像処理装
置の一実施例を説明するための図で、図1(A)に示す
ような3つのコンポーネントR,G,Bから成る原画像
を、図1(B)に示すように、4個のブロックR0,R
1,R2,R3:G0,G1,G2,G3:B0,B
1,B2,B3に分割して符号化する場合、例えば、図
1(C)に示すような3個の符号化装置11,12,1
3を有する画像装置10で処理を行うと、その結果は、
図1(D)に示すように、符号化装置11,12,13
を処理時間に空きのないように並列使用することがで
き、高効率の処理を行うことができる。
FIG. 1 is a diagram for explaining an embodiment of an image processing apparatus according to the present invention. FIG. 1 shows an original image composed of three components R, G and B as shown in FIG. As shown in FIG. 1B, four blocks R0, R0
1, R2, R3: G0, G1, G2, G3: B0, B
1, B2, and B3, when encoding is performed, for example, three encoding devices 11, 12, 1, 1 as shown in FIG.
When the processing is performed by the image device 10 having
As shown in FIG. 1 (D), the encoding devices 11, 12, 13
Can be used in parallel so that there is no free processing time, and highly efficient processing can be performed.

【0008】図2は、本発明の他の実施例を説明するた
めの図で、図1(A)に示したような3つのコンポーネ
ントR,G,Bから成る原画像を、図1(B)に示した
ように、4個のブロックに分割して符号化する場合、例
えば、図2(A)に示すような6個の符号化装置21,
22,23,24,25,26を有する画像処理装置2
0で処理を行うと、その結果は、図2(B)に示すよう
になり、図1に示した場合よりも更に高効率の処理を行
うことができる。
FIG. 2 is a diagram for explaining another embodiment of the present invention. An original image composed of three components R, G, and B as shown in FIG. As shown in FIG. 2), when encoding is performed by dividing into four blocks, for example, as shown in FIG.
Image processing apparatus 2 having 22, 23, 24, 25, 26
When the process is performed at 0, the result is as shown in FIG. 2B, and the process can be performed with higher efficiency than the case shown in FIG.

【0009】[0009]

【発明の効果】複数のコンポーネントから構成される原
画像を、複数のブロックに分割し、複数の符号化装置を
用いて各ブロックのコンポーネント毎に並列処理を行う
画像処理装置において、前記符号化装置の数を前記コン
ポーネントの数の整数倍とし、処理時間に空きのない画
像処理を可能にし、各符号化装置の処理の待ち時間を無
くしたので、高効率の符号化を行うことができる。
According to the present invention, there is provided an image processing apparatus for dividing an original image composed of a plurality of components into a plurality of blocks and performing parallel processing for each component of each block using a plurality of coding apparatuses. Is set to an integral multiple of the number of the components, enabling image processing with no space in the processing time, and eliminating the waiting time of the processing of each encoding device, so that highly efficient encoding can be performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による画像処理装置の一例を説明する
ための図である。
FIG. 1 is a diagram illustrating an example of an image processing apparatus according to the present invention.

【図2】 本発明による画像処理装置の他の例を説明す
るための図である。
FIG. 2 is a diagram for explaining another example of the image processing apparatus according to the present invention.

【図3】 従来の画像処理装置の一例を説明するための
図である。
FIG. 3 is a diagram illustrating an example of a conventional image processing apparatus.

【図4】 従来の画像処理装置の他の例を説明するため
の図である。
FIG. 4 is a diagram for explaining another example of the conventional image processing apparatus.

【符号の説明】[Explanation of symbols]

10,20,30,40…画像処理装置、11,12,
13,21,22,23,24,25,26,31,4
1,42…符号化装置。
10, 20, 30, 40 ... Image processing device, 11, 12,
13,21,22,23,24,25,26,31,4
1, 42 ... coding device.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数のコンポーネントから構成される原
画像を、複数のブロックに分割し、複数の符号化装置を
用いて各ブロックのコンポーネント毎に並列処理を行う
画像処理装置において、前記符号化装置の数を前記コン
ポーネントの数の整数倍とし、処理時間に空きのない画
像処理を可能にした画像処理装置。
1. An image processing apparatus for dividing an original image composed of a plurality of components into a plurality of blocks and performing parallel processing for each component of each block by using a plurality of coding apparatuses. An image processing apparatus, wherein the number of components is an integral multiple of the number of components, and image processing with no processing time is available.
JP2771898A 1998-01-26 1998-01-26 Image-processing unit Pending JPH11215380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2771898A JPH11215380A (en) 1998-01-26 1998-01-26 Image-processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2771898A JPH11215380A (en) 1998-01-26 1998-01-26 Image-processing unit

Publications (1)

Publication Number Publication Date
JPH11215380A true JPH11215380A (en) 1999-08-06

Family

ID=12228799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2771898A Pending JPH11215380A (en) 1998-01-26 1998-01-26 Image-processing unit

Country Status (1)

Country Link
JP (1) JPH11215380A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020149178A1 (en) * 2019-01-18 2020-07-23 日立オートモティブシステムズ株式会社 Neural network compression device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020149178A1 (en) * 2019-01-18 2020-07-23 日立オートモティブシステムズ株式会社 Neural network compression device
CN113272831A (en) * 2019-01-18 2021-08-17 日立安斯泰莫株式会社 Neural network simplifying device
JPWO2020149178A1 (en) * 2019-01-18 2021-10-14 日立Astemo株式会社 Neural network contraction device
CN113272831B (en) * 2019-01-18 2024-07-23 日立安斯泰莫株式会社 Shortening device of neural network

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