JPH11214622A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an inductor having a multiple solenoid structure, without increasing the area and volume, using a multilayered wiring technique in a semiconductor device. SOLUTION: Interlayer contacts 7 between a first layer Al wiring 1 and a second upper layer Al wiring 2 on a semiconductor substrate are connected electrically, a prim. solenoid coil 9 is formed as an inductor of a solenoid structure and is made annular on a plane while being electrically connected. Similarly a sec. and tert. solenoid coils 10, 11 are formed, and these solenoid coils 9, 10, 11 are connected electrically by interlayer contacts 8 to form an inductor of a triple solenoid structure, which can be made as a pat of the existing process for avoiding increasing the area and volume so that high inductance can be obtained in a small volume.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device for forming an inductor having a multi-solenoid structure on a semiconductor substrate using a multilayer wiring technique.

[0002]

2. Description of the Related Art In recent years, semiconductor logic circuits have been reduced in area and made into one chip, and the era of a system-on-chip has just arrived. Under these circumstances, a resistor or a capacitor which is a passive element is formed on-chip together with an active element such as a transistor unless its value is large. However, at present, inductors are hardly on-chip. Further, in the conventional on-chip inductor, the inductance value is only about several tens of pH (pico Henry) to several tens of nH (nano Henry), and μH (micro Henry) or mH (milli Henry)
In order to obtain an inductance of the order, the area and the volume become very large, or a material having a high relative permeability must be coated around the inductor wiring.

Hereinafter, a conventional example will be described with reference to the drawings. 5 and 6 show a structure of a conventional on-chip inductor. 5 and 6, reference numeral 20 denotes a signal line (aluminum wiring), reference numeral 21 denotes a wiring interlayer contact, and reference numeral 22 denotes a material having a high relative magnetic permeability (eg, ferrite).

In FIG. 5, the periphery of an aluminum wiring 20 is covered with a high relative magnetic permeability material 22. In FIG. 6, an aluminum wiring 20 is formed in an array in a lower layer, a high relative permeability material (core) 22 is formed thereon via an insulating film (not shown), and an insulating film is further formed thereon. An aluminum wiring 20 is formed so as to sequentially connect both ends of the lower aluminum wiring 20 via a not shown), and the lower aluminum wiring 20 and the upper aluminum wiring 20 are electrically connected by a wiring interlayer contact 21; An inductor having a solenoid structure is formed (see JP-A-6-89976).

In a semiconductor logic circuit, particularly when designing an analog circuit, if the inductor can be made on-chip, the degree of freedom in design as a system chip increases, and the smaller the area and volume occupied by the inductor, the more the degree of freedom in design. Increase.

[0006]

However, in the conventional structure, in order to obtain a large inductance, the wiring length of the aluminum wiring 20 constituting the inductor must be long, and the inductor is formed in the LSI chip. It's extremely difficult, and even if you can do it on-chip,
In order to increase the area and the volume and to increase the inductance value, the high magnetic permeability material 22 had to be used.

The present invention provides a multi-solenoid structure which can be formed on a semiconductor substrate as a part of an existing process while preventing an increase in area and volume by using a multilayer wiring technique in such a semiconductor device. It is an object to form an inductor having the same.

[0008]

In a semiconductor device according to the present invention, a first layer metal wiring and an upper second metal wiring on a semiconductor substrate are electrically connected to an interlayer contact thereof to form a solenoid structure. Is formed as a primary solenoid coil, the primary solenoid coil is annularly arranged on a plane, and further, in each of the upper layers of the second layer, one or more annular solenoid coils having the same structure as the primary solenoid coil are provided. The solenoid coils are electrically connected by interlayer contacts, and an inductor having a multiple solenoid structure is formed on a semiconductor substrate.

According to the present invention, an inductor having a multi-solenoid structure can be formed on a semiconductor substrate as a part of an existing process while preventing an increase in area and volume by using a multilayer wiring technique. Semiconductor device is obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is to electrically connect a first layer metal wiring, an upper second layer metal wiring and an interlayer contact thereof on a semiconductor substrate, An inductor having a solenoid structure is formed as a primary solenoid coil, the primary solenoid coil is annularly arranged on a plane, and an annular single or plural solenoids having the same structure as the primary solenoid coil are provided on each of the upper layers of the second layer. A coil is formed, these solenoid coils are electrically connected to each other by interlayer contacts, and an inductor having a multiple solenoid structure is formed on a semiconductor substrate. By forming an inductor with a multiple solenoid structure at the same time, as part of the existing process while suppressing the increase in area and volume What can Komu Ri, it is possible to a larger inductance obtained in a small volume,
Therefore, it has an effect that the inductor can be formed on a semiconductor substrate on a chip.

According to a second aspect of the present invention, in the first aspect of the present invention, each solenoid coil of the multiple solenoid inductor is spirally arranged on a plane. In addition, there is an effect that a larger inductance can be obtained as compared with the inductance of the structure of the first aspect of the present invention.

A third aspect of the present invention is the invention according to the first or second aspect, wherein at least one of the solenoid coils is a unit cell having a certain unit inductance value. With this unit cell, it is possible to easily use an inductance when designing various analog circuits, and it is possible to easily lay out an inductor having a desired inductance value L on a semiconductor substrate. It has the action of:

The invention according to claim 4 is the invention according to claim 1 or 2, wherein the plurality of solenoid coils are combined to form a unit cell having a certain unit inductance value. With this unit cell, it is possible to easily use an inductance when designing various analog circuits, and it is possible to easily lay out an inductor having a desired inductance value L on a semiconductor substrate. Has an action.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a configuration diagram of an inductor having a triple solenoid structure formed on a semiconductor substrate of an LSI chip according to a first embodiment of the present invention, and FIG. 2 is an enlarged view of a local portion of FIG.

In FIG. 1, reference numerals 1, 2, 3, 4, 5, and 6 denote aluminum wirings constituting an inductor, and reference numerals 7 and 8 denote wiring interlayer contacts. As shown in FIG.
A layer aluminum wiring 1 (an example of a first metal wiring), an upper layer aluminum wiring 2 (an example of a second metal wiring), and an interlayer contact 7 thereof are electrically connected to each other to form a primary as an inductor having a solenoid structure. Forming a solenoid coil 9;
Further, as shown in FIG. 1, the primary solenoid coil 9 is formed in an annular shape on a plane while being electrically connected.

Similarly, an upper third aluminum wiring layer 3
And the aluminum wiring 4 of the fourth layer and the interlayer contact 7 thereof are electrically connected to form a secondary solenoid coil 10. The secondary solenoid coil 10 is formed into a ring shape on a plane. The tertiary solenoid coil 11 is formed by electrically connecting the wiring 5 with the aluminum wiring 6 of the sixth layer and the interlayer contact 7 thereof, and the tertiary solenoid coil 11 is formed into a ring shape on a plane.

Then, the terminal of the aluminum wiring 2 of the second layer of the primary solenoid coil 9 is electrically connected to the starting end of the aluminum wiring 3 of the third layer of the secondary solenoid coil 10 by an interlayer contact 8, and The end of the fourth-layer aluminum wiring 4 of the solenoid coil 10 is electrically connected to the beginning of the fifth-layer aluminum wiring 5 of the tertiary solenoid coil 11 by the interlayer contact 8 to form an inductor having a triple solenoid structure. ing.

Since the triple (multiple) solenoid structure inductor can be manufactured as a part of an existing process while preventing an increase in area and volume, a larger inductance can be obtained in a small volume. It becomes possible. Therefore, since the inductor can be formed on-chip on the semiconductor substrate, an analog ゛ circuit including the inductor can be easily designed. Further, since the inductor can be formed by an existing process, the cost is not increased, and analog circuit design can be easily realized.

If a higher inductance is required, it is of course possible to use a high magnetic permeability material as a substance between the layers. Further, by forming a solenoid coil in an upper layer up to a layer where wiring is possible and electrically connecting the same, a more multiplex structure can be obtained. [Embodiment 2] FIG. 3 is a configuration diagram of a triple solenoid structure inductor formed on a semiconductor substrate of an LSI chip according to Embodiment 2 of the present invention.

The primary solenoid coil 9 of the first embodiment is spirally arranged on a plane while being electrically connected, and its terminal end is connected to the third upper layer via an interlayer contact 8.
The secondary solenoid coil 10 is connected to the aluminum wiring 3 in the same layer as described above, and the secondary solenoid coil 10 is also spirally arranged in this layer while being electrically connected. The layer is connected to the aluminum wiring 5, and the tertiary solenoid coil 11 is also arranged spirally in that layer while being electrically connected in the same manner as described above.

According to this structure, a larger inductance can be obtained as compared with the inductance of the structure of the first embodiment. FIG. 4 is a block diagram of a unit cell of a solenoid coil having a unit inductance value. If the solenoid coil 9 or 10 or 11 having a certain unit inductance value is provided as a unit cell, various analog circuit designs can be realized. In some cases, an inductance can be easily used, and an inductor having a desired inductance value L can be easily laid out on an LSI chip. In addition, a plurality, for example, a primary solenoid coil 9 and a secondary solenoid coil
It is also possible to combine 10 with a unit cell having a certain unit inductance value.

[0022]

As described above, according to the present invention, an inductor having a multi-solenoid structure using metal wiring can be formed in a small volume on a semiconductor substrate by using a multilayer wiring technique.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an inductor having a triple solenoid structure formed on a semiconductor substrate of an LSI chip according to a first embodiment of the present invention.

FIG. 2 is an enlarged view of a local portion of FIG.

FIG. 3 is a configuration diagram of a triple solenoid structure inductor formed on a semiconductor substrate of an LSI chip according to a second embodiment of the present invention;

FIG. 4 is a configuration diagram of a unit cell of a solenoid coil having a certain unit inductance value according to the present invention.

FIG. 5 is a configuration diagram of a conventional on-chip inductor.

FIG. 6 is a configuration diagram of a conventional on-chip inductor.

[Explanation of symbols]

 1,2,3,4,5,6 Aluminum wiring 7,8 Wiring interlayer contact 9 Primary solenoid coil 10 Secondary solenoid coil 11 Tertiary solenoid coil

Claims (4)

[Claims] A first metal wiring on a semiconductor substrate, a second metal wiring on an upper layer, and an interlayer contact thereof are electrically connected to form an inductor having a solenoid structure as a primary solenoid coil; The solenoid coil is arranged in a ring shape on a plane, and further, in each of the upper layers of the second layer,
An annular single or plural solenoid coils having the same structure as the primary solenoid coil are formed, these solenoid coils are electrically connected by interlayer contacts, and an inductor having a multiple solenoid structure is formed on a semiconductor substrate. Semiconductor device. 2. The semiconductor device according to claim 1, wherein each solenoid coil of said multiple solenoid inductor is spirally arranged on a plane. 3. The semiconductor device according to claim 1, wherein at least one of said solenoid coils is a unit cell having a certain unit inductance value. 4. A combination of the plurality of solenoid coils,
3. The semiconductor device according to claim 1, wherein the unit cell has a unit inductance value.