JPH11213692A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain sufficient efficiency with a small count of error corrections, decrease a circuit scale of an error-correcting circuit and reduce a count of memory cells to be used when a memory comprising memory cells storing multi-bit data is error corrected. SOLUTION: A flash memory 10 records in hexadecimal (four bits) with an error-correcting circuit using a 2 error correctable shortened read solomon code incorporated therein. At the write time, an input data Din is converted by an encoder 12 to the shortened read solomon code thereby obtaining a write data WD. The write data WD is converted by a converter 13 to four-bit parallel data and supplied to a cell array 11, where the data is sequentially written to each memory cell constituting the cell array. On the other hand, at the read time, a read data RD from the cell array 11 is converted by a converter 14 to one-byte (eight-bit) parallel data, supplied to a decoder 15 and error corrected in units of bytes, whereby an output data Dout is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory device. More specifically, it is read as an error correction code for a memory comprising memory cells for storing multi-bit data.
The present invention relates to a memory device which obtains sufficient performance with a small number of error corrections by using a Solomon code, reduces the circuit scale of an error correction circuit, and reduces the number of memory cells used.

[0002]

2. Description of the Related Art In recent years, semiconductor memories such as flash memories have been widely used as memory devices. In a flash memory, data is stored using a cell array (typically, about 65 million cells) in which a large number of memory cells each including a floating gate (charge storage layer) and a control gate are formed on a semiconductor substrate. (See FIG. 5).
In this case, data is stored in each cell array according to the amount of charge stored in the floating gate.

FIGS. 6A and 6B show the structure of a memory cell 100 used for a flash memory. That is, the memory cell 100 is formed by stacking the charge storage layer (floating gate) 102 and the control gate 103 on the semiconductor substrate 101. When writing data to the memory cell 100, the amount of charge stored in the floating gate 102 is controlled, and the binary threshold voltage shown in FIG. 7 is changed according to the stored data ("0" or "1"). Choose one. On the other hand, when data is read from the memory cell 100, the reference voltage provided in the middle of the binary threshold voltage is used and the memory cell 1
It is determined whether the data of the memory cell 100 is “0” or “1” depending on whether the threshold voltage of 00 is higher or lower than the reference voltage.

[0004] In semiconductor memories, it is an important issue to prevent a decrease in reliability due to various effects accompanying higher integration and higher density. In particular, in order to prevent a failure caused by aging such as a cell failure due to an increase in the number of write / erase operations, it is necessary to incorporate an error correction circuit using an error correction code such as a Hamming code into the semiconductor memory. Often there.

An error correction code is obtained by adding redundant data called check data to information data, and an error in the code is corrected by using the check data. For example, as shown in FIG. 8, a shortened Hamming code of 512-bit information data is added with 10-bit check data, and corrects an error even if one error occurs in a 522-bit code. It becomes possible.

FIG. 9 shows a configuration of a flash memory 110 in which an error correction circuit using a Hamming code is incorporated. The flash memory 110 includes a cell array 111 having a plurality of memory cells and input data Din.
Is converted to a shortened Hamming code to obtain write data WD for writing to the cell array 111.
And a Hamming code decoder 113 that performs error correction processing on read data RD read from the cell array 111 to obtain output data Dout. In this case, the encoder 112 and the Hamming code decoder 113 constitute an error correction circuit. Then, the encoder 112 adds 10-bit check data to each 512 bits of the input data Din, and generates a shortened Hamming code of 512 bits of information data.

In the flash memory 110 shown in FIG. 9, data writing is performed as follows. That is, the input data Din is input to the encoder 112.
Then, in the encoder 112, the input data Din is converted from the information data into the 512-bit shortened Hamming code to be the write data WD. And the encoder 1
The write data WD output from 12 is supplied to the cell array 111 and written.

On the other hand, data reading is performed as follows. The read data RD read from the cell array 111 is input to the Hamming code decoder 113.
In the Hamming code decoder 113, if there is no error in one code of the read data RD, the information data is output as it is as the output data Dout. When the number of error bits in one code of the read data RD is 1, After the error is corrected, the information data is output as output data Dout.

Next, a shortened BCH code (Bose-Chaudhuri-Hocquenghem cod) capable of correcting two errors is used as an error correction code.
e) when to use. The BCH code and the shortening of the code are discussed in literatures such as “Code Theory” by Hideki Imai (IEICE). For example, if the information data is a 512-bit shortened BCH
As shown in FIG. 10, the code has 20-bit check data added thereto, and even if two errors occur in the 532-bit code, the error can be corrected.

FIG. 11 shows a configuration of a flash memory 120 in which an error correction circuit using a BCH code is incorporated. The flash memory 120 includes a cell array 121 having a plurality of memory cells and input data Din.
Is converted to a shortened BCH code to obtain write data WD for writing to the cell array 121.
B that performs error correction processing on read data RD read from cell array 121 to obtain output data Dout
And a CH code decoder 123. In this case, the encoder 122 and the BCH code decoder 123 constitute an error correction circuit. In the encoder 122, 20-bit check data is added to each 512 bits of the input data Din, and a shortened BCH code in which the information data is 512 bits and which can correct two errors is generated.

In the flash memory 120 shown in FIG. 11, data writing is performed as follows. That is, the input data Din is input to the encoder 122.
Then, in the encoder 122, the input data Din is converted from the information data into the 512-bit shortened BCH code to be the write data WD. And the encoder 12
2 is the write data WD output from the cell array 1
21 to be written.

On the other hand, data reading is performed as follows. The read data RD read from the cell array 121 is input to the BCH code decoder 123. BC
In the H code decoder 123, if there is no error in one code of the read data RD, the information data is directly output data D
When the number of error bits in one code of the read data RD is 1 or 2, the information data is output as output data Dout after the error is corrected.

As shown in FIGS. 9 and 11, by incorporating an error correction circuit inside the flash memories 110 and 120, even if some cell failure occurs due to aging, a read error of written data does not occur. It becomes possible to do so. However, in general, an error correction code needs to have a large number of redundant test data in order to correct many errors, so that the number of memory cells used increases and the circuit size of the error correction circuit increases. Become.

Next, a memory card using a plurality of flash memories (flash memory chips) will be described. As a memory device for storing an amount of data that cannot be handled by a single-chip flash memory, there is a memory card including a plurality of flash memories and a controller.

FIG. 12 shows a configuration of a memory card 130 provided with an error correction circuit using a BCH code in a controller. The memory card 130 includes two flash memories 131 and 132 and a controller 133 for writing and reading data to and from the flash memories 131 and 132.

Then, the controller 133 converts the input data Din into the shortened BCH code and writes the write data WD for writing to the flash memories 131 and 132 with the card interface 134 for exchanging data with the outside of the card. Encoder 135, a BCH encoder / decoder 136 that performs error correction processing on read data RD read from the flash memories 131 and 132 to obtain output data Dout, and a flash memory 13
And a flash interface 137 for controlling writing / reading of data to / from the memory devices 1 and 132.

In this case, the encoder 135 and the BCH code decoder 136 constitute an error correction circuit. Then, in the encoder 135, 20-bit check data is added for every 512 bits of the input data Din, and a shortened BCH code in which the information data is 512 bits and which can correct two errors is generated.

In the memory card 130 shown in FIG. 12, data writing is performed as follows. That is, the input data Din is taken into the card by the card interface 134 and supplied to the encoder 135. Then, in the encoder 135, the input data D
In is converted into the 512-bit shortened BCH code of the information data to be the write data WD. Then, the write data WD output from the encoder 135 is written to the flash memory 131 or 132 under the control of the flash interface 137.

On the other hand, data reading is performed as follows. The read data RD read from the flash memory 131 or 132 under the control of the flash interface 137 is BC
It is input to the H code decoder 136. BCH code decoder 1
In 36, if there is no error in one code of the read data RD, the information data is output as it is as the output data Dout. If the number of error bits in one code of the read data RD is 1 or 2, the error is After the correction, the information data is output as output data Dout. Thus, the output data Dout output from the BCH code decoder 136 is output to the outside of the card via the card interface 234.

As described above, the error correction code can be used in a memory card using a plurality of flash memories. When error correction is performed by a controller, a larger error correction circuit can be provided as compared with the case where the error correction is incorporated in a flash memory, so that there is a feature that more errors can be corrected.

Next, multi-value recording in the flash memory will be described. In recent years, flash memories that store multiple bits in one cell have been proposed for the purpose of increasing the storage capacity of the flash memory. For example, in a memory cell 100 of a flash memory that performs quaternary multi-level recording, FIG.
As shown in A to D, the amount of charge stored in the floating gate 102 is controlled to store data (“11”, “10”,
14 according to “01” or “00”).
To one of the threshold voltages. To read data, a ternary reference voltage provided between each threshold voltage is used. The data of the memory cell 100 is read by comparing the threshold voltage of the memory cell 100 with each reference voltage. Thus, one memory cell 100 has 2
Bit information can be stored.

The same applies to multi-level recording flash memory.
An error correction circuit can be used as in the case of value recording. FIG. 15 shows a configuration of a flash memory 140 for performing 16-level (4-bit) recording in which an error correction circuit using a BCH code is incorporated. This flash memory 140 has a cell array 14 having a plurality of memory cells.
1, an encoder 142 for converting the input data Din into a shortened BCH code to obtain write data WD for writing to the cell array 141, and converting the write data WD output from the encoder 142 into 4 bits from serial data. And a 1-bit / 4-bit converter 143 which converts the data into parallel data and supplies the parallel data to the cell array 141.

The flash memory 140 converts read data RD read from the cell array 111 from 4-bit parallel data to serial data.
The bit / bit converter 144 and the read data RD converted into serial data by the 4-bit / 1 bit converter 144 are subjected to error correction processing to output data Dout.
And a BCH code decoder 145 that obtains In this case, the encoder 142 and the BCH code decoder 145 constitute an error correction circuit. Then, in the encoder 142, 20-bit check data is added for every 512 bits of the input data Din, and a shortened BCH code in which the information data is 512 bits and which can correct two errors is generated.

In the flash memory 140 shown in FIG. 15, data is written as follows. That is, the input data Din is input to the encoder 142.
Then, in the encoder 142, the input data Din is converted from the information data into the 512-bit shortened BCH code to be the write data WD. And the encoder 14
2 is 1 bit / 4
The bit converter 143 converts the serial data into 4-bit parallel data (4-bit data to be stored in a memory cell), supplies the converted data to the cell array 141, and sequentially writes the data into each memory cell constituting the cell array 141.

On the other hand, data reading is performed as follows. The read data RD read from the cell array 141 is converted from 4-bit parallel data into serial data by a 4-bit / 1-bit converter 144, and is converted into a BC.
It is supplied to the H code decoder 145. BCH code decoder 1
In 45, if there is no error in one code of the read data RD, the information data is output as it is as the output data Dout. If the number of error bits in one code of the read data RD is 1 or 2, the error is After the correction, the information data is output as output data Dout.

[0026]

A flash memory that performs multi-level recording, such as the flash memory 140 shown in FIG. 15, has a feature that a plurality of bits are erroneous due to one cell failure. In a conventional flash memory, one bit is stored in one memory cell, and therefore, a code for correcting a bit error has been mainly used as an error correction code. If an error occurs, a code that corrects an error in a bit unit is inefficient.

For example, in a flash memory that stores 4-bit data in one memory cell, if one memory cell becomes inaccessible, a four-correction code must be used to correct the error. It happens to disappear. Here, as described above, when trying to correct a large number of errors with the error correction code, the error correction circuit becomes large, so that there is a problem that the circuit scale increases. Also, in order to correct many errors, it is necessary to add more redundant data, so that a problem arises that many memory cells are required.

Accordingly, an object of the present invention is to provide a memory device which can obtain sufficient performance with a small number of error corrections, reduce the circuit scale of the error correction circuit, and reduce the number of memory cells used. I do.

[0029]

A memory device according to the present invention has a plurality of memory cells, each memory cell storing multi-bit information, and converting input data into a Reed-Solomon code. And a Reed-Solomon code decoder for performing error correction processing on read data read from the cell array to obtain output data.

Further, a memory device according to the present invention has a memory section having a plurality of memory cells, each of which has a cell array for storing multi-bit data, and a memory for writing data to the memory section. A controller for performing reading, wherein the controller converts input data into Reed-Solomon code to obtain write data for writing to the memory unit, and performs error correction processing on read data read from the memory unit. And a Reed-Solomon code decoder that obtains output data by performing

Each memory cell of the cell array stores multi-bit data. At the time of writing, input data is read / written by the encoder as write data.
It is converted to a Solomon code, and this Reed-Solomon code is written to the cell array. The Reed-Solomon code is
This is an error correction code for correcting a plurality of bits into one byte and performing error correction in byte units. At the time of reading, multi-bit data stored in each memory cell of the cell array is read, and the read data is subjected to error correction by a Reed-Solomon code decoder to obtain output data.

As described above, the use of the Reed-Solomon code for performing error correction on a byte-by-byte basis as an error correction code for a memory composed of memory cells for storing multi-bit data allows sufficient performance with a small number of error corrections. Get
The circuit scale of the error correction circuit can be reduced, and the number of memory cells used can be reduced.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a flash memory 10 according to a first embodiment. The flash memory 10 is a flash memory that performs 16-level (4-bit) recording incorporating an error correction circuit using a shortened Reed-Solomon Code capable of correcting two errors. The Reed-Solomon code and the shortened Reed-Solomon code are codes in which a plurality of bits are combined into one byte and error correction is performed in byte units. The contents of the Reed-Solomon code are also discussed in the literature such as "Code Theory" by Hideki Imai (The Institute of Electronics, Information and Communication Engineers) mentioned above.

Now, assume that 8 bits are 1 byte and the number of information data is 128 bytes, and a shortened Reed-Solomon code capable of correcting two errors is taken as an example. In this case, as shown in FIG. 2, the inspection data is 4 bytes, and the total length of the code is 132 bytes = 1,056 bits.

In FIG. 1, the flash memory 10
A cell array 11 having a plurality of memory cells; an encoder 12 for converting input data Din, which is 8-bit parallel data, into a shortened Reed-Solomon code to obtain write data WD for writing to the cell array 11; The write data WD output from the converter 12 is shown in FIG.
As shown in FIG. 7, an 8-bit / 4-bit converter 13 which converts 1-byte (8-bit) parallel data into 4-bit parallel data (4-bit data to be stored in a memory cell) and supplies the same to the cell array 11 have.

The flash memory 10 converts read data RD read from the cell array 11 from 4-bit parallel data to 1-byte (8-bit) parallel data as shown in FIG.
The bit converter 14 and the 4-bit / 8-bit converter 1
And a Reed-Solomon code decoder 15 for subjecting the read data RD converted to 1-byte parallel data to error correction processing to obtain output data Dout. In this case, the encoder 12 and the Reed-Solomon code decoder 15 constitute an error correction circuit. Then, the encoder 12 adds 4 bytes of check data for every 128 bytes of the input data Din, and generates a shortened Reed-Solomon code in which the information data is 128 bytes and which can correct two errors.

In the flash memory 10 shown in FIG. 1, data writing is performed as follows. That is, the input data Din, which is 8-bit parallel data, is input to the encoder 12. Then, this encoder 12
Then, the input data Din is converted into the 128-byte shortened Reed-Solomon code of the information data to be the write data WD. Then, the write data WD output from the encoder 12 is converted from 1-byte (8-bit) parallel data into 4-bit parallel data by the 8-bit / 4-bit converter 13 and supplied to the cell array 11, where 11 is sequentially written into each memory cell.

On the other hand, data reading is performed as follows. The read data RD read from the cell array 11 is converted from 4-bit parallel data into 1-byte (8-bit) parallel data by a 4-bit / 8-bit converter 14 and supplied to a Reed-Solomon code decoder 15. . In the Reed-Solomon code decoder 15, if there is no error in one code of the read data RD, the information data is output as it is as output data Dout in byte units, and the number of error bytes in one code of the read data RD is one. Otherwise, when the error is corrected, the information data is output in byte units as output data Dout after the error is corrected.

The input data Din and the output data Dout
Is not 8-bit parallel data, the encoder 1
2, a bit converter for converting the input data Din into 8-bit parallel data is disposed at a stage preceding the Reed-Solomon code decoder 15, and a 8-bit parallel data is converted into parallel data or serial data corresponding to the output data Dout at a stage subsequent to the Reed-Solomon code decoder 15. A bit converter for converting data into data may be provided.

As described above, in the first embodiment,
A Reed-Solomon code that performs error correction on a byte-by-byte basis is used as an error correction code for a cell array 11 composed of memory cells storing 4-bit data, and sufficient performance can be obtained with a small number of error corrections. Therefore, the circuit scale of the error correction circuit can be reduced, and the number of memory cells used can be reduced.

The effect of the first embodiment will be described with an example. Assuming that 65536 cells of information data are one block, and the cell array is composed of 1024 blocks, writing / reading to / from the memory is performed in block units. Now, it is assumed that the probability that a normal cell at the time of manufacturing becomes a defective cell that is inaccessible after 1 million writing / erasing is 0.001%.
The probability of a block failure occurring after 10,000 write / erase operations is compared.

If a shortened BCH code capable of correcting eight errors is used for 128 bytes, that is, 1024 bits of information data, only 88 bits of test data are required.
Here, since a defect of one cell needs to be corrected for four bits, a defect of up to two cells can be corrected by a code capable of correcting eight errors. Also, 1112 bits can be stored in 278 cells, and 25 in one block.
Since six codes are included, the probability of occurrence of a bad block in this case is approximately 0.000091 according to equation (1).
%.

[0043]

(Equation 1)

Next, the occurrence probability of a bad block when the shortened Reed-Solomon code capable of correcting two errors is used is determined. In this case, a defect of up to 2 bytes can be corrected. Here, by the conversion of 4 bits / 8 bits, 1
When it is noted that a cell error does not affect a plurality of bytes, a byte error rate when 8 bits of information for 2 cells are 1 byte is as shown in Expression (2).
Therefore, the probability of occurrence of a bad block is approximately 0.000077% from equation (3).

[0045]

(Equation 2)

Therefore, a shortened BC capable of 8 error corrections
It can be seen that the H code and the shortened Reed-Solomon code capable of correcting two errors have almost the same error correction capability. However, when the Reed-Solomon code is used as compared with the BCH code, the number of corrections is two, which is much smaller than eight, and the circuit size of the error correction circuit can be reduced. Also, redundant data is 32 bits for 88 bits.
Since the number of bits is significantly smaller, the number of memory cells used can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 4 shows the configuration of a memory card 20 according to the second embodiment. This memory card 20
Is a memory card that uses two flash memories that record 16 values (4 bits) and incorporates an error correction circuit using a shortened Reed-Solomon code capable of correcting two errors in a controller.

In FIG. 4, the memory card 20 includes two flash memories 21 and 22 and a controller 23 for writing and reading data to and from these flash memories 21 and 22.

The controller 23 converts the input data Din, which is 8-bit parallel data, into a shortened Reed-Solomon code by using a card interface 24 for exchanging data with the outside of the card. Write data W for writing to
As shown in FIG. 3, an encoder 25 for obtaining D and write data WD output from the encoder 25 are converted from 1-byte (8-bit) parallel data to 4-bit parallel data (stored in a memory cell). And an 8-bit / 4-bit converter 26 for converting the data into 4-bit data for conversion.

The memory card 20 stores read data RD read from the flash memories 21 and 22.
As shown in FIG. 3, a 4-bit / 8-bit converter 27 converts 4-bit parallel data into 1-byte (8-bit) parallel data, and the 4-bit / 8-bit converter 27 An error correction process is performed on the read data RD converted into the parallel data, and the output data D
out and a flash interface 29 for controlling writing / reading of data to / from the flash memories 21 and 22
And is configured.

In this case, the encoder 25 and the Reed-Solomon code decoder 28 constitute an error correction circuit.
Then, in the encoder 25, 4-byte check data is added for every 128 bytes of the input data Din, and a shortened Reed-Solomon code in which the information data is 128 bytes and which can correct two errors is generated.

In the memory card 20 shown in FIG. 4, data writing is performed as follows. That is, the input data Din is taken into the card by the card interface 24 and supplied to the encoder 25. In this encoder 25, the input data Din is
The data is converted into an 8-byte shortened Reed-Solomon code and is used as write data WD. Then, the write data WD output from the encoder 25 is converted from 1-byte (8-bit) parallel data into 4-bit parallel data by an 8-bit / 4-bit converter 26, and is flashed according to the control of the flash interface 29. The data is written to the memory 21 or the flash memory 22.

On the other hand, data reading is performed as follows. The read data RD read from the flash memory 21 or the flash memory 22 under the control of the flash interface 29 is converted by the 4-bit / 8-bit converter 27 from 4-bit parallel data to 1-byte (8-bit) parallel data. And supplied to the Reed-Solomon decoder 28. Lead
In the Solomon code decoder 28, 1 of the read data RD
If there is no error in the code, the information data is output as it is as the output data Dout in byte units. If the number of error bytes in one code of the read data RD is 1 or 2, the information data is output after the error is corrected. The data is output as output data Dout in byte units. As described above, the output data Dout output from the Reed-Solomon code decoder 28 is output to the outside of the card via the card interface 24.

The input data Din and the output data Dout
Is not 8-bit parallel data, the encoder 2
5, a bit converter for converting the input data Din into 8-bit parallel data is arranged at a stage preceding the Reed-Solomon code decoder 28. At the stage following the Reed-Solomon code decoder 28, the 8-bit parallel data is converted into parallel data or serial data corresponding to the output data Dout. A bit converter for converting data into data may be provided.

As described above, also in the second embodiment,
Flash memories 21 and 22 as memory units having a cell array of memory cells for storing 4-bit data
The Reed-Solomon code that performs error correction in byte units is used as an error correction code for
As in the third embodiment, sufficient performance can be obtained with a small number of error corrections. Therefore, the circuit scale of the error correction circuit can be reduced, and the number of memory cells used can be reduced. The error correction is performed by the controller 23, and the error correction circuit is connected to the flash memories 21 and 22.
It is possible to have a larger error correction circuit as compared with a case where the error correction circuit is built in the device. Therefore, even if many errors occur due to the influence of multi-level recording, it is possible to correct them.

In the above-described embodiment, the data for two cells is one byte. However, the number of cells to be converted into bytes is not limited to two cells. For example, the data for one cell is one byte, or three bytes. Various modifications are conceivable, such as making the data for a cell one byte. Further, in the above-described embodiment, a flash memory is taken as an example of a storage system. However, the present invention is not limited to a flash memory but can be applied to various storage systems such as other semiconductor memories.

[0057]

According to the present invention, a Reed-Solomon code for performing error correction on a byte-by-byte basis is used as an error correction code for a memory composed of memory cells storing multi-bit data. In this case, sufficient performance can be obtained, the circuit scale of the error correction circuit can be reduced, and the number of memory cells used can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a flash memory according to a first embodiment.

FIG. 2 is a diagram illustrating an example of a shortened Reed-Solomon code.

FIG. 3 is a diagram for explaining an operation of bit conversion.

FIG. 4 is a block diagram illustrating a configuration of a memory card according to a second embodiment.

FIG. 5 is a diagram showing a structure of a cell array.

FIG. 6 is a diagram showing a structure of a memory cell.

FIG. 7 is a diagram showing a voltage distribution of a memory cell.

FIG. 8 is a diagram illustrating an example of a shortened Hamming code.

FIG. 9 is a block diagram showing a configuration of a flash memory incorporating an error correction circuit using a shortened Hamming code.

FIG. 10 is a diagram illustrating an example of a shortened BCH code.

FIG. 11 is a block diagram showing a configuration of a flash memory incorporating an error correction circuit using a BCH code.

FIG. 12 is a block diagram illustrating a configuration of a memory card including an error correction circuit using a shortened BCH code in a controller.

FIG. 13 is a diagram showing electric charges applied to a memory cell when performing multi-level recording.

FIG. 14 is a diagram showing a voltage distribution of a memory cell for performing multi-level recording.

FIG. 15 is a block diagram showing a configuration of a multi-level recording flash memory incorporating an error correction circuit using a shortened BCH code.

[Explanation of symbols]

10: flash memory, 11: cell array,
12 ... encoder, 13 ... 8 bit / 4 bit converter, 14 ... 4 bit / 8 bit converter, 15 ...
・ Reed-Solomon code decoder, 20 ・ ・ ・ Memory card, 21,22 ・ ・ ・ Flash memory, 23 ・ ・ ・ Controller, 24 ・ ・ ・ Card interface, 25 ・
..Encoder, 26... 8 bit / 4 bit converter,
27: 4-bit / 8-bit converter, 28: Reed-Solomon code decoder, 29: Flash interface

Claims (6)

[Claims] 1. A cell array having a plurality of memory cells, each memory cell storing multi-bit data, and a code for converting input data into a Reed-Solomon code to obtain write data for writing to the cell array. And a Reed-Solomon code decoder for performing error correction processing on read data read from the cell array to obtain output data. 2. The input data and the output data are parallel data or serial data of a predetermined bit, and a first bit converter for converting the input data into 1-byte parallel data at a stage before the encoder. And a second bit converter for converting the one-byte parallel data output from the decoder into the parallel data or the serial data of the predetermined bit is provided at a subsequent stage of the Reed-Solomon code decoder. Claim 1
A memory device according to claim 1. 3. The memory cell of the cell array,
Each of them stores m-bit data (m is an integer of 2 or more). Between the encoder and the cell array, 1-byte parallel data output from the encoder is m-bit data. A third bit converter for converting the data into parallel data; and a third bit converter for converting m-bit parallel data output from the cell array into 1-byte parallel data between the cell array and the Reed-Solomon code decoder. The memory device according to claim 1, further comprising four bit converters. 4. The memory device according to claim 1, wherein the Reed-Solomon code has a plurality of bits that can be stored in one or a plurality of memory cells of the cell array as one byte. 5. A memory section having a plurality of memory cells, each memory cell having a cell array storing multi-bit data, and a controller for writing and reading data to and from the memory section. An encoder for converting input data into a Reed-Solomon code to obtain write data for writing to the memory unit; and performing an error correction process on read data read from the memory unit to output data. And a Reed-Solomon code decoder for obtaining: 6. The memory unit according to claim 5, wherein the memory unit comprises one or a plurality of flash memories.
A memory device according to claim 1.