JPH11213654A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dynamic random-access memory(DRAM) in which a bit configuration decided by a wire molding operation can be changed even after a resin molding operation. SOLUTION: In a memory device, a pad 24 which is connected to a power- supply pin 21 or a ground pin 22 is installed, a signal changeover circuit 40 which receives signals from the pad 24 and an NC(nonconnection) pin 23, which outputs the signal from the pad 24 as it is when the NC pin 23 is at a level L and which outputs the inverted signal of the signal from the pad 24 when the NC pin 23 is at a level H is installed, and a bit-configuration changeover circuit 13 which changes over the bit configuration of a memory circuit 12 according to an output signal from the signal changeover circuit 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a DR capable of switching a bit configuration.
It relates to an AM (dynamic random access memory).

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory device called a DRAM has a small number of product types, and is manufactured for each bit configuration (.times.1, .times.4, etc.) from an initial diffusion step in order to make an optimum design. Was. However, as the number of DRAM products has increased, it has become necessary to reduce the number of design evaluation steps.
The bit configuration is determined in a later process with the same basic design, such as selecting the bit configuration by switching the wire bonding in the assembly process.

[0003]

However, in the above-described method of selecting the bit configuration by switching the wire bonding at the time of the assembly process, the bit configuration is determined at the time of the assembly process. There was a problem that the bit configuration could not be changed. Since the bit configuration of a DRAM as a product is determined based on a production plan determined from market trends, if there is an inventory when a large change in demand occurs, the bit configuration is already determined and cannot be changed Therefore, it cannot be dealt with. Therefore, the period from the step of determining the bit configuration to the shipment of the product is restricted. To solve such a problem, Japanese Patent Application Laid-Open No. 5-182465 has been proposed.
In Japanese Patent Application Laid-Open Publication No. H11-157, there is disclosed means for switching a bit configuration by inputting a signal to an NC (no connection) pin. In this method, the bit configuration is determined by the level of a signal applied to the NC pin for a DRAM whose bit configuration has not been determined after the assembly process, and the bit configuration has already been determined by wire bonding during the assembly process. Does not change the bit configuration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a main object of the present invention is to provide a DRAM capable of changing a bit configuration after an assembly process in which a bit configuration has already been determined. It is.

[0005]

According to one aspect of the present invention, a semiconductor memory device includes a memory circuit, a pad,
Signal switching means and bit configuration switching means are provided. The bit configuration of the memory circuit can be switched. The pad is
Connected to power or ground pins. The signal switching means receives a signal from the pad and the non-connection pin, and outputs the signal from the pad as it is when the signal from the non-connection pin is in the first state, and outputs the signal from the non-connection pin in the second state. In this case, an inverted signal of the signal from the pad is output. The bit configuration switching means switches the bit configuration of the memory circuit according to the output signal from the signal switching means.

[0006] Preferably, the first state is a logic low level or an open state, and the second state is a logic high level.

In the semiconductor memory device, when a logic high level voltage is applied to the non-connection pin, an inverted signal from the pad is output from the signal switching means. Therefore,
The bit configuration can be switched by applying a logic high level voltage to the pad. According to another aspect of the present invention, a semiconductor memory device includes a memory circuit, first and second non-connection pins, connection detection means, and bit configuration switching means. The bit configuration of the memory circuit can be switched. The connection detecting means is connected to the first and second non-connection pins, outputs a signal in the first state when the first and second non-connection pins are connected, and outputs the first non-connection signal. When the connection pin and the second non-connection pin are in the non-connection state, a signal in the second state is output. The bit configuration switching means switches the bit configuration of the memory circuit according to an output signal from the connection detection means.

In the above-described semiconductor memory device, when the first non-connection pin and the second non-connection pin are connected, a signal in the first state is output from the connection detection circuit, and the first non-connection pin and the second non-connection pin are connected to each other. Is in the non-connection state, the signal in the second state is output from the connection detection circuit. Therefore, the bit configuration can be switched by changing the connection state between the first non-connection pin and the second non-connection pin.

According to still another aspect of the present invention, a semiconductor memory device includes a memory circuit, a voltage detecting means, and a bit configuration switching means. The bit configuration of the memory circuit can be switched. The voltage detection means outputs a signal in a first state when the power supply voltage is equal to or lower than a predetermined threshold, and outputs a second signal when the power supply voltage is higher than the threshold.
The signal of the state of is output. The bit configuration switching means switches the bit configuration of the memory circuit according to the output signal from the voltage detection means.

In the semiconductor memory device, when the power supply voltage is equal to or lower than a predetermined threshold, a signal in the first state is output from the voltage detecting means. When the power supply voltage is higher than the predetermined threshold, the voltage is detected. The signal in the second state is output from the detection means. Therefore, the bit configuration can be switched according to the magnitude of the power supply voltage.

According to still another aspect of the present invention, a semiconductor memory device includes a memory circuit, a high voltage detecting unit, and a bit configuration switching unit. The bit configuration of the memory circuit can be switched. The high voltage detecting means is connected to the address pin, and outputs a signal in a first state when a voltage higher than a power supply voltage is input to the address pin, and outputs a signal in a second state otherwise. I do. The bit configuration switching means switches the bit configuration of the memory circuit according to the output signal from the high voltage detection means.

Preferably, the address pins are used in a first bit configuration but not used in a second bit configuration.

In the semiconductor memory device, when a voltage higher than the power supply voltage is input to the address pin, a signal in the first state is output from the high voltage detecting means, and a voltage lower than the power supply voltage is input to the address pin. Then, a signal in the second state is output from the high voltage detecting means. Therefore,
The bit configuration can be switched by inputting a voltage higher than the power supply voltage to the address pins.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a block diagram showing an entire configuration of a DRAM according to a first embodiment of the present invention. Referring to FIG. 1, this DRAM includes address pins 1, 2, to 9, 10, an address buffer 11, a memory circuit 12, a bit configuration switching circuit 13, an input / output pin 14, and a power supply pin 21. , Ground pin 22, NC (no connection; non-connection) pin 23, pads 24, 25
, A control circuit 30 and a signal switching circuit 40.

The address buffer 11 includes an address pin 1
The external address signals A0 to A10 are converted into row address signals or column address signals. Memory circuit 1
2 includes memory blocks B1 to B8. Bit configuration switching circuit 13 switches the bit configuration of memory circuit 12 to a 4-bit configuration or an 8-bit configuration in accordance with the level of bit configuration switching signal BHE. Either the power supply pin 21 or the ground pin 22 is connected to the pad 24 according to the bit configuration. The pad 24 is connected to the signal switching circuit 40. NC pin 23 is connected to pad 25. The pad 25 is connected to the control circuit 30.

The control circuit 30 includes a delay circuit 31 and an AND circuit.
It includes a circuit 32, an NMOS transistor 33, and a latch circuit 34, and outputs the potential of the NC pin input through the pad 25 to the signal switching circuit 40. AND circuit 32
Outputs an AND signal P of the power-on reset signal / POR and the signal φ after the power-on reset signal / POR has passed through the delay circuit 31. NMOS transistor 33
Has a source grounded, a drain connected to the pad 25 and the latch circuit 34, and the signal P as a gate input. Latch circuit 34 includes inverters 35, 36, and 37, latches an input signal from pad 25, and outputs the signal to signal switching circuit 40.

The signal switching circuit 40 includes a NAND gate 4
1, 44, inverters 43, 45, and NOR gate 4
2 in response to a signal from the control circuit 30.
4 is output as the bit configuration switching signal BHE as it is or after inverting the external bit configuration switching signal EXTBHE.

Next, the operation of the DRAM configured as described above will be described. The power supply pin 21 or the ground pin 22 and the pad 24 are connected by wire bonding according to the bit configuration (× 4, × 8) determined in the assembly process. That is, in the case of the 8-bit configuration, the power supply pin 21
In the case of a 4-bit configuration, the ground pin 22 and the pad 24 are connected by wire bonding. Therefore, an external bit configuration switching signal EXTBHE having an H (logic high) level in an 8-bit configuration and an L (logic low) level in a 4-bit configuration is input from pad 24 to signal switching circuit 40. FIG. 2 is a timing chart showing the power supply voltage Vcc and the power-on reset signal / POR when the power is turned on. FIG. 3 shows / POR, φ,
6 is a timing chart showing the relationship of P. Referring to FIGS. 2 and 3, when the power of the circuit is turned on, power-on reset signal / POR rises with a delay of a predetermined time Δt. The signal φ after the power-on reset signal / POR has passed through the delay circuit 31 composed of the odd-numbered stages of inverters is a signal that falls later than the rise of the power-on reset signal / POR. Therefore, signal P output from AND gate 32 receiving power-on reset signal / POR and signal φ after passing through delay circuit 31 at the rising edge of / POR and a pulse signal falling at the falling edge of φ Becomes This pulse signal P is N
Since the voltage is inputted to the gate of the MOS transistor 33, the NMOS transistor 3 is momentarily after a predetermined time Δt after the power is turned on.
3 turns on, and the L level is held in the latch circuit 34. When the signal output from latch circuit 34 and input to signal switching circuit 40 is at L level, signal switching circuit 40 uses the level of external bit configuration switching signal EXTBHE input from pad 24 as it is as bit configuration switching signal BHE. Output. Therefore, the level of bit configuration switching signal BHE becomes H level in an 8-bit configuration and L level in a 4-bit configuration.

Next, the operation of the bit configuration switching circuit 13 will be described. When the bit configuration switching signal BHE from the signal switching circuit 40 is at the H level, the memory blocks B1 to B8 in the memory circuit 12 are caused to function as an 8-bit configuration. Addresses corresponding to row addresses or column addresses from address buffer 11 are stored in memory blocks B1 to B8.
Is specified for each of Memory blocks B1 to B8
1-bit data from each of the input / output pins DQ0-D
Input / output through Q7. Therefore, 8-bit data is input / output for one address from the address buffer 11.

When the bit configuration switching signal BHE from the signal switching circuit 40 is at L level, the memory blocks B1 to B8 in the memory circuit 12 are made to function as a 4-bit configuration. An address corresponding to a row address or a column address from the address buffer 11 is a first block including memory blocks B1 and B2, a second block including memory blocks B3 and B4, a third block including memory blocks B5 and B6, and a memory block. It is specified for each of the fourth blocks consisting of B7 and B8.
One-bit data is input / output from each of the first to fourth blocks through each of the input / output pins DQ0 to DQ3. Therefore, 4-bit data is input / output for one address from the address buffer 11.

As described above, the DRAM according to the first embodiment functions as an 8-bit structure when power supply pin 21 and pad 24 are connected by wire bonding during the assembly process, and ground pin 22 and pad 24
When they are connected by wire bonding, they function as a 4-bit configuration.

Here, a case where an H level signal is applied to the NC pin 23 will be considered. When an H level signal is applied to the NC pin 23, the H level is held in the latch circuit 34 in the control circuit 30 through the pad 25, and the H level signal is input from the latch circuit 34 to the signal switching circuit 40. When an H level signal is input from latch circuit 34, that is, control circuit 30, signal switching circuit 40 outputs an inverted signal of external bit configuration switching signal EXTBHE input from pad 24 as bit configuration switching signal BHE. As a result, when power supply pin 21 and pad 24 are connected by wire bonding, bit configuration switching signal BHE is at L level, so that the DRAM functions as a 4-bit configuration, and ground pin 22 and pad 24 are connected. Wire
When connected by bonding, the bit configuration switching signal BHE goes to H level, so that the DRAM functions as an 8-bit configuration.

As described above, according to the first embodiment,
Since the control circuit 30 for inverting and outputting the external bit configuration switching signal EXTBHE when the H level signal is supplied to the NC pin 23 is provided in the signal switching circuit 40, the bit configuration determined by wire bonding during the assembly process is provided. Can be changed even after the resin molding.

[Second Embodiment] FIG. 4 is a block diagram showing a main part of a DRAM according to a second embodiment of the present invention. Referring to FIG. 4, this DRAM includes NC pins 51 and 52 and a connection detection circuit 60 instead of NC pin 23, pad 25 and control circuit 30 shown in FIG. NC pins 51 and 52 are connected to each other in advance, and the other is connected to connection detection circuit 60, respectively. The connection detection circuit 60 includes a one-shot circuit 70
, A transfer gate circuit 80, a latch circuit 90,
120, a delay circuit 100, an inverter 101, and a clocked NAND circuit 110. One-shot circuit 70 includes a delay circuit 71 composed of an odd number of stages of inverters and an AND gate 72, and has the same configuration as the circuit composed of delay circuit 31 and AND gate 32 shown in FIG. And perform the same operation. That is, one-shot circuit 70 supplies power-on reset signal / POR
At the same time, a rising pulse signal P is generated. The transfer gate circuit 80 includes a PMOS transistor 81 and N
It includes MOS transistors 82 and 84 and an inverter 83, and opens and closes between the NC pin 51 and the latch circuit 90 according to the pulse signal P. Latch circuit 90 includes inverters 91, 92, and 93, and outputs an input signal φ1 to clocked NAND circuit 110 while holding an output signal from transfer gate circuit 80. The delay circuit 100
The pulse signal P from the one-shot circuit 70 is received at the input, and a pulse signal P 'obtained by delaying the pulse signal P is output. The pulse signal P 'rises after the pulse signal P falls. Inverter 101 inverts the signal from NC pin 52 and outputs the inverted signal. This NC pin 5
Since inverter 2 is grounded, inverter 101 always outputs input signal φ2 at H level. The clocked NAND circuit 110 includes an inverter 111, PMOS transistors 112, 113, 114, and an NMOS transistor 1
15, 116 and 117, and the signal P 'from the delay circuit 100 is used as a control signal to control the input signal φ1 and the input signal φ2.
Is output. Latch circuit 120 includes inverters 121 and 122, inverts and holds an output signal from clocked NAND circuit 110, and outputs the inverted signal to signal switching circuit 40 shown in FIG.

Next, the operation of the DRAM configured as described above will be described. FIG. 5 is a timing chart of the control signal P of the transfer gate circuit 80, the control signal P 'of the clocked NAND circuit 110, the input signals φ1 and φ2 of the clocked NAND circuit 110, and the bit configuration switching signal BHE. The NC pins 51 and 52 are connected in advance. The NC pin 52 is connected to the input of the inverter 101 of the connection detection circuit 60, and the node between the inverters 101 of the NC pin 52 is grounded. Therefore, input signal φ2 is always at H level. NC pin 51 is also connected to transfer gate circuit 80. When the control signal P is at the L level, the transfer gate circuit 80 turns on the NC pin 51 and the latch circuit 9 because the PMOS transistor 81 and the NMOS transistor 82 are turned on.
0 is connected. Since the NC pin 51 is at the L level, the L level is held in the latch circuit 90 and the input signal φ
1 is at the L level. When the control signal P is at the H level,
Since the PMOS transistor 81 and the NMOS transistor 82 are turned off, the NC pin 51 and the latch circuit 90 are turned off. At this time, since the NMOS transistor 84 is turned on, the output signal from the transfer gate circuit 80 becomes H level and is held by the latch circuit 90, so that the input signal φ1 becomes H level. After the power is turned on, the one-shot circuit 70 generates a pulse signal. This pulse signal is input as the control signal P to the transfer gate circuit 80. While the control signal P is at the H level, the input signal φ1 to the clocked NAND circuit 110 is
Are kept at the H level. At the same time that control signal P falls to L level, input signal φ1 to clocked NAND circuit 110 falls to L level. The pulse signal generated from the one-shot circuit 70 is also input to the delay circuit 100. The delay circuit 100 outputs a pulse signal rising after the falling of the input pulse signal to the clocked NAN.
It is input to the D circuit 110 as a control signal P '. When control signal P 'rises to the H level, the clocked NAND circuit outputs NAND signals of input signals φ1 and φ2. In this case, since φ1 is at H level and φ2 is at L level, an H level signal is output, and an L level signal C inverted by the latch circuit 120 is output to the signal switching circuit 40 shown in FIG. At this time, the signal switching circuit 40 outputs the level of the external bit configuration switching signal EXTBHE input from the pad 24 as it is as the bit configuration switching signal BHE as described in the first embodiment. Therefore, the level of bit configuration switching signal BHE becomes H level in an 8-bit configuration and L level in a 4-bit configuration. Therefore, in the DRAM, the power supply pin 21 and the pad 24 are wire-connected.
It functions as an 8-bit configuration when connected by bonding, and functions as a 4-bit configuration when the ground pin 22 and the pad 24 are connected by wire bonding.

Next, the operation when the NC pins 51 and 52 are disconnected will be described. In this case, after the control signal P of the transfer gate circuit 80 falls, the NC pin 5 remains connected after the NC pin 51 and the latch circuit 90 are connected again.
1 remains at the H level, the clocked N
Input signal φ1 to AND circuit 110 is kept at H level. On the other hand, the input signal φ2 to the clocked NAND circuit 110 keeps the H level as in the case where the NC pins 51 and 52 are connected. Therefore, an L level signal is output from clocked NAND circuit 110 after control signal P 'rises, and H level signal C inverted by latch circuit 120 is sent to signal switching circuit 40 shown in FIG. Is output. At this time, similarly to the first embodiment, signal switching circuit 40 outputs an inverted signal of external bit configuration switching signal EXTBHE input from pad 24 as bit configuration switching signal BHE. As a result, when power supply pin 21 and pad 24 are connected by wire bonding, bit configuration switching signal BHE is at L level, so that the DRAM functions as a 4-bit configuration, and ground pin 22 and pad 24 are connected. When the connection is made by wire bonding, the bit configuration switching signal BHE becomes H level, so that the DRAM functions as an 8-bit configuration.

As described above, according to the second embodiment,
Since the connection detection circuit 60 that generates an H level or L level signal according to the connection state of the NC pins 51 and 52 is provided, the bit configuration can be switched by disconnecting the NC pins 51 and 52 that are connected in advance.

[Third Embodiment] FIG. 6 is a block diagram showing a main part of a DRAM according to a third embodiment of the present invention. Referring to FIG. 6, this DRAM includes a voltage detection circuit 130 instead of NC pin 23, pad 24 and control circuit 30 shown in FIG.

The voltage detection circuit 130 includes the step-down power supply circuit 13
1, a PMOS transistor 132, and an NMOS transistor 133, and outputs an L-level signal C when the input power supply voltage is equal to or lower than a predetermined threshold value. If it is larger than the threshold value, an H-level signal C is output. Step-down power supply circuit 131 outputs a voltage of the threshold level when the input power supply voltage is higher than a predetermined threshold, and outputs the same voltage as the input power supply voltage when the input power supply voltage is lower than the predetermined threshold. Output voltage. The PMOS transistor 132 and the NMOS transistor 133 are connected in series to form an inverter,
The output signal from the step-down power supply circuit 131 is inverted and the signal C is inverted.
Generate The source of the PMOS transistor 132 is connected to the power supply node.

Next, the operation of the DRAM configured as described above will be described. FIG. 7 is a diagram showing input-output characteristics of the step-down power supply circuit 131. The threshold value of step-down power supply circuit 131 in the third embodiment is 3.3V. Therefore, the case where the power supply voltage Vcc is equal to or lower than the threshold value will be described as an example, and the case where the power supply voltage Vcc is higher than the threshold value will be described as Vcc = 5V.

(A) When Vcc = 3.3 V Referring to FIG. 7, the voltage output from step-down power supply circuit 131 is 3.3 V. At this time, if the threshold value of the inverter composed of the PMOS transistor 132 and the NMOS transistor 133 is set to, for example, 3.2 V, the L level signal C is output from the inverter as shown in FIG. This signal C is output to the signal switching circuit 4
Input to 0. In this case, as shown in the first embodiment, signal switching circuit 40 directly outputs the level of external bit configuration switching signal EXTBHE input from pad 24 as bit configuration switching signal BHE. Therefore, the level of bit configuration switching signal BHE becomes H level in an 8-bit configuration and L level in a 4-bit configuration.
As a result, the DRAM functions as an 8-bit configuration when the power supply pin 21 and the pad 24 are connected by wire bonding, and has a 4-bit configuration when the ground pin 22 and the pad 24 are connected by wire bonding. Function.

(B) When Vcc = 5V Referring to FIG. 7, the voltage output from step-down power supply circuit 131 is 3.3V. In general, the threshold value of the inverter is represented by a function of the power supply voltage Vcc. When the threshold voltage of Vcc = 3.3 V, the inverter having the threshold value of 3.2 V has Vcc = 5.
At V, it has a threshold value greater than 3.3V and less than 5V. Accordingly, as shown in FIG. 8B, the H level signal C is output from the inverter.
And this signal is input to the signal switching circuit 40. Therefore, in this case, as shown in the first embodiment, signal switching circuit 40 outputs an inverted signal of external bit configuration switching signal EXTBHE input from pad 24 as bit configuration switching signal BHE. As a result, when power supply pin 21 and pad 24 are connected by wire bonding, bit configuration switching signal BHE is at L level, so that the DRAM functions as a 4-bit configuration, and ground pin 22 and pad 24 are connected. Bit connection switching signal BH when connected by wire bonding
Since E becomes H level, the DRAM functions as an 8-bit configuration.

As described above, according to the third embodiment,
Since the voltage detection circuit 130 that outputs H-level and L-level signals according to the magnitude of the power supply voltage Vcc is provided,
The bit configuration can be changed according to the magnitude of power supply voltage Vcc.

[Embodiment 4] FIG. 10A is a timing chart showing the fetching of an address at the time of reading / writing of a conventional DRAM functioning in a 4-bit configuration by a bonding option, and FIG. ,
9 is a timing chart showing address fetching at the time of reading / writing of a conventional DRAM functioning in an 8-bit configuration by a bonding option. FIG.
As shown in (a), when the 4-bit configuration is set by the bonding option, when row address strobe signal / RAS falls, address pin 1 is pulled down.
10 are taken into the address buffer 11, and the row address signals X0
~ X9. When the bonding option is set to an 8-bit configuration, when column address strobe signal / CAS falls, address signals A0 to A1 applied to address pins 1 to 10 are applied.
0 is taken into the address buffer 11 and output as column address signals Y0 to Y9. A comparison between the 4-bit configuration and the 8-bit configuration shows that Y8
It can be seen that the address is not used.

Focusing on this point, a fourth embodiment described below switches a DRAM set to a 4-bit configuration by a bonding option to an 8-bit configuration.

FIG. 9 is a block diagram of a fourth embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a main part of a RAM. Referring to FIG. 9, this DRAM is provided with NC pin 2 shown in FIG.
3, a super VIH detection circuit is provided instead of the pad 25 and the control circuit 30. The super VIH detection circuit 141 is connected to the address pin 10, and when a voltage higher than the power supply voltage is input to the address pin 10,
A level signal is output, and when a power supply voltage or a voltage lower than the power supply voltage is input, an L level signal is output.

Next, the operation of the DRAM configured as described above will be described. First, consider a DRAM that is wire-bonded to function as a 4-bit configuration. As shown in FIG. 11, a voltage higher than the power supply voltage (super VIH level), for example, 7
When a voltage of V is applied, the voltage of 7 V
The signal is input to the H detection circuit 141, and the super VIH detection circuit 141 outputs an H-level signal C. This H-level signal C is input to the signal switching circuit 40 shown in FIG. Therefore, in this case, as shown in the first embodiment, signal switching circuit 40 outputs an inverted signal of external bit configuration switching signal EXTBHE input from pad 24 as bit configuration switching signal BHE. As a result, since the ground pin 22 and the pad 24 are connected by wire bonding, the bit configuration switching signal BHE becomes H level, and the DRAM functions as an 8-bit configuration. That is, the bit configuration is changed from the 4-bit configuration to the 8-bit configuration.

As described above, according to the fourth embodiment,
Super VIH which is connected to address pin 10 and outputs an H level signal when a voltage higher than the power supply voltage is applied to address pin 10 and outputs an L level signal when a voltage lower than the power supply voltage is applied. Since the detection circuit 141 is provided, a DRAM functioning as a 4-bit configuration
By applying a voltage higher than the power supply voltage to the address pin 10 when the Y address (column address) is fetched, the bit configuration can be changed from a 4-bit configuration to an 8-bit configuration.

Here, the case of switching between the 4-bit configuration and the 8-bit configuration has been described. However, if there is an unused address such as the Y10 address shown in the fourth embodiment at the time of switching the bit configuration, other switching is performed. It can also be used when switching the bit configuration.

[0041]

In the semiconductor memory device according to the present invention, when the signal from the non-connection pin is in the first state, the signal from the pad is output as it is, and the signal from the non-connection pin is in the second state. In some cases, since a signal switching means for outputting an inverted signal of a signal from a pad is provided, a bit configuration can be switched by changing a state of a signal applied to a non-connection pin.

When the first and second non-connection pins are connected to the first and second non-connection pins, the first non-connection pin outputs a signal in the first state when the second non-connection pin is connected to the first non-connection pin. When the non-connection pin and the second non-connection pin are in the non-connection state, a connection detection unit that outputs a signal in the second state is provided, so that the first non-connection pin and the second non-connection pin are connected or disconnected. The bit configuration can be switched by setting the state.

A voltage detection circuit outputs a signal in a first state when the power supply voltage is lower than a predetermined threshold value, and outputs a signal in a second state when the power supply voltage is higher than the threshold value. Because of the means, the bit configuration can be switched according to the magnitude of the power supply voltage.

Further, when a voltage higher than the power supply voltage is input to the address pin connected to the address pin, the first
, And a high voltage detection circuit that outputs the signal in the second state at other times, so that the bit configuration can be switched by inputting a voltage higher than the power supply voltage to the address pin. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a power-on reset signal and a power supply voltage signal shown in FIG.

FIG. 3 is a timing chart for explaining operations of the delay circuit and the AND circuit shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a main part of a DRAM according to a second embodiment of the present invention;

FIG. 5 is a timing chart for explaining an operation of the connection detection circuit shown in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a main part of a DRAM according to a third embodiment of the present invention.

FIG. 7 is a diagram showing input / output characteristics of the step-down power supply circuit shown in FIG. 6;

8A is a diagram for explaining the operation of the inverter shown in FIG. 7 when Vcc = 5V, and FIG.
FIG. 8 is a diagram for explaining an operation of the inverter shown in FIG. 7 when Vcc = 3.3 V.

FIG. 9 is a block diagram showing a configuration of a main part of a DRAM according to a fourth embodiment of the present invention.

10A is a timing chart showing address fetching at the time of reading / writing of a conventional DRAM functioning with a 4-bit configuration, and FIG. 10B is a timing chart showing the reading / writing of a DRAM functioning with a conventional 8-bit configuration. 9 is a timing chart showing the address fetching at the time.

FIG. 11 is a timing chart showing fetching of an address at the time of reading / writing of a DRAM according to a fourth embodiment of the present invention;

[Explanation of symbols]

12 memory circuit, 13 bit configuration switching circuit, 21
Power pin, 22 ground pin, 23, 51, 52 NC
(No connection) pin, 24 pads, 40 signal switching circuit, 60 connection detection circuit, 130 voltage detection circuit,
141 Super VIH detection circuit, EXTBHE external bit configuration switching signal, BHE bit configuration switching signal.

Claims (6)

[Claims] 1. A switchable memory circuit having a bit configuration, a pad connected to a power supply pin or a ground pin, a signal from the pad and a non-connection pin, and a signal from the non-connection pin being a first signal. A signal switching unit that outputs a signal from the pad as it is in the state, and outputs an inverted signal of a signal from the pad when the signal from the unconnected pin is in the second state; And a bit configuration switching means for switching a bit configuration of the memory circuit according to the output signal of the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein said first state is a logic low level or an open state, and said second state is a logic high level. 3. A switchable memory circuit having a bit configuration, first and second non-connecting pins, and the first and second non-connecting pins connected to the first and second non-connecting pins.
Outputs a signal in a first state when the non-connection pin and the second non-connection pin are in a connected state, and outputs a second signal when the first non-connection pin and the second non-connection pin are in a non-connection state. A semiconductor memory device, comprising: connection detection means for outputting a signal in the state; and bit configuration switching means for switching a bit configuration of the memory circuit in accordance with an output signal from the connection detection means. 4. A memory circuit having a switchable bit configuration, and a signal in a first state is output when a power supply voltage is equal to or lower than a predetermined threshold, and a signal is output when the power supply voltage is higher than the threshold. 2. A semiconductor memory device comprising: voltage detection means for outputting a signal in the state 2; and bit configuration switching means for switching a bit configuration of the memory circuit according to an output signal from the voltage detection means. 5. A memory circuit having a switchable bit configuration, connected to an address pin, and outputs a signal in a first state when a voltage higher than a power supply voltage is input to the address pin. A semiconductor memory device comprising: a high-voltage detection unit that outputs a signal in a second state when the signal is high; and a bit configuration switching unit that switches a bit configuration of the memory circuit according to an output signal from the high-voltage detection unit. 6. The semiconductor memory device according to claim 5, wherein said address pin is an address pin used in a first bit configuration but not used in a second bit configuration.