JPH11212816A - Test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive test system which can reduce a memory with a very large capacity. SOLUTION: This system is provided with a clock signal generation part 1 which inputs a clock signal to DUT2 and a constant voltage source 3 which applies a specific voltage to the DUT2. Further, a 1-counting counter 4 is connected to the output terminal of the DUT2. The 1-counting counter 4 counts how many times a signal '1' is sent within an arbitrary specific time from pulse waves outputted from the DUT2. A comparing circuit 6 is connected to the 1-counting counter 6 and a memory part 5 for a 1-counting expected value is connected to the comparing circuit 6. A memory part 5 for the 1- counting expected value is stored with an expected value of the frequency of output of the signal '1' within the specific time when the DUT2 is a conforming article. Further, the comparing circuit 6 compares the generation frequency of the signal '1' counted by the 1-counting counter 4 with the expected value stored in the memory part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test system suitable for a function test of a one-chip microcomputer.
In particular, the present invention relates to a test system that can perform a function test without using a memory that requires a huge capacity.

[0002]

2. Description of the Related Art Conventionally, the following conventional LSI tester has been used for a functional test of a one-chip microcomputer. FIG. 3 is a block diagram showing a configuration of a conventional LSI tester. In a conventional LSI tester, a device under test (DUT) 22 on which a functional test (logic test) is performed is performed.
Signal generator 21 for inputting a clock signal to D
A pattern control unit 27 for controlling a pattern of an instruction code input to the UT 22, a constant voltage source 23 for applying a predetermined voltage to the DUT 22, and a comparison circuit 26 connected to an output terminal of the DUT 22 are provided. Further, the comparison circuit 26 is connected to an expected value pattern generation circuit 25 which stores and generates an expected value signal of a pulse wave output when the DUT 22 is a non-defective product. Further, the pattern control unit 27 is connected to a pattern memory unit 28 in which a pattern of an instruction code input to the DUT 22 is stored.

In the conventional LSI tester configured as described above, a clock signal of a predetermined clock frequency is input from the clock signal generator 21 to the DUT 22, and an instruction code stored in the pattern memory unit 28 in advance is, for example, The peak portion indicates a signal “1 (HIGH)”, and the valley portion indicates a signal “0 (LOW)”. And
A predetermined voltage is applied to the DUT 22 from the constant voltage source 23. As a result, the input instruction code is decoded and executed, and an output signal is output from the output terminal of the DUT 22 as a pulse wave. On the other hand, the expected value pattern generation circuit 25 outputs an expected value signal of a pulse wave stored in advance. The pulse wave output from the DUT 22 and the pulse wave output from the expected value pattern generation circuit 25 are constantly compared by the comparison circuit 26. As a result of the comparison, if the two match, the DUT 22 is determined to be non-defective, and if the two are different, the DUT 22 is determined to be defective.

A data reading test method for a nonvolatile memory has been proposed (Japanese Patent Laid-Open No. 9-45100). In the test and test method described in this publication, read data compiled for each specified address of a memory under test is compared with its expected value. Therefore, according to the conventional test method, the capacity of the memory for storing the expected value can be reduced.

[0005]

However, since the expected value pattern generation circuit 25 provided in the above-described conventional LSI tester needs to store a huge amount of information, its capacity is large and the LSI tester is extremely expensive. There is a problem that it becomes. Further, even with the conventional data read test method for a nonvolatile memory, the reduction of the capacity of the expected value storage memory is not sufficient.

[0006] The present invention has been made in view of the above problems, and has as its object to provide an inexpensive test system capable of deleting a memory requiring a huge capacity.

[0007]

According to the present invention, there is provided a test system for performing a function test of a device, comprising: a 1-counter for counting the number of 1 of a digital signal output from the device at the time of the function test; A memory unit for a one-count expected value storing an expected value of one count of the digital signal output from the device within a predetermined time during the function test, and counting by the one-counter within the predetermined time. A comparison circuit for comparing the number of times 1 with the expected value stored in the expected one count memory.

In the present invention, the number of times a signal "1" is output within an arbitrary time from a signal output from a device to be subjected to a functional test is counted by a one-counter counter, and the counting result and one-count expected value are counted. The comparison value is compared with the expected value stored in the memory unit. If they match, the device is determined to be good,
If they are different, the device is determined to be defective. Therefore, the information stored in the memory unit for one count expected value only needs to be the expected value of one time of the digital signal output from the device within a predetermined time, so that the capacity can be significantly reduced.

In the present invention, it is possible to have a clock signal generator for inputting a clock signal to the device at the time of the function test, and a constant voltage source for applying a predetermined voltage to the device.

[0010] The apparatus may further include a pattern memory unit for storing a pattern of an instruction code input to the device at the time of the function test, and a pattern control unit for controlling the pattern and inputting the pattern to the device.

Since the pattern of the instruction code for the function test is input from the outside of the device, the function test can be performed without being limited by the capacity of the internal ROM built in the device, and a highly reliable test can be performed. It can be carried out.

[0012] When a predetermined voltage is applied to the device from the constant voltage source, the device may be set to a state in which a functional test is performed.

A device to be subjected to a functional test has an internal ROM in which a test program is stored, and is set to a state in which the test is performed when a predetermined voltage is applied from a constant voltage source. Since it is not necessary to input an instruction code, a circuit or the like for that purpose is not required.

In the present invention, it can be used for testing a one-chip microcomputer.

[0015] The one-counter may have as many input terminals as the number of output terminals of the device.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A test system according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of the test system according to the first embodiment of the present invention. In this embodiment, a clock signal generator 1 that inputs a clock signal to a device under test (DUT) 2 on which a functional test (logic test) is performed, and a constant voltage source 3 that applies a predetermined voltage to the DUT 2
Is provided. The DUT 2 has an internal ROM in which a test instruction code is stored. Constant voltage source 3
When a predetermined voltage is applied to DUT2 from
UT2 is set to the test mode. Here, the test mode means that when a clock signal is input to DUT2, DU is output.
In this mode, a program stored in an internal ROM incorporated in T2 is executed and a pulse wave of a predetermined amplitude is output from an output terminal of DUT2. In this pulse wave, for example, a peak indicates a signal “1 (HIGH)” and a valley indicates a signal “0 (LOW)”.

Further, 1 connected to the output terminal of the DUT 2
A count counter 4 is provided. The one-counter 4 is provided with the same number of input terminals as the number of output terminals of the DUT 2. The one-counter 4 outputs DU during the test mode.
From the shape of the pulse wave output from T2, the number of times signal "1" is transmitted within an arbitrary predetermined time is counted.

A comparison circuit 6 is connected to the one-counter counter 4, and a one-count expected value memory unit 5 is connected to the comparison circuit 6. The one-count expected memory unit 5 stores an expected value of the number of times the signal “1” is output within a predetermined time when the DUT 2 is a non-defective product. For example, 1781 times a second, 11790 times a second
The expected value, such as 2,078 times in 3 seconds, is stored. Therefore, an extremely small capacity of the one-count expected value memory unit 5 is sufficient. Further, the comparison circuit 6 compares the number of occurrences of the signal “1” counted by the one-counter 4 with the expected value stored in the one-count expected value memory unit 5,
This is for determining the quality of the UT2.

Next, the operation of the test system of the first embodiment thus configured will be described. In the test system of the present embodiment, when a predetermined voltage is applied from the constant voltage source 3 to the DUT 2, the DUT 2 is set to the test mode. When a clock signal is input from the clock signal generator 1 to the DUT 2, the program stored in the internal ROM is executed, and the circuit block operates to output a signal "1" or "0" as a pulse wave from the output terminal. Is output. In addition, the expected value of the number of times that the signal “1” is output from the DUT 2 when the DUT 2 is non-defective is stored in the one-count expected value memory unit 5 in advance.

Next, the number of times that the signal "1" is output within an arbitrary time from the result output from the DUT 2 is counted by the one-counter counter 4, and this count result and the one-count expected value memory unit 5 are stored. By comparing the set expected value with the comparison circuit 6, the circuit block of the DUT 2 is tested. That is, as a result of comparison by the comparison circuit 6, if the two match, the DUT 2 is determined to be non-defective, and if the two are different, the DUT 2 is determined to be defective.

As described above, in the present embodiment, the function test of the DUT 2 is performed by counting the number of times of the signal “1” output from the DUT 2 within a predetermined time. The required expected value pattern generation circuit is unnecessary. In addition, the DUT 2 from the constant voltage source 3
Since the DUT 2 is set to the test mode by applying a predetermined voltage to the DUT 2, a memory for storing a pattern input to the DUT 2 is not required. Therefore, the test system is inexpensive and simple.

In the test system of this embodiment, for example, a functional test of a one-chip microcomputer is performed.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the test system according to the second embodiment of the present invention. In the second embodiment, a pattern control unit for controlling a pattern of an instruction code input to a device under test and a pattern memory unit for storing the instruction code are provided. Note that FIG.
In the second embodiment shown in FIG. 7, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 2, in the second embodiment, a pattern control unit 17 for controlling a pattern of an instruction code input to the DUT 2 is provided. A pattern memory unit 18 for storing patterns is connected.

In the test system according to the second embodiment, a clock signal having a predetermined clock frequency is input from the clock signal generator 1 to the DUT 2, and a command stored in the pattern memory 18 in advance is provided. For example, the code is a pulse wave that indicates a signal “1” at the peak and a signal “0” at the valley.
Is input to the DUT 2, and a predetermined voltage is applied to the DUT 2 from the constant voltage source 3. As a result, the input instruction code is decoded and executed,
The circuit block operates to output a digital signal indicating a signal “1” or “0” as a pulse wave from the output terminal.
Then, the circuit blocks of the DUT 2 are tested by the same steps as in the first embodiment.

As described above, in this embodiment, the pattern control unit 17 and the pattern memory unit 18 are required, but the circuit block of the circuit block can be used without using the conventionally used large-capacity expected value pattern generation circuit. A functional test is performed. Therefore, the test system is inexpensive and simple. In addition, since the function test can be performed without being limited by the capacity of the internal ROM built in the DUT 2, a test with higher reliability can be performed.

[0026]

As described in detail above, according to the present invention,
The information stored in the memory unit for one count expected value only needs to be the expected value of one time of the digital signal output from the device within a predetermined time, so that the capacity can be significantly reduced. As a result, the test system does not require a memory having a huge capacity and is inexpensive.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a test system according to a first example of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a test system according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional LSI tester.

[Explanation of symbols]

 1, 21; clock signal generator 2, 22; device under test (DUT) 3, 23; constant voltage source 4, 1 count counter 5, 1 expected count memory 6, 26; comparison circuit 17, 27; Control units 18, 28; pattern memory unit 25; expected value pattern generation circuit

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[Procedure amendment]

[Submission date] December 28, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

[0007]

According to the present invention, there is provided a test system for performing a function test of a device, comprising: a 1-counter for counting the number of 1 of a digital signal output from the device at the time of the function test; A memory unit for a one-count expected value storing an expected value of one count of the digital signal output from the device within a predetermined time during the function test, and counting by the one-counter within the predetermined time. have a comparison circuit for comparing the expected value stored in the first number and the one count expected value memory, wherein
One count counter is the same as the number of output terminals of the device
Characterized in that it have the input terminals.

Claims (6)

[Claims] 1. A test system for performing a function test of a device, a 1-counter for counting the number of 1 of a digital signal output from the device at the time of the function test,
A memory unit for a one-count expected value storing an expected value of one count of the digital signal output from the device within a predetermined time during the function test, and counting by the one-counter within the predetermined time. A test system, comprising: a comparison circuit for comparing the number of times 1 with an expected value stored in the expected one-value memory. 2. The test according to claim 1, further comprising: a clock signal generator for inputting a clock signal to the device at the time of the function test; and a constant voltage source for applying a predetermined voltage to the device. system. 3. A pattern memory unit for storing a pattern of an instruction code input to the device at the time of the function test, and a pattern control unit for controlling the pattern and inputting the pattern to the device. Claim 1
Or the test system according to 2. 4. The test system according to claim 2, wherein when a predetermined voltage is applied to the device from the constant voltage source, the device is set to a state in which a functional test is performed. 5. The test system according to claim 1, wherein the test system is used for testing a one-chip microcomputer. 6. The test system according to claim 1, wherein the one-counter has the same number of input terminals as the number of output terminals of the device.