JPH11205159A - Interleave method and device and de-interleave method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform interleave and de-interleave processings for each bit by simple circuit constitution to high-speed sampling 1-bit digital audio. SOLUTION: Serial input digital data DI are turned to 1-byte parallel data PD1 in an S/P conversion circuit 4, written to a buffer storage circuit 5 by the block unit of a prescribed bit number by address signals R/W.AD from an address generation circuit 7 and repeatedly read by the address signals R/W.AD of a reverse order for which the high order and low order of the bit array of the address signals R/W.AD are inverted and the bit of the order specified by selection address signals BS.AD from the address generation circuit 7 is selected for each byte in a bit selection circuit 6. Thus, output digital data DO for which the input digital data DI are interleaved by a bit unit are obtained. This de-interleave device is similar and the digital data of the original bit array are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio encoding apparatus, a decoding apparatus, a digital audio transmitting apparatus and a receiving apparatus, and more particularly, to digital audio data (such as digital audio data (burst-like data loss) having a great effect on data reproduction results. For example, the present invention relates to an interleave / deinterleave method and apparatus used for encoding and decoding of linear digital audio and a stream after 1-bit delta-sigma modulation.

[0002]

2. Description of the Related Art In digital audio equipment,
It is necessary to protect audio data for which temporal continuity is essential from burst errors. For conventional digital audio devices (eg, CDs), published by Corona Co., Ltd .: Supervised by Mari Fujio: "Latest AV Devices and Digital Technology" p. 1 byte as described in 45 (= 8 bits)
Has been performed as a data unit. This interleaving process is realized by changing the write address and the read address to the buffer storage RAM in different orders.

On the other hand, in recent years, high-speed sampling 1-bit digital audio has been actively studied, as described in, for example, JAS Conference 90 Proceedings: "Future Speech Coding Technology" by Yoshio Yamazaki.
For example, conventionally, for audio data of 16 bits and a sampling frequency Fs of 48 kHz, 3.02M corresponding to 1 bit and a sampling frequency of 64 × Fs.
It has become clear that high quality audio data can be transmitted in a Hz ΔΣ (delta sigma) modulated stream.

FIG. 18 is a block diagram schematically showing a conventional example of this system, in which 100 is an input terminal, 101 is a high-speed sampling 1-bit encoder, 102 is a sampling circuit, 103 is a delta-sigma modulation circuit, 104 is a differentiator, 105 is an integrator, 106 is a 1-bit quantizer, 10
7 is a delay unit, 108 is a 1-bit DAC (digital / analog converter), 109 is an output terminal, 110 is an input terminal, 111 is a decoding circuit, 112 is a low-pass analog filter, and 113 is an output terminal.

In FIG. 1, an analog audio signal S 1 is input from an input terminal 100 to a high-speed sampling 1-bit encoder 101. This analog audio signal S1 is sampled at a high sampling frequency of 3.072 MHz by the sampling circuit 102 and then delta-sigma modulated by the delta-sigma modulation circuit 103. In this example, the first-order delta-sigma modulation is shown for the sake of simplicity. However, usually, the fifth-order delta-sigma modulation largely drives the quantization noise to a frequency band higher than 1/6 of the sampling frequency, and The sound quality of the band is improved.

[0006] The delta-sigma modulation circuit 103 includes a differentiator 1
04, an integrator 105, a 1-bit quantizer 106, a delay unit 107, and a 1-bit DAC 108. A difference signal S3 between the analog audio signal S2 from the sampling circuit 102 and the delayed analog audio signal S7 from the 1-bit DAC 108 is generated by a differentiator 104, and the difference signal S3 is cumulatively added by an integrator 105 and the cumulative added value is obtained. S4 is obtained. The 1-bit quantizer 106 generates a quantized signal S5 which becomes 1 when the cumulative addition value S4 is higher than the standard value and becomes 0 when the cumulative addition value S4 is lower than the standard value, and this quantized signal S5 is used as a ΔΣ modulation stream S8. Output from the output terminal 109. The quantized signal S5 is delayed by one sample period by the delay unit 107.
The delayed quantized signal S6 is converted to a 1-bit DAC 10
After being converted into an analog value at 8, the analog value is supplied to the differentiator 104 as the delayed analog audio signal S7.

According to this method, as described in the above-mentioned JAS Conference 90 Proceedings: "Future Speech Coding Technology" by Yoshio Yamazaki, an original analog signal is included in a ΔΣ modulated stream S8 as a 1-bit high-speed sampling digital stream. Since the frequency characteristics of the audio are retained, the input terminal 11 is connected to the decoder 111 having a simple configuration including the analog low-pass filter 112 on the receiving side.
By supplying from 0, it is possible to obtain an analog audio signal decoded and reproduced from its output terminal 113.

In addition, since downsampling at the time of analog / digital conversion in multi-bit encoding and upsampling at the time of digital / analog decoding are not required, re-quantization noise is not generated. It has an effect and is expected as a next-generation digital audio device.

[0009]

By the way, in the above-mentioned conventional high-speed sampling 1-bit digital audio system, temporal continuity is indispensable, so that it is considered that the same processing as the above-mentioned interleaving processing is required. However, 1 byte (8 bits) and 1
Interleaving in units of words (16 bits) is not meaningful and requires interleaving to change the order in units of 1 bit.

However, in this case, the reproduction system is simply realized by the high-speed sampling 1-bit digital audio system if the complexity of the circuit configuration on the reproduction side is significantly increased by adding an address generation circuit for interleave processing. The benefit of the elimination is halved. Therefore, an interleaving process in which the address generation procedure is simple is required.

SUMMARY OF THE INVENTION The present invention has been made in view of such a demand, and has as its object to simplify an address generation procedure and to provide an interleaving method and apparatus capable of performing interleaving and deinterleaving in bit units, and a deinterleave. It is to provide a method and an apparatus.

[0012]

In order to achieve the above object, the present invention divides a 1-bit data stream into blocks of 2 ^N bits, and places 0 to (2 ^N Assign the address of -1). A bit reverse order address is obtained by reversing the order of arrangement of the address from the MSB (most significant bit) to the LSB (least significant bit) when the address is expressed in a binary number.

For example, when the block length is 2 ⁴ (= 16) bits, as shown in FIG. 2A, the address in the bit normal order (the order of the original bits) is set to the MSB as L.
..,..., The LSB to the MSB, and the bit arrangement is reversed (hereinafter, referred to as bit reverse order) to obtain a bit reverse order address. When the block length is 2 ⁶ (= 64), FIG.
The bit reverse order address is obtained as shown in FIG.

Here, while the value of the bit-forward address changes sequentially one by one, the value of the bit-reverse address changes greatly. For example, block length = 2 ⁴ (= 1
6) Assuming that a 4-bit bit-forward address with respect to bits is as shown in FIG. 7, the value of this bit-forward address increases by 1 in the arrangement order. The bit reverse address with respect to the bit normal address has an arrangement order as shown in FIG. According to this, in the arrangement order, each one greatly differs from the value of the immediately preceding one.

Interleave processing is performed according to the change in the value of the bit-reverse address to reconstruct the interleaved 1-bit data stream. For example, the above-described interleaving process in a block having a block length of 2 ⁴ (= 16) bits will be described with reference to FIG.
.., 15 shown in FIG. 7 are assigned in order from the top of the block. If the bits are interleaved with bit-reverse addresses shown in FIG. The bits are arranged in the order of 0, 8, 4, 12,.

At the same time, a block start signal indicating the start timing of a block serving as an interleave processing unit is generated. This block start signal is used to detect the boundary of the interleaved block in the deinterleave processing in the reproduction system, and thereby the timing of clearing the address counter is set.

Also, various signals such as a block start signal and an interleaved 1-bit data stream are multiplexed and transmitted as one multiplexed stream. On the deinterleave side, various signals are separated from the multiplexed stream and deinterleaved. Used for

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an interleaving method and apparatus according to the present invention, wherein 1 is an interleaving apparatus, 2 is an input terminal of a 1-bit stream, 3 is a bit clock input terminal, and 4 is an S / P (serial). / Parallel) conversion circuit, 5 is a buffer storage circuit, 6 is a bit selection circuit, 7 is an address generation circuit, 8 is an address counter circuit, 9 is a bit order switching circuit, 10 is a 1-bit stream output terminal, and 11 is a block start. Signal output terminal. In this embodiment, the data block size is 2 ⁶ (= 64) bits.

In FIG. 1, digital data DI of one bit stream (that is, a serial stream arranged in a time series of one bit) is input from an input terminal 2, and a bit clock φB is input from an input terminal 3. Supplied to The bit clock φB is synchronized with each bit of the input digital data DI.

In the interleave device 1, the input digital data DI is converted into one byte (= 8) by the P / S conversion circuit 4.
), And is stored in the buffer storage circuit 5. The one-byte parallel data PD1 is data having a period eight times as long as the period Tφ of the bit clock φB. Hereinafter, one-byte bits arranged in parallel will be referred to as byte data.

The 1-byte parallel data PD1 is written into the buffer storage circuit 5 by using a 3-bit read / write byte address signal R / W.AD of 8Tφ cycle generated by the address generation circuit 7 as a write address. By acting as a signal, the data is sequentially performed one byte data at a time. The read / write byte address signal R / W.AD as the write address signal sequentially specifies the one-byte parallel data PD1 to be written to the addresses 0, 1, 2,... Then, when one byte of parallel data PD1 for 8 bytes (= 64 bits, therefore, one block) is written, the one byte parallel data PD1 for the next one block is similarly written at addresses 0, 1, 2,. ..., 7 are sequentially designated for writing.

The 1-byte parallel data PD1 written in the buffer storage circuit 5 in this manner is read by a 3-bit read / write byte address signal R / W.AD as a read address signal. In this case, the read / write byte address signal R / W · AD as the read address signal is different from the read / write byte address signal R / W · AD as the write address signal.
This is an address signal that changes in accordance with a rule described later with a period Tφ of the bit clock φB, and is one block per one period (= 8Tφ) of the read / write byte address signal R / W · AD as a write address signal. The byte parallel data PD1 is read out of the eight byte data constituting it in a different order from that at the time of writing.

That is, the same one block of 1-byte parallel data PD1 stored in the buffer storage circuit 5 is repeatedly read out eight times. In this case, each read out constitutes one block. The arrangement order of the eight byte data is different from that at the time of writing to the buffer storage circuit 5. By such a read operation, the parallel data PD2 obtained by interleaving the byte array with respect to the 1-byte parallel data PD1 at the time of writing is obtained from the buffer storage circuit 5 in units of one block. This parallel data PD2 is data having a cycle equal to the cycle Tφ of the bit clock φB.

The parallel data PD2 is supplied to the bit selection circuit 6. In the bit selection circuit 6, the bit selection address signal BS generated by the address generation circuit 7
By AD, the parallel data PD2 is selected and arranged serially one bit at a time for each parallel byte.

In this case, the bit selection address signal BS.
AD has the same value in the 8-byte period of the parallel data PD2, but it is decremented every time the 8-byte period elapses. Moreover, the value of the bit selection address signal BS.AD changes according to the rules described later. Therefore, in the 8-byte period of the parallel data PD2, 8 bytes
Bits of the same order in the bit array are selected, but in the next 8-byte period, they have the same order during that period,
A bit with a different order than the previous 8-byte period will be selected.

Such an operation is repeated for each block of the parallel data.
One bit stream digital data DO is obtained by interleaving the bit stream digital data DI in block units. The digital data DO is output from the output terminal 10.

The address generation circuit 7 comprises an address counter circuit 8 and a bit order switching circuit 9. The address counter circuit 8 counts the bit clock φB from the input terminal 3 and each time the bit clock φB is supplied, the 6-bit bit forward address AD changes to 0, 1, 2,... And the buffer storage circuit 5
Area switching signal AS for switching the storage area between writing and reading, a read / write switching signal R / W for controlling the bit order switching circuit 9, and the start timing of a block serving as a unit of interleave processing Is generated. This block start signal BS is output from the output terminal 11.

The bit order switching circuit 9 comprises six changeover switches 91, 92,..., 96. Each of the changeover switches 91, 92,..., 96 synchronizes with the read / write changeover signal R / W every time 1-byte data of the 1-byte parallel data PD1 is started to be output from the S / P conversion circuit 4. １ ／ of the bit clock φB
It closes to the W contact side during the period and closes to the R contact side during the other periods.

The 6-bit bit forward address AD generated by the address counter circuit 8 has the MSB at the W contact of the changeover switch 91, the next higher bit at the W contact of the switch 92, and the next higher bit. The upper bit is supplied to the W contact of the switch 93,..., LSB is supplied to the W contact of the switch 96, respectively.
.., LSB are connected to the R contact of the switch 91, and the LSB is connected to the R contact of the switch 91. Supplied.

Then, the changeover switches 91, 92,.
When 96 is closed to the W contact side, the forward address supplied thereto is output from the bit order switching circuit 9 as it is, but when switched to the R contact side, the MSB is changed to the LSB,
The bit normal address AD is set so that the LSB becomes the MSB.
Is obtained, a bit reverse order address obtained by inverting the bit arrangement of the upper and lower bits is obtained.

As described above, the bit order switching circuit 9 outputs the one-byte parallel data P from the S / P conversion circuit 4.
During a period of 周期 cycle of the bit clock φB at which the output of one byte data of D1 is started, the changeover switches 91, 92,.
, 96 are closed to the W contact side and the 6-bit normal address AD is output as it is, and during the other periods, the changeover switches 91, 92,. The address is output. The upper three bits of these bit forward and reverse addresses are supplied to the buffer storage circuit 5 as the read / write byte address R / W.AD, and the lower three bits are the bit selection address BS.AD.
Is supplied to the bit selection circuit 6.

FIG. 2B shows the relationship between the 6-bit forward address and the 6-bit reverse address.
Since the bit arrangement is reversed between these, as shown in the figure, for example, the bit forward address “011011” having a value of “27” in decimal becomes a bit reverse address “110110” of “54” in decimal. .

However, the upper three bits of the bit normal address and the bit reverse address are the read / write byte address R / W · AD of the buffer storage circuit 5.
The lower 3 bits of the bit reverse address are the bit selection circuit 6
Of the bit selection address BS.AD. Therefore, the read / write byte address R / W · AD changes its value every eight clocks of the bit clock φB when using the bit normal order address, whereas the bit clock when using the bit reverse order address. The value changes every φB clock. Further, the value of the bit selection address BS · AD based on the bit reverse address changes every clock of the bit clock φB.

FIG. 3 shows the relationship between the bit forward address and the bit reverse address and the input digital data DI in FIG.
And the bit arrangement of the output digital data DO. The numbers in the columns A and B represent the bit numbers of the input digital data DI (for example, the first bit in the block of the input digital data DI). , Bit 0, and bit 1, bit 2,..., Bit 63 in the order of arrangement. Column A shows the bit arrangement of the input digital data, and Column B shows the bit arrangement of the output digital data DO. I have.

The read / write byte address R / W.AD for writing in the buffer storage circuit 5, which is the upper three bits of the bit normal address, has its address value sequentially set to "0" every eight clocks of the bit clock φB. ₁₀ , "1" ₁₀ , "2" ₁₀ ,
It changes to “3” ₁₀ , “4” ₁₀ , “5” ₁₀ , “6” ₁₀ , “7” ₁₀ (note that “” ₁₀ represents a decimal number). This allows
As described above, in the buffer storage circuit 5, the 1-byte parallel data PD1 is output every eight clocks of the bit clock φB.
Are supplied one byte at a time, and these are sequentially addressed as “0”.
₁₀ , "1" ₁₀ , "2" ₁₀ , "3" ₁₀ , "4" ₁₀ , "5" ₁₀ , "6"
₁₀ , “7” is stored in ₁₀ .

The read / write byte address R / W.AD for reading from the buffer storage circuit 5, which is the upper three bits of the bit reverse address, has an address value of "0" sequentially for each clock of the bit clock φB. " ₁₀ ," 4 " ₁₀ ,
It changes to “2” ₁₀ , “6” ₁₀ , “1” ₁₀ , “5” ₁₀ , “3” ₁₀ , and “7” ₁₀ . That is, in the buffer storage circuit 5, the addresses “0” ₁₀ , “4” ₁₀ , “2” ₁₀ , “6” ₁₀ , “1” ₁₀ ,
Reading is performed in the order of “5” ₁₀ , “3” ₁₀ , and “7” ₁₀ , and this reading is repeated every eight clock periods of the bit clock φB. For this reason, the 1-byte parallel data PD1 of the same block is repeatedly read eight times, but the reading order of the eight 1-byte data forming this block is completely different from that at the time of writing.

Therefore, in FIG. 4, 1-byte parallel data PD for one block of the buffer storage circuit 5 is now shown.
The address of the storage area for 1 byte of 1 is 0, respectively.
Assuming that 1, 2,..., 7, one byte of one-byte parallel data PD1 for one block is stored in each area.
,..., Are written in this order. The 1-byte parallel data PD1 for one block written in this manner is read out from each storage area one byte at a time in the order of,. This reading is
It is repeated eight times during the period in which the next one block of 1-byte parallel data PD1 is written.

In view of the above, the buffer storage circuit 5 has at least two units each having such a capacity as to store the one-byte parallel data PD1 for one block, of which one is written. Switching is controlled by the area switching signal AS so that reading is performed on the other side.

The bit selection address BS.AD of the bit selection circuit 6, which is the lower three bits of the bit reverse address, is
The same address value is taken for eight clock periods of the bit clock φB for reading one block of one-byte parallel data PD1 at the read / write byte address R / W · AD for reading from the buffer storage circuit 5, but the bit clock φ
Each time the 8 clock periods of B elapse, “0” ₁₀ , “4” ₁₀ ,
It changes in the order of “2” ₁₀ , “6” ₁₀ , “1” ₁₀ , “5” ₁₀ , “3” ₁₀ , and “7” ₁₀ .

The bit selection address BS.AD designates, for each byte of the 1-byte parallel data PD2 read out from the buffer storage circuit 5 as described above, a bit to be extracted among the 8 bits constituting the byte. Is what you do. For example, if the bit selection address BS / AD is “0” ₁₀
Then, the 0th bit is extracted and output from the 8 bits constituting one byte supplied to the bit selection circuit 6.

The eight bits forming one byte are represented by # in the order in which they are arranged in advance by the input digital data DI.
Assuming that the bits are 0, # 1, # 2,..., # 7, in FIG. 5, in the 1-byte parallel data PD2 for one block read out from the buffer storage circuit 5 for the first time, the bit selection address BS.AD Since the address value is “0” ₁₀ , the # 0 bit hatched with diagonal lines is extracted for each byte, and the 1-byte parallel data PD2 for one block to be read out for the second time is selected by a bit. Since the address value of the address BS / AD is “4” ₁₀ , the # 4 bit hatched with diagonal lines is extracted for each byte. In this manner, for each one-byte parallel data PD2 of one block from the buffer storage circuit 5, the bits extracted from the eight bytes constituting the data are # 0, # 4, # 2, # 6, and # 1. , # 5, #
3, # 7.

In this way, the bit selection circuit 6 obtains the digital data DO of a 1-bit stream whose phase is synchronized with the frequency of the bit clock φB and is output from the output terminal 10 to the outside.

By the way, 1 of the input digital data DI
In the block, bit 0, bit 1, bit 2, bit 3,..., Bit 63 in the order of arrangement from the first bit
In FIG. 5, the bit of # 0 of 1 byte (0) read first in the reading of the first block from the buffer storage circuit 5 is bit 0, and 1 byte (4) read next The bit of # 0 is bit 32, and the bit of # 0 of 1 byte (2) to be read next is bit 16..., # Of 1 byte (7) read at the end of the first read Bit 0 is bit 5
6.

Then, the next 1 from the buffer storage circuit 5
The # 4 bit of 1 byte (0) that is read first in the reading of the block is bit 4, the # 4 bit of 1 byte (4) that is read next is bit 36, and is read next. The bit of # 4 of 1 byte (2) is bit 20..., The bit of # 4 of 1 byte (7) read at the end of the first read is bit 6
0.

Similarly, looking at the bit arrangement of the digital data DO of the 1-bit stream output from the bit selection circuit 6, the bit arrangement shown in the column "A" in FIG. The bit arrangement order is as shown in the column "B". That is, the bit i (where i = 0, 1, 2,..., 6)
The arrangement order Ni of 3) is as follows: Ni = a _i5 · 2 ⁵ + a _i4 · 2 ⁴ + a _i3 · 2 ³ + a _i2 · 2 ² +
a _i1 · 2 ¹ + a _i0 · 2 ⁰ where a _i5 , a _i4 , a _i3 , a _i2 , a _i1 , a _i0 are 1 or 0, and in the output digital data DO, the arrangement order of these bits i No is: No = a _i0 · 2 ⁵ + a _i1 · 2 ⁴ + a _i2 · 2 ³ + a _i3 · 2 ² +
become ^{_{a i4 · 2 1 + a i5}} · 2 0. That is, if the bit order of the input digital data DO in one block is represented by a 6-bit binary number, the bit order in the one block of the output digital data DO is the six bits constituting the 6-bit binary number. Are converted into an order represented by a binary number in which the upper and lower bits are inverted. In this manner, the input digital data D
Output digital data DO in which I is interleaved in bit units for each block is obtained.

Generally, input digital data DI is 2 ^N
When a bit-forward address and a bit reverse order obtained by inverting the upper and lower bits of the bit order are set to N bits, the order of the bits in the block of the input digital data DI is An address is assigned, and the arrangement order of the bit i is Ni, that is, Ni = a _{i (N−1)} · 2 ^(N−1) + a _{i (N−2)} · 2 ^(N−2) + a
_{i (N-3) · 2} (N-3) + ...... + When a _i0 · 2 ^0, the output digital data DO, the bit i ^{_{is, No = a i0 · 2 (}} N-1) + a i1 · 2 ^(N-2) + …… + a _{i (N-2)
^{· 2 1 + a i (N}} -1) · 2 will be arranged in ^{the zeroth,} interleaved 1
Bit stream digital data DO is obtained.

FIG. 6 is a timing chart showing the operation of the embodiment shown in FIG. 1 when the data block size (block length) is 2 ⁴ (= 16 bits).

Also in this case, the S / P conversion circuit 4 in FIG. 1 supplies the one-byte parallel data PD1 to the buffer storage circuit 5, so that one block is composed of two bytes. , The one-byte digital data of one block is repeatedly read twice.

At this time, the bit normal address AD generated by the address counter circuit 8 in FIG.
The bit reverse address generated by the bit order switching circuit 9 is also 4 bits, of which one MSB is read / read.
The write byte address signal R / W · AD becomes the lower 3 bits.
The bit is the bit selection address BS of the bit selection circuit 6.
AD. FIG. 2A shows the relationship between the bit forward address and the bit reverse address in this case.
For example, bit normal order address of "0101" (decimal "5" _10), when converted into bit-reversed address,
The value is “1010” (“10” _{10 in} decimal).

6A shows a bit clock φB input from the input terminal 3 of FIG. 1, and as shown in FIG. 6B, each bit is synchronized with the bit clock φB. Input digital data DI is input from input terminal 2 in FIG. Here, 16 bits for one block are designated as bit 0, bit 1, bit 2, bit 3,..., Bit 15 in the order of arrangement. The order of the bit arrangement corresponds to the bit forward address. FIG. 7 shows the relationship between the decimal number and the binary number of the bit forward address.

FIG. 6C shows the input digital data D
FIG. 6D shows an area switching signal AS for switching and setting a write mode and a read mode of a storage area in units of blocks in the buffer storage circuit 5.

When the input digital data of one block shown in FIG. 6B is stored in the buffer storage circuit 5 as 1-byte parallel data PD1, the storage area in which the data is written is set to the high level of the area switching signal AS. As a result, a read mode is set, and the digital data of this block is read and supplied to the bit selection circuit 6. As a result, as shown in FIG. 6E, output digital data DO interleaved in bit units is obtained. The bit arrangement of the block in the output digital data DO is shown in FIG.
The order is shown as a decimal number.

Here, when the input digital data DI at the input terminal 2 and the output digital data DO at the output terminal 10 in FIG. 1 are viewed in bit units, the S / P in FIG.
Assuming one circuit block having the functions of the conversion circuit 4, the buffer storage circuit 5, and the bit selection circuit 6, the read / write switching signal R generated by the address counter circuit 8 of FIG. / W is shown in FIG.
As shown in (f), it is synchronized with the bit clock φB. At the high-level timing of the read / write switching signal R / W, bit 0, bit 1, bit 2,..., Bit 14, bit 15 of the input digital data DI are taken into the assumed circuit block in that order. Also, at the low-level timing of the read / write switching signal R / W, each bit is output from the assumed circuit block in the order of the bit reverse address in FIG.
.., Bit 7 and bit 15 in the order of bit digital output DO. FIG. 6G shows the bit relationship between the input digital data DI and the output digital data DO with respect to the read / write switching signal R / W shown in FIG. 6F.

In the circuit configuration shown in FIG.
When the read / write switching signal R / W shown in (f) is at a high level, the switches 91 and 9 in the bit order switching circuit 9 are switched.
When 2,..., 96 are switched to the W side, the S / P
The one-byte parallel data PD1 from the conversion circuit 4 is written into the buffer storage circuit 5, and the changeover switches 91, 92,... In the bit order changeover circuit 9 are provided for each low level of the read / write changeover signal R / W. .., 96 are switched to the R side, so that reading is performed byte by byte. At the time of this writing, hatching is performed by hatching every eight clocks of the bit clock φB in the read / write switching signal R / W. Only at the time of the high level shown in FIG. 5, 1-byte parallel data PD1 is written into buffer storage circuit 5.

As described above, in the first embodiment, the interleaved output digital data DO is obtained. In the output digital data D0, as shown in FIG. 3 and FIG. The odd-numbered bits in the block of the digital data DI are arranged in the second half, and the even-numbered bits are arranged in the first half.
(I + 1) indicates that in the output digital data DO,
They will be arranged far enough apart. For example, when one block length is 16 bits, as is clear from FIG.
The adjacent bits i and (i + 1) have at least 4 bits. When one block length is 64 bits, adjacent bits i and (i + 1) have at least 16 bits, as is clear from FIG. In general, when one block length is composed of 2 ^N bits, adjacent bits i,
(I + 1) is separated by at least 2 ^(N-2) bits.

Thus, in the first embodiment, excellent interleave processing is performed despite simple operations.

A block start signal BS (FIG. 6C) is output from the address counter circuit 8 as a signal indicating the start timing of the block of the above-mentioned interleave processing. On the receiving side, the block start signal BS and the interleaved 1-bit stream output digital data DO are sent, so that the output digital data DO can be easily deinterleaved as described later.

At this time, an area switching signal AS for switching the read / write access area of the buffer storage circuit 5 can be used as the block start signal BS. The area switching signal AS is a signal for switching the area in which the writing / reading is performed, and when the buffer storage circuit 5 is provided with two storage areas for one block, the one in which the previous one block was written is used. This block is read from the storage area (for example, area A), and the next block is written in the other storage area (area B) during the read period of this block. During the writing period in the storage area of the block, the stored block is read.

By using such a procedure, the interleave processing can be performed with a simple circuit configuration. Also, the receiving side may perform the same processing, and the further reverse order of the bit reverse order returns to the bit normal order, so that there is almost no burden on the receiving apparatus.

FIG. 8 is a block diagram showing a first embodiment of a deinterleaving method and apparatus according to the present invention.
12 is a deinterleave device, 13 is a 1-bit stream input terminal, 14 is a bit clock input terminal, 15
Is a P / S conversion circuit, 16 is a buffer storage circuit, 17 is a bit selection circuit, 18 is a block start signal input terminal, 19 is an address generation circuit, 20 is an address counter circuit, 21 is a bit order switching circuit, and 22 is 1 Output terminal for bit stream.

In the figure, input digital data DI ′ of one bit stream is input from an input terminal 13, and bit clock φB is input from an input terminal 14 to the deinterleaver 12. This input digital data D
I ′ is 1-bit stream digital data interleaved by the interleaving device 1 shown in FIG. 1 as described above. This deinterleave device 1
2 performs the same operation as the interleave device 1 shown in FIG.
I ′ is deinterleaved into one bit stream of the original bit arrangement.

In the deinterleave device 12, the input digital data DI 'is converted into 1-byte parallel data PD3 by the P / S conversion circuit 15, and then written into the buffer storage circuit 16.

On the other hand, the address generation circuit 19 operates in the same manner as the address generation circuit 7 shown in FIG. 1, and the address counter circuit 20 counts by the block start signal BS indicating the start point of the block inputted from the input terminal 18. By counting the bit clock φB from the input terminal 14 while clearing, as in the address counter circuit 8 in FIG.
D ', the area switching signal AS', and the read / write switching signal R /
W ′.

The bit order switching circuit 21 is controlled by the read / write switching signal R / W ', so that the bit clock φ, like the bit order switching circuit 9 in FIG.
This bit normal address A is alternately provided every half cycle of B.
D ′ and its bit arrangement are output as a bit reverse order address obtained by inverting the upper and lower bits, and these upper 3 bits are sent to the buffer storage circuit 16 by the read / write byte address signal R / W.
AD ′, and the lower three bits are supplied to the bit selection circuit 1
7 is supplied as a bit selection address signal BS.AD '.

Buffer storage circuit 16 also has two types of areas, similarly to buffer storage circuit 5 in FIG. 1. When one area is to be written, the other area is to be read by area switching signal AS '. like,
Switching of these areas is performed.

The buffer storage circuit 16 operates similarly to the buffer storage circuit 5 in FIG.
By sequentially specifying addresses in the area designated for writing by the read / write byte address signal R / W · AD ′ from the bit normal address, the parallel data PD supplied every eight clocks of the bit clock φB
3 are sequentially written, and one block of parallel data P
In the area where D3 is stored, in accordance with the read / write byte address signal R / W · AD ′ from the bit reverse order address, this one block of parallel data is replaced by the next one block of parallel data PD3 in another area. Are repeatedly read eight times while the parallel data P
It is supplied to the bit selection circuit 17 as D4.

The bit selection circuit 17 supplies the supplied parallel data PD similarly to the bit selection circuit 6 in FIG.
For each byte of 4, the bits of the order specified by the bit selection address signal BS.AD 'from the bit reverse order address are extracted, and the output digital data DO' of one bit stream is generated. Parallel data PD4 in this case
The method of extracting bits for each byte is the same as that of the bit selection circuit 6 in FIG. 1, and as described with reference to FIG. 5, during the reading period of one block of parallel data PD4 from the buffer storage circuit 16, The order of the extracted bits in the byte is the same, but the order of the extracted bits in the byte changes each time the reading of one block is repeated.

In this way, the deinterleave device 12 has the same configuration and performs the same operation as the interleave device 1 shown in FIG.
I ′ is interleaved. Since the input digital data DI ′ is interleaved by the interleave device 1 shown in FIG. 1, the interleave by the interleave device 1 shown in FIG. 1 is performed. And the deinterleaved output digital data DO 'having the same bit arrangement as the input digital data DI in FIG.
It will be obtained from.

FIG. 9 shows the conversion of the arrangement order of bits in one bit stream by the operation of the deinterleaver 12 described above.

In the figure, the numbers in columns C and D represent the bit numbers of the input digital data DI in FIG. In this case, the 6-bit bit forward address indicates the order assigned to each bit in one block of the input digital data DI 'in FIG. This order is as shown in column C, and is the same as column B in FIG.

In each block of the input digital data DI ′, the bit arrangement order represented by the bit normal order address is converted into the arrangement order represented by the bit reverse order address. The bit arrangement order in the output digital data DO 'is as shown in column D. This bit arrangement is the same as the original input digital data DI in FIG. 1 shown in column A of FIG.

Thus, the digital data of one bit stream interleaved by interleave apparatus 1 shown in FIG. 1 is converted by deinterleave apparatus 12 in FIG. 8 which performs almost the same configuration and operation as this interleave apparatus. , Can be deinterleaved. This deinterleave device 12 differs from the interleave device shown in FIG. 1 in that the address counter circuit 8 in FIG. 1 generates a block start signal BS, whereas the address counter circuit 20 generates the block start signal BS. Only the points cleared by the BS.

FIG. 10 is a block diagram showing a specific example of a high-speed sampling 1-bit stream encoder to which the embodiment shown in FIG. 1 is applied, wherein 30 is a sampling circuit, 31 is a bit reverse interleaving circuit, and 32 is This is a data multiplexing circuit, and portions corresponding to FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description will be omitted.

In the figure, an analog audio signal S 1 input from an input terminal 101 is supplied to a sampling circuit 3.
At 0, the signal is sampled at a sampling frequency of 3072 kHz, further processed by the delta-sigma modulator 103 to become a high-speed sampling 1-bit audio stream S8, and supplied from the input terminal 2 to the bit reverse order interleave circuit 31. Further, the bit clock φB synchronized with the sampling pulse of the sampling circuit 30 is
The signal is supplied from the input terminal 3 to the bit reverse interleaving circuit 31 and also to the data multiplexing circuit 32.

The bit-reverse interleaving circuit 31 is the interleaving device 1 shown in FIG.
O and the block start signal BS are multiplexed together with the bit clock φB by the data multiplexing circuit 32 and output as a multiplexed stream S9. This multiplex stream S
8 is transmitted to the receiving side or recorded on a recording medium.

Here, a specific example of the multiplexing process in the data multiplexing circuit 32 will be described with reference to FIG.

In the figure, bit clock φB (FIG. 1)
1 (a)) and the block start signal BS (FIG. 11)
(B)) and the output digital data DO (FIG. 11 (c)) of the bit stream interleaved,
A multiplex stream S9 is obtained. As shown in FIG. 11D, the multiplex stream S9 includes a synchronization word SY for detecting synchronization, auxiliary data SD, a serial stream SS of transmission data, and various flags. It is configured. These flags include a V flag F1 indicating data reliability, a U flag F2 that can be defined by a user, and a transmission data S.
C indicating that S is a 1-bit stream of ΔΣ modulation
A flag F3 and a P flag F4 which is a parity bit.

The serial stream SS in the multiplex stream S9 is the interleaved output digital data DO from the bit order / deinterleaving circuit 31.
The auxiliary data SD indicates whether the block start signal BS indicates the start timing of the block.

As described above, the multiplexed stream having the data structure shown in FIG. 11D is synchronized with the bit clock φB, and the bit clock φB is subjected to Bi-φ modulation. ), And the bit clock φB is also multiplexed on the signal. Thus, the bit clock φB, the block start signal BS, and the output digital data DO are multiplexed and transmitted or recorded as one multiplexed stream S9. In addition, since such multiplex processing is originally required for data transmission, it does not increase the complexity of the configuration.

In this way, appropriate interleave processing can be performed on high-speed sampled 1-bit audio data with a simple configuration.

FIG. 12 is a block diagram showing a specific example of a decoder to which the embodiment shown in FIG. 8 is applied to the encoder shown in FIG.
Denotes a bit-reverse order deinterleave circuit, and portions corresponding to FIGS. 11 and 8 are denoted by the same reference numerals, and redundant description is omitted.

In the figure, a multiplex stream S9 from the encoder shown in FIG. 10 is interleaved by a data separation circuit 33 into a 1-bit stream DI ′.
(That is, the output digital data DO of the bit-reverse interleaving circuit 31 in FIG. 10), the block start signal BS, and the bit clock φB, which are supplied to the bit-reverse deinterleaving circuit 34 from the input terminals 13, 14, and 18, respectively. . The bit reverse order deinterleave circuit 34 is the deinterleave device 12 shown in FIG. 8, and the output terminal 22 outputs the deinterleaved output digital data DO 'as a high-speed sampling 1-bit audio stream. The output digital data DO 'is supplied to the decoder 111, and an analog audio signal is obtained at the output terminal 113.

In this way, deinterleaving can be performed on the interleaved high-speed sampled 1-bit audio data by a simple configuration and processing.

FIG. 13 is a diagram showing another embodiment of the interleaving method according to the present invention.

In this embodiment, the input digital data D
In order to interleave I even at a block boundary, I changes the order of change of the bit normal address before generating the bit reverse address. That is, in the embodiment shown in FIG. 1, the value of the bit-forward address generated by the address counter circuit 8 increases by one every bit clock φB. Is reduced, and the bit-reverse address is generated from the converted address.

In the interleave device 1 shown in FIG.
Assuming that the block length is 2 ⁴ = 16 bits, in the output digital data DO, as apparent from FIG. 6E, the last bit 15 of the preceding block is followed by the first bit 0 of the next block. However, this order is shown in FIG.
This is the same as the case of the input digital data DI shown in (b), and no interleaving is performed at the block boundary.

In this embodiment, this problem can be easily avoided, and FIG.
First, the input digital data DI shown in FIG. 13A is numbered for each block in correspondence with the ascending bit forward address in which the value shown in FIG. This bit-forward address is temporarily converted to a descending bit-forward address in which the value shown in FIG. Then, the bit order in descending order is inverted in the upper and lower bits of the bit arrangement in the same manner as described above, and the address is inverted as shown in FIG.
Is generated. By using such an improved bit reverse address, FIG.
As shown in the above, in the interleaved output digital data DO, in each block, the arrangement of the first bit 0 and the last bit 15 is switched, and bit 15 of the next block follows bit 15 at the block boundary. In other words, interleaving is performed at the boundary between two blocks.

FIG. 14 is a block diagram showing another embodiment of the interleave device according to the present invention for realizing such an interleave method, wherein 1 ′ is an interleave device,
9 'is a bit order switching circuit, 35 is an inverter,
Parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In this figure, the interleave device 1 'uses a bit order switching circuit 9' in which an address generator 7 is provided with an inverter 35.

That is, the read / write byte address signal R / W · AD for the write area of the buffer storage circuit 5
Is similar to the read / write byte address signal R / W.AD output from the bit order switching circuit 9 in FIG.
Although the upper three bits of the bit-forward address AD output from the address counter circuit 8 are read / write byte address signals R / W.AD for the read area, FIG.
It consists of the upper 3 bits of the improved bit reverse address described in 3 (b). The bit selection address signal BS.AD in the bit selection circuit 6 also includes the lower three bits of the improved bit reverse address.

Therefore, in the bit order switching circuit 9 ′, for the write area of the buffer storage circuit 5, the upper 3 bits of the bit normal address AD from the address counter circuit 8 are extracted to read / write data. The byte address signal R / W.AD is generated. For the read area of the buffer storage circuit 5 and the bit selection circuit 6, each bit of the bit forward address AD is set to "1", "0" by the inverter 35. 13 (b), the bit sequence is generated in the descending order, as shown in FIG. 13 (b), and then the bit arrangement is inverted to the higher and lower order to be converted to the improved bit reverse address. The upper three bits are used as a read / write byte address signal R / W · AD for the read area of the buffer storage circuit 5, and the lower three bits of the bit selection circuit 6 Bit select address signal BS / AD
And

Other operations are the same as those of the embodiment shown in FIG.

FIG. 15 shows the bit arrangement of the input digital data DI and the output digital data DO in FIG. 14. The numbers in the A and B columns are the bit numbers in the input digital data DI. The column shows the bit arrangement of the input digital data DI, and the column B shows the bit arrangement of the output digital data DO.

As is apparent from a comparison between the column B of FIG. 3 and the column B of FIG. 15, the bit in the output digital data DO in FIG. The arrangement is reversed from the bit arrangement of the output digital data DO in FIG. Thus, in this embodiment, in the input digital data DI, the last bit 63 of the preceding block is followed by the leading bit 0 of the next block, but in the output digital data DO, The last bit is bit 0, followed by bit 63 of the next block, and two bits 63 bits apart at the boundary of the two blocks. Therefore, interleaving is performed even at the block boundary.

Thus, in this embodiment, FIG.
Will be more completely interleaved.

FIG. 16 is a block diagram showing another embodiment of the deinterleave device according to the present invention for the interleave device 1 shown in FIG. 14, in which 12 'is a deinterleave device, 21' is a bit number switching circuit, and 36 Denotes an inverter, and the portions corresponding to those in FIG.

In the figure, in the address generation circuit 19, a bit order switching circuit 21 'having an inverter 36 is used instead of the bit order switching circuit 21 of the address generation circuit 7 of the deinterleave device 12 shown in FIG. ing. Other configurations and operations are the same as those of the deinterleave device 12 shown in FIG.

The bit order switching circuit 21 'has the same configuration and performs the same operation as the bit order switching circuit 9' in FIG.
2 'has the same configuration and performs the same operation as the interleaving device 1' in FIG.

However, in FIG. 16, the input digital data DI 'from the input terminal 13 to the deinterleave device 12' is the output digital data DO of FIG.
This is shown in FIG. 1 by the deinterleaver 12 '.
By performing the same processing as that of the interleave device 1 'shown in FIG. 4, the output digital data DO' having the same bit arrangement as the input digital data DI from the input terminal 2 in FIG.

FIG. 17 shows the bit arrangement of the input digital data DI 'and the output digital data DO' in FIG. 16, and the numbers in the C and D columns are the bit numbers in the input digital data DI in FIG. In the column C, the input digital data DI 'in FIG.
And the column D shows the bit arrangement of the output digital data DO '. The bit arrangement of the output digital data DO 'shown in column D of FIG. 17 is the same as the input digital data DI shown in FIG.
Is the same as the bit array.

Thus, deinterleaving apparatus 12 'shown in FIG. 16 performs the same operation with the same configuration as interleaving apparatus 1' shown in FIG.
The digital data of the 1-bit stream interleaved by the interleaver 1 ′ shown in FIG. 7 is returned to the original digital data of the bit arrangement.

Although the embodiments of the present invention have been described above, the present invention is not limited to only these embodiments.

For example, in each of the above embodiments, the input digital data DI and DI 'are converted into 1-byte digital data and stored in the buffer storage circuits 5 and 16, but the present invention is not limited to this. (= 16 bits)
For example, S / P conversion and processing may be performed in other units. In this case, if one block of the input digital data is composed of 2 ^N bits and the input digital data DI and DI ′ are converted into 2 ^M- bit digital data and the above processing is performed, the bit The forward address, the bit reverse address, and the improved bit reverse address are composed of N bits, of which the upper (NM) bits are the read / write byte address signals R / W.AD, R / R of the buffer storage circuits 5, 16. W AD '
Bit reverse order address, lower M of improved bit reverse order address
The bits become the bit selection addresses BS.AD and BS.AD 'of the bit selection circuits 6 and 17.

In addition, since the bit reverse order processing is a one-to-one data exchange and is symmetrical in input and output, the higher order (N−N) of the bit reverse order address and the improved bit reverse order address is used.
M) The bits are read / write byte address signals R / W.AD, R / W.AD 'of the buffer storage circuits 5 and 16, the bit reverse order address is used in the write area, and the lower M bits of the bit normal order address are the bits. The bit selection addresses BS • AD and BS • AD ′ of the selection circuits 6 and 17 may be used, and are almost the same as the processing in the above embodiment except that the polarity of the read / write switching signals R / W and R / W ′ is changed. is there.

[0105]

As described above, according to the present invention,
By employing a bit order switching circuit for switching between a bit forward address and a bit reverse address, it is possible to perform 1-bit interleave processing and 1-bit deinterleave processing with an address generation circuit having a simple configuration. A 1-bit digital audio reproduction circuit having a simple circuit configuration, which is expected as a next-generation digital audio device, can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of an interleaving method and apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of a procedure for generating a bit reverse order address.

FIG. 3 shows a block length of 2 in the embodiment shown in FIG.
FIG. 9 is a diagram showing a relationship between a bit normal address and a bit reverse address when ⁶ (= 64) bits are used, and a bit arrangement in input / output digital data.

FIG. 4 is a diagram schematically showing a write order and a read order in the buffer storage circuit in FIG. 1;

FIG. 5 is a diagram schematically showing an operation of the bit selection circuit in FIG. 1;

FIG. 6 shows a block length of 2 in the embodiment shown in FIG.
FIG. 11 is a diagram illustrating an interleave processing operation when ⁴ (= 16) bits are set.

FIG. 7 is a diagram showing a relationship between a bit normal address and a bit reverse address in the operation shown in FIG. 6;

FIG. 8 is a block diagram illustrating an embodiment of a deinterleaving method and apparatus according to the present invention for the embodiment illustrated in FIG. 1;

FIG. 9 shows a block length of 2 in the embodiment shown in FIG.
FIG. 9 is a diagram showing a relationship between a bit normal address and a bit reverse address when ⁶ (= 64) bits are used, and a bit arrangement in input / output digital data.

FIG. 10 is a block diagram showing a specific example of a high-speed sampling 1-bit stream encoder to which the embodiment shown in FIG. 1 is applied.

FIG. 11 is a diagram illustrating a specific example of multiplexing processing in the data multiplexing circuit in FIG. 5;

FIG. 12 is a block diagram illustrating a specific example of a decoder for the encoder illustrated in FIG. 10 to which the embodiment illustrated in FIG. 8 is applied.

FIG. 13 is a diagram illustrating another embodiment of an interleaving method according to the present invention.

FIG. 14 is a block diagram showing another embodiment of an interleaving device according to the present invention using the interleaving method shown in FIG.

15 is a block length of 2 in the embodiment shown in FIG.
FIG. 9 is a diagram showing a relationship between a bit normal address and a bit reverse address when ⁶ (= 64) bits are used, and a bit arrangement in input / output digital data.

FIG. 16 is a block diagram illustrating another embodiment of the deinterleave device according to the present invention for the interleave device illustrated in FIG. 14;

FIG. 17 shows a case where the block length in the embodiment shown in FIG.
FIG. 9 is a diagram showing a relationship between a bit normal address and a bit reverse address when ⁶ (= 64) bits are used, and a bit arrangement in input / output digital data.

FIG. 18 is a block diagram showing an example of a conventional high-speed sampling 1-bit audio encoding / decoding system.

[Explanation of symbols]

 1, 1 'interleave device 2, 3 input terminal 4 serial / parallel conversion circuit 5 buffer storage circuit 6 bit selection circuit 7 address generation circuit 8 address counter circuit 9, 9' bit order switching circuit 10, 11 output terminal 12, 12 ' Deinterleave device 13, 14 Input terminal 15 Serial / parallel conversion circuit 16 Buffer storage circuit 17 Bit selection circuit 18 Input terminal 19 Address generation circuit 20 Address counter circuit 21, 21 'Bit order switching circuit 22 Output terminal

Claims (24)

[Claims] 1. A 1-bit digital stream signal is input, and a number from 0 to (2 ^N -1) (where N is a natural number of 3 or more) is assigned to bits of the 1-bit digital stream signal in the order of input. After allocating as a sequential address, the block is divided into 2 ^N blocks, and the bit arrangement order when the bit normal address allocated to each bit in the block is represented by an N-bit binary number is ranked higher and lower. An interleaving method characterized by reordering the bits in the block in accordance with the order of bit-reversed addresses obtained by lower-order inversion to obtain an interleaved 1-bit digital stream signal. 2. The 1-bit digital stream signal interleaved by the interleave processing method according to claim 1 is input, and bits of the 1-bit digital stream signal are numbers from 0 to (2 ^N -1) in the input order. (Where N is a natural number of 3 or more) is assigned as a bit-forward address and is divided into 2 ^N blocks, and the bit-forward address assigned to each bit in the block is 2 bits of N bits. The data in the block is rearranged in accordance with the order of the bit-reversed address obtained by inverting the arrangement order of the bits when expressed in hexadecimal, in order to obtain a 1-bit digital stream signal from which interleaving has been resolved. How to deinterleave. 3. A number obtained by inputting a 1-bit digital stream signal and counting up the bits of the 1-bit digital stream signal from 0 to (2 ^N -1) in the input order (where N is 3 or more) (A natural number) is assigned as a first bit forward address, and is divided into 2 ^N blocks. Each bit of the first bit forward address assigned to each bit in the block is set to “1”. , "0" inverted (2
A second bit normal order address of an array that counts down from ^N- 1) to 0 is obtained. Further, the bit array order when the second bit normal order address is represented by an N-bit binary number is inverted to a higher order and a lower order. An interleaving method characterized by reordering the data in the block in accordance with the order of the bit-reversed addresses obtained as a result to obtain an interleaved 1-bit digital stream signal. 4. A 1-bit digital stream signal interleaved by the interleaving method according to claim 3 is input, and the bits of the 1-bit digital stream signal are counted up from 0 to (2 ^N -1) in the input order. The obtained number (where N is a natural number of 3 or more) is allocated as a first bit normal address, and then divided into 2 ^N blocks, and the first bit allocated to each bit in the block is allocated. Invert each bit of the bit forward address by “1” and “0” (2
A second bit normal order address of an array that counts down from ^N- 1) to 0 is obtained, and the bit array order when the second bit normal order address is represented by an N-bit binary number is inverted to upper and lower order. A deinterleaving method characterized in that data in the block is rearranged in accordance with the order of the obtained bit-reverse address to obtain an interleaved 1-bit digital stream signal. 5. The interleaving method according to claim 1, wherein the input 1-bit digital stream signal is 1 bit.
An interleaving method characterized by being an audio stream of bit ΔΣ modulation. 6. The deinterleaving method according to claim 2, wherein the output 1-bit digital stream signal is 1 bit.
A deinterleaving method characterized by being an audio stream of bit ΔΣ modulation. 7. A 1-bit digital stream input in 1-bit units is divided into blocks of 2 ^N bits (where N is a natural number of 3 or more), and interleaving is performed in the blocks by exchanging in 1-bit units. And an interleave device for outputting an interleaved 1-bit digital stream, comprising: buffer storage means for storing the input 1-bit digital stream; The count value is repeatedly counted from 0 to (2 ^N -1), and the count value is stored in a bit-normal order address [b (N-1), b (N-2), ..., b (1),
b (0)], and an address counter means for outputting an area switching signal for switching an access area for writing and reading in the buffer storage means; A bit reverse order address [brev (N−1), brev (N−2),...
brev (1), brev (0)] (however,
(N-1) = b (0), brev (N-2) = b
(1),..., Brev (1) = b (N−2), bre
v (0) = b (N-1)), and a bit order switching means for switching between the bit forward address and the bit reverse address when writing and reading the buffer storage means. Characteristic interleave device. 8. The 1-bit digital stream signal interleaved by the interleaving device according to claim 7, which is input and divided into blocks of 2 ^N bits (where N is a natural number of 3 or more), and A deinterleaving device for performing deinterleaving by interchanging in units of 1 bit and outputting a 1-bit digital stream signal deinterleaved from the interleaved 1-bit digital stream signal; Buffer storage means for storing a digital stream; and counting repeatedly from 0 to (2 ^N -1) in synchronization with the input 1-bit digital stream, and counting the count value in a bit-normal order address [b (N-1) , B (N−
2),..., B (1), b (0)] and outputs an area switching signal for switching an access area for writing and reading of the buffer storage means. The bit normal address is input, and the bit arrangement of the bit normal address is inverted to upper and lower bits, and the bit reverse address [brev (N−1), brev (N−2),.
brev (1), brev (0)] (however,
(N-1) = b (0), brev (N-2) = b
(1),..., Brev (1) = b (N−2), bre
v (0) = b (N-1)), and a bit order switching means for switching between the bit forward address and the bit reverse address when writing and reading the buffer storage means. Characteristic deinterleave device. 9. A 1-bit digital stream input in 1-bit units is divided into blocks of 2 ^N bits (where N is a natural number of 3 or more), and interleaving is performed in the blocks by exchanging in 1-bit units. An interleaving device for outputting an interleaved 1-bit digital stream, comprising: buffer storage means for storing the input 1-bit digital stream; and a bit clock synchronized with the input 1-bit digital stream. Input, the bit clock is repeatedly counted up from 0 to (2 ^N -1), and a read / write switching signal indicating whether a write address is output or a read address is output, An address for outputting an area switching signal for switching the access area Counter means and, bit normal order address of N bits by the count-up of the address counter means [b (N-1), b (N-
2),..., B (1), b (0)], and a bit reverse order address [brev (N−1), brev (N−
2),..., Brev (1), brev (0)] (where, brev (N−1) = b (0), brev (N−
2) = b (1),..., Brev (1) = b (N−
2), brev (0) = b (N-1)), and a bit order switching means for switching and outputting between the bit forward address and the bit reverse address in accordance with the read / write switching signal. An interleaving device characterized by the following. 10. The 1-bit digital stream signal interleaved by the interleave device according to claim 9 is input and divided as a block composed of 2 ^N bits (N is a natural number of 3 or more). What is claimed is: 1. A deinterleaving device for performing deinterleaving by interchanging in units of 1 bit and outputting a 1-bit digital stream signal deinterleaved from the interleaved 1-bit digital stream signal, wherein the input 1-bit digital stream is And a bit clock synchronized with the input 1-bit digital stream, and the bit clock is repeatedly counted up from 0 to (2 ^N -1), and the bit normal address [b ( N-1), b (N-2) , ......, b
(1), b (0)], recognizes a block boundary of the interleaving of the input 1-bit digital stream, clears the counter value, and outputs it as a write address of the buffer storage means or outputs it as a read address. Address counter means for outputting a read / write switching signal indicating whether to output as an address, an area switching signal for switching an access area of the buffer storage means by writing and reading, A bit reverse address [brev (N-1), brev (N-2),..., B
rev (1), brev (0)] (where brev (N
-1) = b (0), brev (N-2) = b (1),...
.., Brev (1) = b (N−2), brev (0) =
b (N-1)), and a bit order switching means for switching the bit forward address and the bit reverse address in accordance with the read / write switching signal. 11. A 1-bit digital stream signal input in 1-bit units is divided into blocks of 2 ^N bits (where N is a natural number of 3 or more), and the block is replaced by 1-bit units in the blocks. and interleaving, a interleaving unit for outputting the interleaved bit digital stream is, 2 is input the 1-bit digital stream signal ^M
Serial / parallel conversion means for converting into parallel data of bits (where M is a positive integer smaller than N); and buffer storage means for storing the 2 ^M- bit parallel data output from the serial / parallel conversion means. A bit clock synchronized with the input 1-bit digital stream is input, and the bit clock is repeatedly counted up from 0 to (2 ^{(N + M)} -1) (N
+ M bits), generates a block start signal every time 2 ^{(N + M)} are counted, and indicates whether a write address or a read address is output to the buffer storage means. Address counter means for outputting a read / write switching signal and an area switching signal for switching an access area of the buffer storage means; and a high-order N bit of the (N + M bits) count value is set to a bit forward address [ b (N-1), b (N-2),
.., B (1), b (0)], and the bit arrangement of the bit normal address is inverted and the upper and lower bits are inverted.
(N-2),..., Brev (1), brev (0)]
(However, brev (N-1) = b (0), brev (N
−2) = b (1),..., Brev (1) = b (N−
2), brev (0) = b (N-1)), and switches between the bit forward address and the bit reverse address in accordance with the read / write switching signal to read / write addresses of the buffer storage means. Bit order switching means for outputting as a signal; and the 2 ^M- bit parallel data output from the buffer storage means, and the lower M bits of the (N + M bits) count value output from the address counter means.
Enter the bit as a bit selection address signals, the 2 ^M
Bit selection means for selecting bits of parallel data in the order specified by the bit selection address signal, serially arranging the bits, and outputting as an interleaved 1-bit digital stream signal. 12. The 1-bit digital stream signal interleaved by the interleaving device according to claim 11, which is inputted and divided into blocks of 2 ^N bits (where N is a natural number of 3 or more), and Deinterleaving by interchanging in units of 1 bit within the 1 bit digital stream signal interleaved and 1
A deinterleave device for outputting a bit digital stream signal, comprising: a serial / parallel converter for converting the interleaved 1-bit digital stream signal into parallel data of 2 ^M bits (where M is a positive integer smaller than N). means a buffer storage means for storing the parallel data of the 2 ^M-bit output from the serial-parallel conversion means, said type the interleaved bit digital stream signal synchronized with bit clocks, the bit clocks 0 To (2 ^{(N + M)} -1) to generate a count value of (N + M bits), and input the block start signal indicating the interleave boundary of the interleaved 1-bit digital stream signal; The block start signal A read / write switching signal for clearing a counter value at the indicated interleave boundary and outputting a write address or a read address to the buffer storage means, and an area switch for switching an access area of the buffer storage means Address counter means for outputting a signal and a high-order N bits of the (N + M bits) count value as bit-forward addresses [b (N-1), b (N-2),
.., B (1), b (0)], and the bit arrangement of the bit normal address is inverted and the upper and lower bits are inverted.
(N-2),..., Brev (1), brev (0)]
(However, brev (N-1) = b (0), brev (N
−2) = b (1),..., Brev (1) = b (N−
2), brev (0) = b (N-1)), and switches between the bit forward address and the bit reverse address in accordance with the read / write switching signal to read / write addresses of the buffer storage means. Bit order switching means for outputting as a signal; and the 2 ^M- bit parallel data output from the buffer storage means, and the lower M bits of the (N + M bits) count value output from the address counter means.
Enter the bit as a bit selection address signals, the 2 ^M
Bit selecting means for selecting bits of parallel data in the order specified by the bit selection address signal, serially arranging the bits, and outputting a 1-bit digital stream signal deinterleaved from the interleaved 1-bit digital stream signal And a deinterleave device. 13. A 1-bit digital stream input in 1-bit units is divided into blocks of 2 ^N bits (where N is a natural number of 3 or more), and interleaving is performed in the blocks by exchanging in 1-bit units. the was, in an interleaved unit that outputs the interleaved bit digital stream signal, 2 is input the 1-bit digital stream signal ^M
Serial / parallel conversion means for converting into parallel data of bits (where M is a positive integer smaller than N); and buffer storage means for storing the 2 ^M- bit parallel data output from the serial / parallel conversion means. A bit clock synchronized with the input 1-bit digital stream signal is input, and the bit clock is set to 0.
To (2 ^{(N + M)} -1), and outputs a count value of (N + M) bits, outputs a block start signal every time 2 ^{(N + M)} are counted, and stores the buffer. Address counter means for outputting a read / write switching signal indicating whether to output a write address or a read address to the means, and an area switch signal for switching an access area of the buffer storage means; ) In the count value of the first bit, the first bit forward address [b (N−1), b (N−
2),..., B (1), b (0)], and inverts each bit of the first bit forward address by “1” and “0”. A bit order for generating a bit-reverse address of N bits inverted in the lower order, switching between the bit-forward address and the bit-reverse address in accordance with the read / write switching signal, and outputting the read / write address signal of the buffer storage means Switching means; and the 2 ^M- bit parallel data output from the buffer storage means, and the lower M bits of the (N + M bits) count value output from the address counter means.
Enter the bit as a bit selection address signals, the 2 ^M
Bit selection means for selecting bits of parallel data in the order specified by the bit selection address signal, serially arranging the bits, and outputting as an interleaved 1-bit digital stream signal. 14. The 1-bit digital stream signal interleaved by the interleaving device according to claim 13 is input and divided into 2 ^N blocks (where N is a natural number of 3 or more). What is claimed is: 1. A deinterleaving device for deinterleaving by interchanging in units of 1 bit and outputting a 1-bit digital stream signal obtained by deinterleaving the interleaved 1-bit digital stream signal, wherein the interleaved 1-bit digital stream is Serial / parallel conversion means for converting a signal into parallel data of 2 ^M bits (where M is a positive integer smaller than N); and storing the 2 ^M bit parallel data output from the serial / parallel conversion means Buffer storage means Enter the interleaved said 1-bit digital stream signal synchronized with bit clocks, the bit clock counts up repeatedly from 0 to ^{(2 (N + M) -1} ) (N + M) and outputs the count value of the bit Inputting the block start signal indicating the interleave boundary of the interleaved 1-bit digital stream signal, clearing the counter value at the interleave boundary indicated by the block start signal, and outputting a write address to the buffer storage means. A read / write switching signal indicating whether to output a read address is output, the data is moved to a digit higher than the counter value, and a part or all of the digit higher than the counter value is stored in the buffer storage means. And output an area switching signal to switch the access area Address counter means, inputting the upper N bits of the (N + M bits) count value as a first bit forward address, and setting each bit of the first bit forward address to "1", "0" The bit arrangement is inverted to generate an N-bit bit-reverse address obtained by reversing the bit arrangement of the upper and lower bits. A bit order switching means for outputting as a read / write address signal; a 2 ^M- bit parallel data output from the buffer storage means; and a count value of the (N + M) bits output from the address counter means Lower M of
Enter the bit as a bit selection address signals, the 2 ^M
Bit selecting means for selecting bits of parallel data in the order specified by the bit selection address signal, serially arranging the bits, and outputting a 1-bit digital stream signal deinterleaved from the interleaved 1-bit digital stream signal And a deinterleave device. 15. The interleave apparatus according to claim 7, wherein the input 1-bit digital stream signal is 1 bit.
An interleaving device characterized by being an audio stream of bit ΔΣ modulation. 16. The deinterleave device according to claim 8, wherein the output 1-bit digital stream signal is 1 bit.
A deinterleave device characterized by being a bit ΔΣ modulated audio stream. 17. The interleave device according to claim 11, wherein M is 3 or 4. 18. The deinterleave device according to claim 12, wherein M is 3 or 4. 19. The interleave device according to claim 7, 9, 11 or 13, wherein said address counter means repeatedly counts down from (2 ^N -1) to 0 instead of counting up. apparatus. 20. The deinterleave apparatus according to claim 8, wherein the address counter means counts down repeatedly from (2 ^N -1) to 0 instead of counting up. Deinterleave device. 21. The interleave apparatus according to claim 7, wherein the bit forward address is used for reading from the buffer storage means, and the bit reverse order address is used for writing to the buffer storage means. Interleave device characterized by the following. 22. The deinterleave device according to claim 8, 10, 12, or 14, wherein the bit normal order address is used for reading the buffer storage means, and the bit reverse order address is used for writing to the buffer storage means. A deinterleave device characterized by the following. 23. The data multiplexing means according to claim 9, 11 or 13, wherein said interleaved 1-bit digital stream signal, said block start signal and said bit clock are multiplexed to generate a multiplexed stream signal. An interleaving device comprising: 24. Data supplied from the interleaver according to claim 23, wherein the multiplexed stream signal is supplied, and data for separating the interleaved 1-bit digital stream signal, the block start signal, and the bit clock from the multiplexed stream signal. 15. The deinterleaving device according to claim 10, further comprising a separating unit.