JPH11204829A - Semiconductor element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid introducing crystal defects into a semiconductor layer below a selective growing mask, by constituting the selective growing mask from a separate structure disposed near a substrate. SOLUTION: A selective growing mask 150 is laid on an n-type GaN contact layer 103 surface formed on a wafer 100 with the n-type GaN contact layer 103 so as to possibly approach to the wafer 100. With the selective growing mask 150 laid on the wafer 100, an n-type GaN layer 104 and n-type Al0.1 Ga0.9 N layer 105 of 0.3 μm are grown at a wafer temp. of 1050 deg.C. Because of the selective growing mask 150 not closely contacted to the n-type GaN layer 104, it is possible to avoid introducing crystal defects into the n-type GaN layer 104 surface even due to the thermal hysteresis in the selective growth step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which can be manufactured by a simple method using a selective growth mask, and a semiconductor device manufactured using the method. About.

[0002]

2. Description of the Related Art FIG. 8 is a schematic sectional view of a nitride-based compound semiconductor light emitting device manufactured by using a conventional selective growth method. In the prior art for manufacturing this light emitting element, a GaN layer is formed on a sapphire substrate 800 as a first growth step.
The low-temperature buffer layer 801 has an n-type G of 0.01 to 0.2 μm.
The aN layer 802 is formed to a thickness of about 1 to 4 μm. Next, this n
A selective growth window region 811 is formed by forming an oxide film 810 for selective growth on the p-type GaN layer 802 and then removing a part of the oxide film 810 for selective growth by using a normal photolithography technique and an etching technique. To form Subsequently, the wafer provided with the selective growth oxide film 810 is introduced into a growth apparatus, and an n-type AlGaN cladding layer 803, a non-doped or p-type or n-type InGaN layer 804,
A p-type AlGaN cladding layer 805 and a p-type GaN cap layer 806 are selectively grown sequentially. Thereafter, the oxide film (dielectric) 810 for selective growth is removed, an n-type electrode 807 is formed on the n-type GaN layer 802, and a p-type electrode 808 is formed on the p-type GaN cap layer 806. Was prepared. Such a conventional example is disclosed in JP-A-8-255929.
No. 6,086,045.

In the above-mentioned prior art device, three lamination steps (two crystal growth steps and one selective growth oxide film 810 formation step) are required, the steps are complicated, and the cost of the element is reduced. Get higher. Further, when the selective growth oxide film 810 is formed by directly laminating the selective growth oxide film 810 on such a semiconductor crystal, the selective growth oxide film 810 is removed after the selective growth, and the exposed underlying layer is removed. N-type GaN layer 8
02 current between adjacent n-type electrodes 807 formed on the surface
When the voltage characteristics were examined, as shown in FIG. 3B, ohmic contact did not occur, and a voltage drop of about 0.8 V was observed at a current of 10 mA. Normally, when an n-type electrode having an equivalent size is formed on an equivalent n-type GaN layer that does not pass through the selective growth step, the voltage drop at a current of 10 mA should be as small as 0.15 V as shown in FIG. In comparison with, it was confirmed that the resistance was increased about five times. Further, an initial accelerated aging test at 80 ° C. and 30 mA for 12 hours was performed on the device manufactured by the above-described conventional process in a wafer state.
The resistance value between 07 further increased, as shown in FIG. 3C. In this case, the voltage drop at 10 mA current was 1.2 V, which was not negligible with respect to the voltage of the light emitting element of 3.5 V.

[0004]

In the manufacturing method to which the above conventional technique is applied, the n-type GaN layer 802
On top of that, it was necessary to form an oxide film 810 for selective growth such as SiO ₂ using a plasma CVD method or an electron beam evaporation method for the selective growth.

[0005] For this reason, the manufacturing process becomes complicated to grow a semiconductor layer using selective growth to manufacture a semiconductor device, the cost of a semiconductor light emitting device chip is high, and the manufacturing time is long. Was. Further, due to the difference in expansion coefficient between the oxide film provided for selective growth and the semiconductor, a crystal defect is introduced into the semiconductor layer below the selective growth mask due to the thermal history in the selective growth step, and as a result, the semiconductor layer is formed in the region. In addition, there is a problem that the resistance of the electrode is increased.

[0006] Regarding the increase in resistance, the underlying n-type GaN layer 802 on which the selective growth oxide film 810 was formed was formed.
A detailed examination of the crystal quality of the surface showed that 10 ¹² cm ^-2
(A crystal defect density of the n-type GaN layer 802 in a region where the selective growth oxide film 810 is not formed is about 10 ¹⁰ cm ⁻² , A 100-fold increase in defects was seen). This increase in crystal defects below the selective growth oxide film 810 is caused by the difference in the thermal expansion coefficient between the selective growth oxide film 810 and the underlying semiconductor layer (the n-type GaN layer 802 in the above-described conventional example). This is because defects were generated in the vicinity of the surface of the underlying n-type GaN layer 802 in the previous temperature raising step or the high temperature step after the selective growth. Also, this phenomenon is S
The thermal expansion coefficient difference between the selective growth oxide film 810 made of iO ₂ and GaN is as large as 5 × 10 ^−6, and when the temperature is raised to a high temperature, n
It is presumed that a large compressive stress is applied to the p-type GaN layer 802.

[0007]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and provides a method of manufacturing a semiconductor device manufactured by a simple process by selective growth capable of forming a low-resistance n-type electrode with good controllability. Is provided.

The first step of the present invention is to form a first semiconductor layer of a first conductivity type on a substrate, a second step of providing a selective growth mask on the first semiconductor layer, (1) The semiconductor layer and the selective growth mask are heated to a predetermined temperature, and a material gas is brought into contact with the substrate to selectively form a laminated structure on the substrate located in a window region of the selective growth mask. A method of manufacturing a semiconductor device, comprising: a third step of growing a body; and a fourth step of forming a first electrode on a first semiconductor layer in a region corresponding to a lower portion of the selective growth mask,
The selective growth mask is formed of a separate structure disposed close to the substrate.

In another aspect of the present invention, the selective growth mask is made of the different structure made of a metal or a semiconductor which does not soften at a predetermined temperature raised in the third step, and at least the different structure is formed. The surface other than the surface opposed to the substrate is covered with a dielectric film in which crystal growth in the third step is suppressed as compared with the surface of the substrate, wherein the third step comprises: An element having a property of exhibiting the same conductivity type as the first semiconductor layer or a metal having a property of forming an ohmic electrode with respect to the first semiconductor layer on a surface of the selective growth mask facing the first semiconductor layer; 5. The method according to claim 4, wherein an auto-doped film containing an element is formed, wherein the semiconductor element is made of a nitride-based compound semiconductor and is selectively formed in the third step. The stacked structure includes a second semiconductor layer of a second conductivity type, and after the fourth step, a second semiconductor layer formed in a portion corresponding to a window region of the selective growth mask has a second semiconductor layer. The method includes a fifth step of forming an electrode.

According to a fifth aspect of the present invention, there is provided a semiconductor device manufactured by using the manufacturing method according to the first aspect, wherein a width of a region covered with the selective growth mask to suppress crystal growth. Is 200 μm or more. According to a sixth aspect of the present invention, there is provided a semiconductor device manufactured by using the manufacturing method according to the third aspect, wherein the selective growth mask forms a part of an electrode structure. I have.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. (Embodiment 1) A manufacturing process diagram of a semiconductor light emitting device embodying the present invention is shown in FIG. Here, metal organic vapor phase epitaxy is used as a crystal growth technique, and ammonia (NH ₃ ) is used as a group V material, and trimethylgallium, trimethylaluminum, trimethylindium is used as a group III material.
Biscyclopentadienyl magnesium (Cp ₂ Mg) was used as a p-type impurity, monosilane was used as an n-type impurity, and hydrogen and nitrogen were used as carrier gases.

First, an AlN buffer layer 102 having a thickness of 50 nm was grown on a sapphire substrate 101 at a growth temperature of 550 ° C.
Then, an n-type GaN contact layer 103 is grown to a thickness of 10 μm at a growth temperature of 1050 ° C. Next, the n-type GaN
On the wafer 100 with the contact layer 103, a selective growth mask 150 is arranged on the surface of the n-type GaN contact layer 103 (FIG. 1A). Here, it is desirable that the selective growth mask 150 be as close as possible to the wafer 100, but it is not necessary to be in close contact with the wafer 100.

FIG. 2 is a structural view of the selective growth mask 150 used here observed from above. The main member of the selective growth mask 150 is a Mo plate 1 having a thickness of 0.7 mm, which is hardly deformed even at the growth temperature of the GaN crystal.
51, and the whole was covered with an Al ₂ O ₃ film 152. The shape of the selective growth window region 153 is a square 500 μm × 500.
The width of the mask region 154 between the adjacent selective growth window regions 153 was 500 μm.

Next, in the MOCVD apparatus, the temperature of the wafer 100 is set to 1050 ° C. while the selective growth mask 150 is superimposed on the wafer 100, and the n-type GaN layer 10
4 is 1 μm thick and n-type Al _0.1 Ga _0.9 N layer 105 is 0.3
The undoped In _0.3 Ga _0.7 N quantum well active layer 106 is grown to a thickness of μm and the wafer temperature is further lowered to 800 ° C.
Is grown to a thickness of 3 nm. Next, the growth temperature was again raised to 1050 ° C.
The p-type Al _0.1 Ga _0.9 N layer 107 is 0.3 μm thick.
Then, the crystal growth of the p-type GaN contact layer 108 was performed in order of 0.5 μm. This second selective growth mask 150
In the accompanying growth, main crystal growth occurred in a portion corresponding to the selective growth window region 153 of the selective growth mask 150, and as a result, a laminated structure having a shape as shown in FIG. 1B was formed.

Next, the substrate temperature was lowered to room temperature, the selective growth mask 150 was removed from the wafer 100, and the wafer was taken out of the MOCVD apparatus. Finally, FIG. 1 (c)
As shown in FIG. 3, an n-type electrode 109 for injecting current from the outside is provided on the surface of the n-type GaN contact layer 103.
After the p-type electrode 110 was formed on the p-type GaN contact layer 108, an alloy was applied at 550 ° C. for 1 minute, and finally, the device was divided and formed into chips, thereby producing a light-emitting device.

In the above steps, the formation of the dielectric film and the photolithography process as in the conventional example are unnecessary, and the steps can be simplified. Therefore, the price of the gallium nitride-based compound semiconductor light emitting device chip can be reduced, and the time for manufacturing the gallium nitride-based compound semiconductor light emitting device can be greatly reduced.

When the resistance value of the n-type electrode 109 of the device of this embodiment was measured, it was found that the n-type electrode was directly formed on the n-type GaN layer which had not been selectively grown as shown in FIG. The characteristic of D in FIG. 3 which is almost the same characteristic was obtained.
This is because, in the present invention, n-type Ga is used as a selective growth mask.
Since the selective growth mask 150 made of a separate structure that does not need to be in close contact with the N contact film 103 was used, the mask and the n-type GaN contact layer 10 in the selective growth step were used.
This is considered to be the result of achieving selective growth without generating distortion due to a difference in thermal expansion coefficient between the substrate and No. 3.

In the selective growth step, the crystal is formed under the mask region 154 in the selective growth step with respect to the distance from the end of the mask region 154 where the growth is suppressed immediately below the mask region 154 of the selective growth mask 150 of the device of this embodiment. The thickness of the wrapped and grown layer was examined. FIG. 4 is an enlarged view of an end portion of the mask region 154. In addition to the stacked structures 104 to 108 selectively grown in the selective growth window region 153, the wraparound growth layers 111 corresponding to the respective stacked structures 104 to 108 are also formed on the n-type GaN contact layer 103 in the mask region 154. You can see that. The thickness of the wraparound growth layer 111 becomes smaller as the distance from the end of the mask region 154 increases. This occurs because the edge of the mask region 154 of the selective growth mask 150 at a portion facing the wafer 100 from a right angle, or because the selective growth mask 150 and the selective growth mask 150 are not completely adhered. This is a phenomenon unique to MOCVD.

FIG. 5 shows the relationship between the distance from the end of the mask region 154 and the total thickness of the wraparound growth layer 111 grown in the selective growth step by wraparound growth. In the vicinity of the end of the mask region 154 of 50 μm, a crystal layer of 0.5 μm or more is formed by the wraparound growth.
Although formed below, one end from the end of the mask region 154
It was found that in a region separated by 00 μm or more, almost no formation of a crystal layer due to the wraparound growth was observed. This tendency is due to the selective growth conditions of MOCVD (gas pressure is in the range of atmospheric pressure to 50 torr, growth rate is 0.5 μm
/ Hour to 7 μm / hour, substrate temperature 600 ° C to 1
(In the range of 200 ° C.). Therefore, in the selective growth step, the underlying layer (in this case, n
The GaN layer 104), a layer having a conductivity type opposite to that of the GaN layer 104 (in this case, the p-type layers 107 and 108) or a structure including a high-resistance layer, or a low-resistance ohmic contact with the n-type electrode 109 In the case of forming a structure (such as a structure having a large hetero-interface) that hinders the growth, the selective growth mask 150 is formed so that at least a region at least 100 μm away from the end of the mask region 154 is included as the mask region 154. Needs to be controlled. That is,
In consideration of the wraparound growth from both sides, the selective growth region 15
The width of the mask region 154 between the three needs to be 200 μm or more. On the other hand, the width of the mask region 154 is 200
If it is not less than μm, adverse effects on the electrode due to the wraparound growth can be prevented, but if the width is not less than 1000 μm, crystals are deposited on the selective growth mask 150 in the selective growth step, and this is caused by the selective growth window. When the selective growth mask 150 is removed from the wafer 100 after the selective growth process by being connected to the semiconductor crystal layer formed on the semiconductor in the region 153, the semiconductor layer structures 104 to 108 formed in the selective growth region 153 have cracks or chips. A problem arose.
Therefore, it is understood that the width of the mask region 154 of the selective growth mask 150 should desirably be selected within a range of 200 μm or more and 1000 μm or less.

Further, as a material for the selective growth mask 150, a selective growth temperature (700 to 11 in the case of a GaN system) is used.
(00 ° C.), a material whose shape is not deformed is desirable. Specifically, in addition to Mo, Ta, W, stainless steel,
Alloy of iron and nickel, alloy of iron and nickel and cobalt,
Or a semiconductor such as Si or GaAs, or a dielectric such as sapphire. As a cover material for suppressing growth formed on the surface of the selective growth mask 150, a thermally stable dielectric film made of an amorphous material is preferable. In addition to Al ₂ O ₃ , Al ₂ O _x (X
<2), the composition is different, or SiO _y (y ≦ 2), S
Si compounds such as i ₃ N _z (z ≦ 4) can be applied.

As described above, by applying the present invention, a light-emitting element can be manufactured by simple steps, and the selective growth mask 150
To prevent an increase in the resistance value of the electrode formed in the non-selective growth region without introducing crystal defects into the surface of the n-type GaN layer 104 due to the thermal history in the selective growth step because it does not adhere to the substrate. Was completed.

(Embodiment 2) Next, a description will be given of a device according to another embodiment of the present invention. The difference from the first embodiment is that a material including an element serving as an n-type dopant is disposed in a portion of the selective growth mask member facing the wafer, so that the p-type Is to suppress the conversion. FIG. 6 shows a structural diagram of the selective growth mask 650 used for manufacturing the device of this embodiment. FIG. 6A is a top structural view, and FIG.
It is sectional drawing in A 'cross section.

The selective growth mask 650 includes a selective growth window region 653 having a 400 μm-wide stripe-shaped missing portion,
400 μm wide mask region 654 formed between them
It is composed of Also, this selective growth mask 6
Reference numeral 50 denotes a side surface and an upper surface of a mask main member 651 made of Ta, which are covered with an Al ₂ O ₃ film 652, and the lower surface of the mask is formed of a dielectric film containing Si made of a SiO _y (y = 1.5) film 655. .

In the fabrication of the device of the present embodiment, the step of forming the semiconductor layer (including the selective growth step) is the same as that of the first embodiment. Therefore, the detailed description will not be repeated here, and the description will be made using the same figure numbers as those of the first embodiment except for the parts related to the mask structure.

When the thickness of the wraparound growth layer 111 by selective growth in a portion corresponding to a portion immediately below the mask region 654 of the device manufactured in this embodiment was examined, almost the same result as in FIG. 5 was confirmed. However, in this element, when the conductivity type of these wraparound growth layers 111 was examined,
It was found that all the layers included were n-type and the p-type layer was not included.

A translucent p-type electrode 110 is formed on the surface of the stripe-shaped p-type GaN contact layer 108 in the selective growth window region 653 of the wafer thus manufactured.
An n-type electrode 109 including a wraparound growth portion is formed in a portion located below the mask region 654, and finally, at 650.degree.
Alloyed for 0 seconds. The division into elements is performed by using a mask region 654.
The individual chips are taken out by scribing at a 400 μm pitch in the direction perpendicular to the central portion of the n-type electrode 109 corresponding to
A light-emitting element was used.

In the light emitting device manufactured by the above-described method, a simple film forming process for depositing a selective growth mask layer on the surface of the wafer 100 and a photolithography or etching process for defining a selective growth region are performed without any simple steps. In the process, a light-emitting element can be manufactured so as to be selectively grown. Further, the current between the n-type electrodes 109 of this element is
When the voltage characteristics were measured, the n-type G shown in FIG.
Exactly the same characteristics as in the case of directly forming on the aN contact layer 103 were obtained, and an increase in resistance due to the adoption of the selective growth step for forming the wraparound growth layer 111 could be suppressed.

Since the Si compound composed of the SiO _y film 655 is used on the lower surface of the mask facing the wafer 100, Si is converted from the SiO _y film 655 to GaN during the selective growth.
This is presumably because Si is automatically added to the wraparound growth layer 111 having a system multilayer structure (auto doping), and this Si functions as an n-type dopant. As described above, in the case where the Si-based compound is formed at least in the lower surface layer of the selective growth mask 650, the entire area including the wraparound growth portion up to the end of the mask region 654 can be an n-type layer. When the n-type electrode 109 is formed in the element portion corresponding to the mask region 654 in which the selective growth is suppressed, the n-type ohmic electrode can be formed over the entire surface corresponding to the mask region 654, and the Resistive n-type electrode 109
Can be realized. Further, in the case of this embodiment, there is no limitation that the mask region width is required to be 200 μm or more as described in the first embodiment.
Even when the mask region 654 is narrowed to
No increase in resistance was observed.

In order to realize the auto-doping of Si with good controllability, the composition of the SiO _y film 655 under the mask 650 is such that 1.0 ≦ y ≦ 1.8, that is, Si is excessively larger than a complete Si oxide film. Doping amount in which the resistance is low and p-type doping can be compensated in a certain state: 10 ¹⁷ -1
0 ²⁰ cm ^-3 of Si can be added to the wraparound growth layer 111. Similar effects can be achieved by adding a small amount of n-type impurities other than Si, such as S, Ge, and Se, to a dielectric such as Al ₂ O _x and forming them under the mask.

The layer formed under the mask may be a single or plural metal layers containing Ti, Al, and W for forming an n-type ohmic electrode in addition to the SiO _y film. The n-type electrode 1 is formed on the low-resistance layer containing these metals which is naturally formed under the mask region 654.
09 can also be formed. Further, the layer below the mask region 654 containing these metals could be used directly as an electrode.

Further, as a mask for selective growth, FIG.
A selective growth mask 750 as shown in FIG. This mask is composed of a main member 751 made of Si, an Al ₂ O ₃ growth suppressing film 752 covering the left, right, and upper surfaces, and a Ti layer 755 and an Al layer 756 disposed on the lower surface of the mask. By bringing such a selective growth mask 750 into close contact with the n-type GaN layer 103 in the selective growth step, Ti reacts with the n-type GaN layer 103 during the selective growth,
An n-type ohmic electrode can be formed. In this case, by using a conductive Si substrate as the main member of Si, as shown in FIG. 7B, after selective growth, the selective growth mask 750 is directly fused to the wafer and the Al ₂ O on the upper surface thereof is formed. _By removing the ₃ by etching and forming the n-type electrode 109 on the exposed conductive Si substrate, the selective growth mask itself can be used as a base for the electrode, thereby further simplifying the process. Is also possible. Also, after the ohmic electrode is formed during the selective growth step as the electrode, a thermal cycle is performed by cooling after the selective growth, which has been a problem in the conventional technology.
An ohmic electrode is formed before a crystal defect is introduced into the n-type GaN layer 103. Therefore, a current-voltage characteristic between the n-type electrodes as shown in FIG. Was.

The present invention is not limited to the above embodiment, and can be applied to the following cases. (1) The crystal growth method for selective growth is other than MOCVD,
Chemical vapor deposition (CVD) such as halide vapor phase epitaxy (HVPE) using halogen compounds as metal gas
If it is the law. (2) When the selective growth pattern has another shape such as a circle or a polygon, or when the size of the selective growth pattern is different. (3) The crystal to be grown is other than GaN based, for example, AlG
aAs, InGaPAs, InGaAlP, InGaAs
sN, other III-V semiconductors, G
e, a semiconductor such as Si. (4) The case where the applied element is not a light emitting element but an electronic device that does not emit light, such as a transistor or a diode.

[0033]

As described above, by applying the present invention, a complicated process such as film formation of a selective growth mask is not required, and a crystal defect is formed in a crystal under a mask region even in a selective growth step. A light emitting device could be formed by selective growth without inducing. As a result, the cost of the device could be reduced, and an n-type electrode having a low resistance equivalent to that of an electrode formed on a normal n-type layer without performing selective growth could be formed below the mask region.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor element of Embodiment 1.

FIG. 2 is a structural diagram of a selective growth mask used in Embodiment 1.

FIG. 3 is a current-voltage characteristic of an n-type electrode.

FIG. 4 is a schematic diagram of a wraparound growth structure in a mask region.

FIG. 5 is a diagram showing the dependence of the wraparound growth layer thickness on the distance from the end of the mask region.

FIG. 6 is a structural diagram of a selective growth mask used in a second embodiment.

7A is a structural diagram of another selective growth mask in the second embodiment, and FIG. 7B is a structural diagram of a light emitting element manufactured using the selective growth mask.

FIG. 8 is a manufacturing process diagram of a semiconductor element manufactured by conventional selective growth.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 wafer 101, 800 sapphire substrate 102 AlN buffer layer 103 n-type GaN contact layer 104, 802 n-type GaN layer 105 n-type Al _0.1 Ga _0.9 N layer 106 In _0.3 Ga _0.7 N quantum well active layer 107 p-type Al _0.1 Ga _0.9 n layer 108 p-type GaN contact layer 109 n-type electrode 110 p-type electrode 111 wraparound growth layer 150,650,750 selective growth mask 151 Mo plate 152 Al ₂ O ₃ film 153,653 selective growth window region 154,654 masked area 651 Mask main member 652 Al ₂ O ₃ film 655 SiO _y (y = 1.5) film 751 Si main member 752 Al ₂ O ₃ growth suppression film 755 Ti layer 756 Al layer 801 GaN low temperature buffer layer 803 n-type AlGaN cladding layer 804 n-type InGaN layer 805 p-type A lGaN cladding layer 806 p-type GaN cap layer 807 n-type electrode 808 p-type electrode 810 oxide film for selective growth 811 window region for selective growth

Claims (6)

[Claims] A first step of forming a first semiconductor layer of a first conductivity type on a substrate; a second step of providing a selective growth mask on the first semiconductor layer; The temperature of the growth mask is raised to a predetermined temperature, and a material gas is brought into contact with the substrate, so that the substrate is positioned in a window region of the selective growth mask.
A method of manufacturing a semiconductor device, comprising: a third step of selectively growing a laminated structure; and a fourth step of forming a first electrode on a first semiconductor layer in a region corresponding to a lower portion of the selective growth mask. A method of manufacturing a semiconductor device, wherein the selective growth mask is formed of a separate structure disposed close to the substrate. 2. The method according to claim 1, wherein the selective growth mask is formed of the different structure made of a metal or a semiconductor that does not soften at a predetermined temperature raised in the third step, and faces at least the substrate of the different structure. 2. The method according to claim 1, wherein a surface other than the surface to be covered is covered with a dielectric film that suppresses crystal growth in the third step as compared with the surface on the substrate. 3. 3. In the third step, an element having a property of exhibiting the same conductivity type as that of the first semiconductor layer is provided on a surface of the selective growth mask facing the first semiconductor layer. 3. The method according to claim 2, wherein an auto-doped film including a metal element having a property of forming an ohmic electrode is formed. 4. The semiconductor device is made of a nitride-based compound semiconductor, and the laminated structure selectively formed in the third step includes a second semiconductor layer of a second conductivity type. The method according to claim 1, further comprising a fifth step of forming a second electrode on a second semiconductor layer formed in a portion corresponding to a window region of the selective growth mask after the fourth step. A method for manufacturing a semiconductor device. 5. A semiconductor device manufactured by using the manufacturing method according to claim 1, wherein a width of a region covered with the selective growth mask and in which crystal growth is suppressed is 200 μm or more. Semiconductor element. 6. A semiconductor device manufactured by using the manufacturing method according to claim 3, wherein the selective growth mask forms a part of an electrode structure.