JPH11195762A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device, in which a memory capacitor is easily and reliably formed on an upper layer of bit lines so as to suppress short-circuiting between the bit lines, and planarizing of the upper layer of the bit lines as well as further insulation between the bit lines and an upper-layer wiring can be adequately secured. SOLUTION: A silicon nitride film is formed by a CVD process on an interlayer insulating film 18 so as to cover bit lines 20, the entire surface of the silicon nitride film is anisotropically etched to be left at only sidewall faces of the bit lines 20 to thereby form widewalls 21. A contact hole 23 for formation of a storage node electrode 24 is provided between the sidewalls 21 for an adjacent pair of the bit lines 20. Even when the contact hole 23 is misaligned, the bit lines 20 can be protected by the sidewalls 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor memory device having a memory capacitor such as a DRAM.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing. Along with this, one of the important issues is how to secure a matching margin between the layers constituting the semiconductor element, and several solutions have been proposed. For example, in Japanese Unexamined Patent Application Publication No. 8-78632, in the case of a semiconductor memory having a so-called COB (Capacitor Over Bitline) structure, a storage contact hole is formed while securing a margin for a bit line and a source / drain thereunder. A technique for performing this is disclosed. Specifically, after a storage contact hole is formed in the interlayer insulating film, a silicon oxide film is formed so as to cover the surface layer of the interlayer insulating film including the inner wall surface of the storage contact hole, and the entire surface of the silicon oxide film is formed. Is anisotropically etched to leave sidewalls of the silicon oxide film so as to cover only the inner wall surfaces of the storage contact holes, thereby forming sidewalls. Here, when the storage contact hole is formed, for example, the distance between the bit line and the inner wall surface of the storage contact hole, that is, the thickness of the interlayer insulating film from the bit line to the inner wall surface is extremely thin, or extremely Even when a part is exposed from the inner wall surface, the side wall protects the bit line, thereby preventing inconvenience such as short circuit.

On the other hand, in order to advance the miniaturization and high integration of semiconductor elements, flattening of each layer is also one of the important factors.
As disclosed in Japanese Patent No. 8542, a method of forming an insulating film on a side wall of a metal wiring to reduce a step,
As disclosed in JP-A-3-138940, a technique of forming a silicon nitride film on a side wall of a metal wiring for the purpose of preventing the occurrence of overhang and the like is also disclosed in JP-A-9-153610.
As disclosed in Japanese Unexamined Patent Application Publication No. H11-260, there is a method of forming a gate electrode and a source / drain electrode at almost the same height via a side wall insulating film to achieve flattening.

[0004]

However, the technique disclosed in Japanese Patent Application Laid-Open No. 8-78632 has the following serious problems. When forming the sidewall on the inner wall surface of the storage contact hole by anisotropic etching, it is indispensable to completely remove the silicon oxide film at the bottom of the storage contact hole. In general, it is known that when performing anisotropic etching of a silicon oxide film, it is difficult to remove a silicon oxide film in a minute deep recess (groove) such as a bottom of a storage contact hole due to a so-called microloading effect. I have. Therefore, in this case, as a result of completely removing the silicon oxide film at the bottom of the storage contact hole, the silicon oxide film on the bit line is excessively reduced. As a result, the thickness of the interlayer insulating film between the bit line and the lower electrode (storage node electrode) of the memory capacitor is reduced, and the interlayer capacitance is increased. This tendency becomes remarkable as the miniaturization of the semiconductor memory progresses, and when the film thickness becomes severe, the bit line is exposed and eventually a short circuit occurs between the bit line and the storage node electrode.

Accordingly, an object of the present invention is to respond to recent demands for further miniaturization and high integration of semiconductor memories.
A memory capacitor is easily and reliably formed on the bit line so as to prevent the occurrence of a short circuit or the like between the bit line and the bit line. It is an object of the present invention to provide a semiconductor memory device and a method of manufacturing the same, which can sufficiently secure the above-mentioned conditions.

[0006]

According to the present invention, there is provided a semiconductor memory device in which an access transistor having a gate and a pair of impurity diffusion layers and a memory in which a lower electrode and an upper electrode face and are capacitively coupled to each other via a dielectric film. A semiconductor memory device including a capacitor, wherein the memory capacitor is formed at a position substantially above a bit line connected to one of the pair of impurity diffusion layers, and covers a side wall of the bit line. As described above, sidewalls made of an insulating material are formed.

In one embodiment of the semiconductor memory device of the present invention, an interlayer insulating film covering the bit line and the sidewall is formed, and the lower electrode of the memory capacitor is connected to the other of the pair of impurity diffusion layers. An opening formed in the interlayer insulating film for connection with the bit line is located near the sidewall covering at least a side wall of another bit line adjacent to the bit line.

In one embodiment of the semiconductor memory device of the present invention, a part of the side wall covering the side wall of the another bit line is exposed on the inner wall of the opening.

In one embodiment of the present invention, the sidewall is a silicon nitride film or a silicon oxynitride film.

In one embodiment of the semiconductor memory device of the present invention, a protective film is formed so as to cover a surface layer of the bit line, and the sidewall is formed on a side wall of the bit line via the protective film. Have been.

In one embodiment of the semiconductor memory device according to the present invention, a side wall surface of the bit line has a forward tapered shape.

According to the method of manufacturing a semiconductor memory device of the present invention, there is provided an access transistor having a gate and a pair of impurity diffusion layers, and a memory capacitor in which a lower electrode and an upper electrode face each other via a dielectric film and are capacitively coupled. A method of manufacturing a semiconductor memory device, wherein the memory capacitor is formed at a position substantially above a bit line connected to one of the pair of impurity diffusion layers, the first method covering the access transistor. A first step of forming an insulating film and a second step of patterning the first insulating film to form a first opening exposing a part of one surface of the pair of impurity diffusion layers A third step of patterning the bit line in a strip shape on the first insulating film so as to fill the opening, and the first step of covering the bit line.
Forming a second insulating film having a lower etching rate than the insulating film, and etching the entire surface of the second insulating film to cover the side wall of the bit line.
A fifth step of leaving the first insulating film, a sixth step of forming a third insulating film so as to cover the bit lines and the second insulating film, and patterning the third and first insulating films. Forming a second opening exposing a part of the other surface of the pair of impurity diffusion layers near at least the second insulating film covering a side wall of another bit line parallel to the bit line; A seventh step of forming; and an eighth step of forming the lower electrode of the memory capacitor on the third insulating film so as to fill the inside of the second opening.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, in the seventh step, the second hole is defined so as to be defined by a distance between the pair of adjacent bit lines. Are formed in a self-aligned manner.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the second insulating film is a silicon nitride film or a silicon oxynitride film.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, after the third step and before the fourth step, a fourth insulating film is formed so as to cover a surface layer of the bit line. Is formed, and in the fifth step, the second insulating film is left on the side wall of the bit line via the fourth insulating film.

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, in the third step, the bit line is patterned so that the side wall surface has a forward tapered shape.

[0017]

According to the present invention, a sidewall made of a silicon nitride film or a silicon oxynitride film is formed on the side wall of the bit line before the second opening (storage contact hole) is formed. The formation position of the storage contact hole is, for example, between adjacent bit lines. In this case, the diameter of the storage contact hole is substantially defined by the sidewall covering the side wall of each adjacent bit line, and a slight displacement occurs during the formation. Even if it occurs, a storage contact hole having a predetermined hole diameter is formed in a self-aligned manner by being restricted by the sidewall. That is, since the sidewall is made of a material having a low etching rate, the film thickness of the sidewall is suppressed, the insulation with the bit line is sufficiently maintained, and the desired storage node electrode having a sufficient alignment margin is secured. Is formed.

Further, after the bit lines are formed and before the above-mentioned sidewalls are formed, a fourth insulating film (protective film) is formed so as to cover each bit line, thereby affecting the bit lines. The stress is alleviated, thereby preventing the bit line from being damaged due to the strong stress.

Further, by forming the side wall surface of the bit line into a forward tapered shape, the formation area of the side wall is increased, and the alignment margin when forming the storage contact hole is further expanded. As a result, the edge becomes difficult to be exposed, and a storage node electrode in which insulation is maintained more reliably is formed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some specific embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. In the first embodiment, a semiconductor memory device includes an access transistor and a memory capacitor, and the memory capacitor is formed substantially in a layer above the bit line, so-called COB (Capacitor Over Bi-layer).
A DRAM having a (tline) structure will be exemplified, and the configuration thereof will be described together with a manufacturing method. 1 to 5 are schematic cross-sectional views showing a method of manufacturing the DRAM according to the first embodiment in the order of steps. FIG. 1A is a cross-sectional view taken along a bit line.
FIG. 4B is a cross-sectional view in a direction orthogonal to the bit lines.

First, as shown in FIG. 1, a field oxide film 13 is formed as an element isolation structure on a p-type silicon semiconductor substrate 11 by a so-called LOCOS method to define an element formation region. The field oxide film 1
Instead of 3, by the field shield element separation method,
A conductive film may be embedded in the oxide film to form a field shield element isolation structure for isolating elements by fixing a portion of the silicon semiconductor substrate immediately below to a predetermined potential with the conductive film.

Next, a thermal oxide film is formed by performing a heat treatment on the surface of the silicon semiconductor substrate 11 in the element formation region which is separated from each other by the field oxide film 13 and is relatively defined. A polycrystalline silicon film and a silicon oxide film are deposited and formed.

Next, the thermal oxide film, the polycrystalline silicon film, and the silicon oxide film are patterned by photolithography and subsequent dry etching, and the thermal oxide film, the polycrystalline silicon film, and the silicon oxide film are formed into an electrode shape in the element formation region. Leave the gate oxide film 12 and the gate electrode 15
Then, the cap insulating film 16 is patterned.

Next, after the photoresist used for patterning is removed by ashing, a silicon oxide film is deposited and formed on the entire surface including the gate electrode 15 by CVD.
The entire surface of the silicon oxide film is anisotropically etched to form a sidewall 17 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 12, the gate electrode 15, and the cap insulating film 16.

Next, using the cap insulating film 16 and the side wall 17 as a mask, an impurity is introduced into the surface region of the silicon semiconductor substrate 11 on both sides of the gate electrode 15 by ion implantation to form a pair of impurity diffusion layers 10 serving as a source / drain. To complete the access transistor having the gate electrode 15 and the pair of impurity diffusion layers 10.

Next, a polycrystalline silicon film is formed on the entire surface including the field oxide film 13 by the CVD method, and the polycrystalline silicon film is patterned by photolithography and subsequent dry etching to include the impurity diffusion layer 10. The extraction electrode 14 is formed while leaving the polycrystalline silicon film in an island shape extending between the adjacent field oxide films 13. The lead electrode 14 functions as a pad for securing a margin for matching with the impurity diffusion layer 10 when forming each of the openings (bit contact holes 19 and storage contact holes 23) described later. Note that the extraction electrode 14 is formed before the impurity diffusion layer 10 is formed, and the impurity in the extraction electrode 14 is diffused into the silicon semiconductor substrate 11 by subjecting the silicon semiconductor substrate 11 to heat treatment. May be formed.

Next, a silicon oxide film is deposited and formed on the entire surface of the silicon semiconductor substrate 11 including the field oxide film 3 by a CVD method, and a reflow process is performed to flatten the surface, thereby forming an interlayer insulating film 18. Subsequently, the interlayer insulating film 18 is patterned by photolithography and subsequent dry etching to expose a part of the surface of the extraction electrode 14 formed on one of the pair of impurity diffusion layers 10 (usually serving as a drain). A bit contact hole 19 to be formed is formed. Thereafter, a polycrystalline silicon film is deposited and formed on the interlayer insulating film 18 including the inside of the bit contact hole 19 by a CVD method, and the polycrystalline silicon film is patterned into a band shape by photolithography and subsequent dry etching, and the extraction electrode is formed. Bit line 2 connected to lower impurity diffusion layer 10 through
0 is formed. As shown in FIG. 1B, each bit line 20 is connected to a corresponding lead electrode 14 through a bit contact hole 19, and is formed in parallel at substantially equal intervals.

Next, as shown in FIG. 2, a silicon nitride film is formed on the interlayer insulating film 18 by a CVD method so as to cover the bit line 20, and the entire surface of the silicon nitride film is anisotropically etched. The side wall 21 is formed while leaving the silicon nitride film only on the side wall surface of the bit line 20. As the sidewall 21, a silicon oxynitride film may be formed instead of the silicon nitride film. Here, the extraction electrode 14 connected to the other (usually a source) of the pair of impurity diffusion layers 10 is located below the adjacent bit lines 20.

Next, as shown in FIG. 3, a silicon oxide film is formed on the interlayer insulating film 18 so as to cover the bit line 20 by CVD.
Then, an interlayer insulating film 22 is formed by deposition.

Next, as shown in FIG.
A storage contact hole for exposing a part of the surface of the extraction electrode 14 formed on the other of the pair of impurity diffusion layers 10 (usually as a source) by patterning the substrates 2 and 18 by photolithography and subsequent dry etching. 23 are formed. Here, the interlayer insulating film 22,
Since the material (silicon nitride film) of the side wall 21 has a lower etching rate than the material 18 (silicon oxide film), the distance between the side walls 21 covering the side wall surfaces of the adjacent bit lines 20 is reduced during patterning. The hole diameter of the storage contact hole 23 is defined. In this example, the separation distance, that is, the hole diameter is 0.1 μm or more.
It is about 0.15 μm. Therefore, even if a slight displacement occurs during the formation of the storage contact hole 23, only a part of the sidewall 21 is exposed from the inner wall of the storage contact hole 23, and the lower layer is pulled out by being restricted by the sidewall 21. A part of the surface of the electrode 14 can be exposed, and the storage contact hole 23 is formed in a self-aligned manner while maintaining a sufficient alignment margin.

Next, as shown in FIG. 5, a polycrystalline silicon film is deposited and formed on the entire surface of the interlayer insulating film 22 including the inside of the storage contact hole 23 by the CVD method, and this polycrystalline silicon film is subjected to photolithography and subsequent steps. The storage node electrode 24 is formed by patterning by dry etching. This storage node electrode 24
As described above, since the storage contact holes 23 are formed in a state where the thickness of the sidewalls 21 is sufficiently maintained, a positional shift occurs when the storage contact holes 23 are formed, and the sidewalls 21 are removed from the inner wall surface. Even in the case of being exposed, there is no possibility that the interlayer capacitance between the bit line 20 and the bit line 20 is increased. Furthermore, the storage node electrode 24 can be formed accurately and easily as originally designed without causing a short circuit or the like between them.

Subsequently, a three-layer structure film of a silicon oxide film / silicon nitride film / silicon oxide film and a polycrystalline silicon film are sequentially deposited by a CVD method so as to cover the storage node electrode 24, and are subjected to predetermined patterning. ONO
A film 25 and a cell plate electrode 26 are formed. here,
A storage node electrode 24, an ONO film 25, and a cell plate electrode 26;
ONO film 2 in which cell and cell plate electrode 26 are dielectric films
Thus, a memory capacitor which is opposed and capacitively coupled through the capacitor 5 is completed.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a connection hole and subsequent formation of a wiring layer, formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion Are often formed sequentially.)
Through various steps such as the above, the DRAM is completed. As an example, FIG. 6A shows the bit line 20 or the bit line 2 concerned.
0 and a lower layer wiring M which is a wiring formed of the same material at the same time.
1 and an upper layer wiring M2 are schematically shown connected via a via hole VH formed in the interlayer insulating film 31. Here, since the sidewall 21 is formed on the sidewall of the lower wiring M1 as described above, even if the via hole VH is misaligned as shown in FIG. And the lower layer wiring M1 and the upper layer wiring M2 are reliably connected without adversely affecting the lower layer.

As described above, in the first embodiment, before the storage contact hole 23 is formed, the side wall 21 made of the silicon nitride film or the silicon oxynitride film is formed on the side wall of the bit line 20. . The formation position of the storage contact hole 23 is, for example, between the adjacent bit lines 20. In this case, each of the adjacent bit lines 2
The hole diameter of the storage contact hole 23 is substantially defined by the sidewall 21 covering the side wall of the zero, and the storage contact hole 23 having a predetermined hole diameter is formed in a self-aligned manner even if a slight displacement occurs during formation. Is done. That is, since the side wall 21 is made of a material having a low etching rate, the reduction in the film thickness of the side wall 21 is suppressed, the insulation with the bit line 20 is sufficiently maintained, and a desired alignment margin is ensured. The storage node electrode 24 will be formed.

Therefore, according to the first embodiment, the occurrence of a short circuit or the like with the bit line 20 is suppressed in response to the recent demand for further miniaturization and higher integration of the DRAM. In addition, a memory capacitor can be easily and reliably formed on the upper layer of the bit line 20, and furthermore, it is possible to sufficiently flatten the upper layer of the bit line 20 and sufficiently secure insulation between the bit line 20 and a further upper layer wiring.

-Modification- A modification of the first embodiment will now be described.
The DRAM of this modified example has substantially the same configuration as that of the first embodiment, but the structure near the bit line 20 is slightly different. Hereinafter, the structure of the DRAM of this modified example will be described together with its manufacturing method. 7 and 8 are schematic cross-sectional views sequentially showing main steps of a method of manufacturing a DRAM according to this modification. FIG. 7A is a cross-sectional view taken along a bit line.
FIG. 4B is a cross-sectional view in a direction orthogonal to the bit lines. Components corresponding to those of the DRAM of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as in the first embodiment, a gate electrode 15 and a pair of impurity diffusion layers 10 serving as a source / drain are formed on a silicon semiconductor substrate 11 to complete an access transistor, and an interlayer insulating film 18 is formed. A bit line 20 is patterned on the upper surface (see FIG. 1).

Next, as shown in FIG.
A silicon oxide film is deposited to a thickness of about 30 nm on the entire surface of the interlayer insulating film 18 by a CVD method so as to cover
To form

Next, as shown in FIG. 8, the protection film 2 is formed by the CVD method so as to cover the bit line 20 with the protection film 27 interposed therebetween.
7, a silicon nitride film is formed, and the entire surface of the silicon nitride film is anisotropically etched to form a protective film 2 for each bit line 20.
The side wall 21 is formed while leaving the silicon nitride film only on the side wall surface via. As the sidewall 21, a silicon oxynitride film may be formed instead of the silicon nitride film. Here, the extraction electrode 14 connected to the other (usually a source) of the pair of impurity diffusion layers 10 is located below the adjacent bit lines 20.

Thereafter, similarly to the first embodiment, the interlayer insulating film 22, the storage contact hole 23, the storage node electrode 24, the ONO film 25, and the cell plate electrode 26 are formed.
Are completed, and the DRAM is completed through various steps of forming further interlayer insulating films and connection holes.

As described above, in the modification of the first embodiment, before the storage contact hole 23 is formed, the side wall 21 made of the silicon nitride film or the silicon oxynitride film is formed on the side wall of the bit line 20. Is done. The formation position of the storage contact hole 23 is, for example, between the adjacent bit lines 20. In this case, the hole diameter of the storage contact hole 23 is substantially defined by the sidewall 21 that covers the side wall of each adjacent bit line 20. Even if a slight displacement occurs, the storage contact hole 2 having a predetermined hole diameter is regulated by the side wall 21 and self-aligned.
3 is formed. That is, since the side wall 21 is made of a material having a low etching rate,
Thus, a desired storage node electrode 24 is formed in which the reduction of the film thickness of 1 is suppressed, the insulation from the bit line 20 is sufficiently maintained, and a sufficient alignment margin is secured.

Further, after the bit lines 20 are formed and before the above-described sidewalls 21 are formed, each bit line 20 is formed.
By forming the protective film 27 so as to cover the bit line 20, the stress applied to the bit line 20 is reduced, and the occurrence of damage or the like of the bit line 20 due to the strong stress is prevented.

Therefore, according to this modification, the bit line 2
Bit line 2 so that the occurrence of a short circuit or the like between them is suppressed.
A memory capacitor is easily and reliably formed in the upper layer of 0, and the stress that is likely to be exerted on the bit line 20 by the action of the protective film 27 is reduced. Further, in addition to this, it is possible to make the upper layer of the bit line 20 flat and sufficiently secure the insulation between the bit line 20 and the further upper layer wiring. This can be realized easily and reliably without sacrificing the cost.

(Second Embodiment) Next, the second embodiment of the present invention
An embodiment will be described. D of the second embodiment
The RAM has substantially the same configuration as that of the first embodiment, except that the shape of the bit line is slightly different. 9 to 13 are schematic cross-sectional views showing a method of manufacturing the DRAM of the second embodiment in the order of steps, in which (a) is a cross-sectional view along a bit line, and (b) is a bit line. It is sectional drawing of a direction orthogonal to FIG.

First, as shown in FIG. 9, a field oxide film 113 is formed as an element isolation structure on a p-type silicon semiconductor substrate 111 by a so-called LOCOS method to define an element formation region. Instead of the field oxide film 113, a conductive film is buried in the oxide film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed at a predetermined potential by the conductive film to perform element isolation. May be formed.

Next, a thermal oxide film is formed by performing a heat treatment on the surface of the silicon semiconductor substrate 111 in the element formation region which is separated from each other by the field oxide film 113 and is relatively defined. A polycrystalline silicon film and a silicon oxide film are deposited and formed.

Next, the thermal oxide film, the polycrystalline silicon film, and the silicon oxide film are patterned by photolithography and subsequent dry etching, and the thermal oxide film, the polycrystalline silicon film, and the silicon oxide film are formed into an electrode shape in the element formation region. Leave the gate oxide film 112 and the gate electrode 1
15 and its cap insulating film 116 are patterned.

Next, after the photoresist used for patterning is removed by ashing, a silicon oxide film is deposited and formed on the entire surface including on the gate electrode 115 by the CVD method. Etching is performed to form sidewalls 117 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 112, the gate electrode 115, and the cap insulating film 116.

Then, using the cap insulating film 116 and the side wall 117 as a mask, an impurity is introduced into the surface region of the silicon semiconductor substrate 111 on both sides of the gate electrode 115 by ion implantation to form a pair of impurity diffusion layers 110 serving as a source / drain. Is formed to complete an access transistor having a gate electrode 115 and a pair of impurity diffusion layers 110.

Next, a polycrystalline silicon film is formed on the entire surface including the field oxide film 113 by the CVD method, and the polycrystalline silicon film is patterned by photolithography and subsequent dry etching to include the impurity diffusion layer 110. The extraction electrode 114 is formed while leaving the polycrystalline silicon film in an island shape extending between the adjacent field oxide films 113. This extraction electrode 114
Functions as a pad for securing a margin for matching with the impurity diffusion layer 110 at the time of forming openings (bit contact holes 119 and storage contact holes 123) described later. The extraction electrode 114 is formed before the impurity diffusion layer 110 is formed, and a heat treatment is performed on the silicon semiconductor substrate 111 to form the extraction electrode 11.
4 may be diffused into the silicon semiconductor substrate 111 to form the impurity diffusion layer 110.

Next, a silicon oxide film is deposited and formed on the entire surface of the silicon semiconductor substrate 111 including on the field oxide film 3 by a CVD method, and the surface is flattened by performing a reflow process to form an interlayer insulating film 118. Subsequently, the interlayer insulating film 118 is patterned by photolithography and subsequent dry etching to form one of the pair of impurity diffusion layers 110 (usually, a drain).
A bit contact hole 119 exposing a part of the surface of the lead electrode 114 formed thereon is formed.

Next, a polycrystalline silicon film is deposited and formed on the interlayer insulating film 118 including the inside of the bit contact hole 119 by the CVD method, and the polycrystalline silicon film is patterned into a belt shape by photolithography and subsequent etching, and is drawn out. A bit line 120 connected to the lower impurity diffusion layer 110 via the electrode 114 is formed.
Here, as shown in FIG. 9B and the circle C therein,
The side surface of the bit line 120 along the band shape is a forward tapered shape. Therefore, during the etching of the polycrystalline silicon film, the anisotropy is slightly relaxed and some isotropic properties are imparted. In other words, this etching is a so-called anisotropic etching, but is a method having a slight isotropic ratio. Therefore, the side wall surface of the bit line 120 has a slightly gentle taper shape. Accordingly, the side wall surface of the bit line 120 is reliably covered with the sidewall 121 described later, and the upper edge of the bit line 120 is hardly exposed. In this example, it is desirable that the taper angle θ be about 60 ° to 80 ° with respect to the horizontal plane. If the taper angle θ is larger than 80 ° (80 ° <θ ≦ 90 °), the edge coverage of the bit line 120 is poor, and if it is smaller than 60 ° (0 ° <θ <60).
This is because the thickness of the bit line 120 may be too thin or the coverage of the side wall surface may be impaired. As shown in FIG. 9B, each bit line 120 is connected to a corresponding lead electrode 114 through a bit contact hole 119, and is formed in parallel at substantially equal intervals.

Next, as shown in FIG.
A silicon nitride film is formed on the interlayer insulating film 118 by CVD so as to cover 0, and the entire surface of the silicon nitride film is anisotropically etched to leave the silicon nitride film only on the side wall surface of each bit line 120. The wall 121 is formed. Here, since the side wall surface of the bit line 120 is a forward tapered surface as described above, the side wall 121 having excellent coverage of the edge of the bit line 120 is formed. As the sidewall 121, a silicon oxynitride film may be formed instead of the silicon nitride film.
Note that a lead electrode 114 connected to the other of the pair of impurity diffusion layers 110 (usually serving as a source) is located below the adjacent bit lines 120.

Next, as shown in FIG.
Then, a silicon oxide film is deposited and formed on the interlayer insulating film 118 by a CVD method so as to cover 0, thereby forming an interlayer insulating film 122.

Next, as shown in FIG.
The storage contact holes 22 and 118 are patterned by photolithography and subsequent dry etching to expose a part of the surface of the extraction electrode 114 formed on the other (usually a source) of the pair of impurity diffusion layers 110. 123 is formed. Here, since the material of the sidewall 121 (silicon nitride film) has a lower etching rate than the material of the interlayer insulating films 122 and 118 (silicon oxide film), it covers the side wall surface of the adjacent bit line 120 during patterning. Sidewall 121
The hole diameter of the storage contact hole 123 is determined by the separation distance therebetween. In this example, this separation distance,
That is, the pore diameter is set to about 0.1 μm to 0.15 μm. Therefore, even if a slight displacement occurs during the formation of the storage contact hole 123, the side wall 12
1 is only exposed from the inner wall of the storage contact hole 123, and it is possible to accurately expose a part of the surface of the lower extraction electrode 114 by being restricted by the sidewall 21. The storage contact holes 123 are formed in a self-aligned manner while keeping sufficient.

Next, as shown in FIG. 13, C is formed on the entire surface of the interlayer insulating film 122 including the inside of the storage contact hole 123.
A polycrystalline silicon film is deposited and formed by the VD method, and the polycrystalline silicon film is patterned by photolithography and subsequent dry etching to form a storage node electrode 124. The storage node electrode 124 is formed in the storage contact hole 123 while the thickness of the side wall 121 is sufficiently maintained as described above.
Is formed, the storage contact hole 1 is temporarily
Even when the side wall 121 is exposed from the inner wall surface due to displacement during the formation of the
There is no possibility that an increase in interlayer capacitance will occur between the first and second electrodes. Moreover, the storage node electrode 124 is formed accurately and easily as originally designed without short-circuiting between the two.

Subsequently, a three-layer structure film of a silicon oxide film / silicon nitride film / silicon oxide film and a polycrystalline silicon film are sequentially deposited by a CVD method so as to cover the storage node electrode 124, and are subjected to predetermined patterning. And ON
An O film 125 and a cell plate electrode 126 are formed. Here, the storage capacitor includes a storage node electrode 124, an ONO film 125, and a cell plate electrode 126. Is completed.

Thereafter, although not shown in the drawing, further formation of an interlayer insulating film, formation of a connection hole and subsequent formation of a wiring layer, and formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion Are often formed sequentially.)
Through various steps such as the above, the DRAM is completed. As an example, in FIG. 14A, the lower layer wiring M3 and the upper layer wiring M4, which are formed of the same material at the same time as the bit line 120 or the bit line 120, are connected to via holes VH formed in the interlayer insulating film 131. FIG. 1 schematically shows a state in which connection is made via a switch. Here, since the side wall 121 is formed on the tapered side wall surface of the lower wiring M3 as described above,
As shown in FIG. 14B, even if misalignment occurs in the via hole VH, the lower wiring M3 and the upper wiring M4 are protected by the side wall 121 having a large occupation area and a low etching rate without adversely affecting the lower layer. Connection with the terminal is surely established.

As described above, in the second embodiment, before the storage contact hole 123 is formed,
A side wall 121 made of a silicon nitride film or a silicon oxynitride film is formed on the side wall of the bit line 120. The formation position of the storage contact hole 123 is, for example, between the adjacent bit lines 120. In this case, the hole diameter of the storage contact hole 123 is substantially defined by the sidewall 121 covering the side wall of each adjacent bit line 120. Even if a slight displacement occurs, the storage contact hole 123 having a predetermined hole diameter is formed in a self-aligned manner while being regulated by the sidewall 121. That is, since the side wall 121 is made of a material having a low etching rate, the reduction in the thickness of the side wall 121 is suppressed, the insulation from the bit line 120 is sufficiently maintained, and a desired alignment margin is secured. Storage node electrode 124
Is formed.

Further, by forming the side wall surface of the bit line 120 into a forward tapered shape, the formation area of the side wall 121 is increased, and the alignment margin when the storage contact hole 123 is formed is further expanded.
The coverability of the edge of the upper surface is improved, so that the edge becomes difficult to be exposed, and the storage node electrode 124 with more insulated insulation is formed.

Therefore, according to the second embodiment, the occurrence of a short circuit or the like with the bit line 120 is suppressed in response to the recent demand for further miniaturization and higher integration of the DRAM. In addition, a memory capacitor can be easily and reliably formed on the upper layer of the bit line 120, and it is possible to sufficiently planarize the upper layer of the bit line 120 and sufficiently secure insulation between the bit line 120 and a further upper layer wiring.

-Modification- Here, a modification of the second embodiment will be described.
The DRAM of this modified example has substantially the same configuration as that of the second embodiment, but the structure near the bit line 120 is slightly different. Hereinafter, the structure of the DRAM of this modified example will be described together with its manufacturing method. 15 and 16 are schematic cross-sectional views sequentially showing main steps of a method of manufacturing a DRAM of this modification, in which (a) is a cross-sectional view along a bit line, and (b) is a bit line. It is sectional drawing of a direction orthogonal to FIG. Components corresponding to those of the DRAM of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as in the second embodiment, the gate electrode 115 and the source /
A pair of impurity diffusion layers 110 serving as drains are formed to complete the access transistor, and a bit line 120 is patterned on the interlayer insulating film 118 so that the side wall surface has a forward tapered shape (see FIG. 9).

Next, as shown in FIG.
A protective layer 127 is formed by depositing a silicon oxide film to a thickness of about 30 nm on the entire surface of the interlayer insulating film 118 by CVD so as to cover 20.

Next, as shown in FIG.
A silicon nitride film is formed on the protection film 127 by a CVD method so as to cover the bit lines 120 via the protection film 127, and the entire surface of the silicon nitride film is anisotropically etched.
The sidewall 121 is formed while leaving the silicon nitride film only on the side wall surface via the protective film 127. As the sidewall 121, a silicon oxynitride film may be formed instead of the silicon nitride film. here,
In the lower layer between the adjacent bit lines 120, the extraction electrode 114 connected to the other (usually, the source) of the pair of impurity diffusion layers 110 is located.

Thereafter, similarly to the second embodiment, an interlayer insulating film 122, a storage contact hole 123, a storage node electrode 124, an ONO film 125, a cell plate electrode 126, and the like are formed, and further interlayer insulating films and connections are formed. The DRAM is completed through various steps for forming holes.

As described above, in the modification of the second embodiment, before the storage contact hole 123 is formed, the side wall 121 made of the silicon nitride film or the silicon oxynitride film is formed on the side wall of the bit line 120. Is done. The storage contact hole 123 is formed, for example, between adjacent bit lines 120. In this case, the side wall 12 covering the side wall of each adjacent bit line 120 is formed.
1, the hole diameter of the storage contact hole 123 is substantially defined. Even if a slight displacement occurs during the formation, the storage contact hole 123 having a predetermined hole diameter is formed in a self-aligned manner while being regulated by the sidewall 121. That is, since the side wall 121 is made of a material having a low etching rate, the reduction in the thickness of the side wall 121 is suppressed, the insulation from the bit line 120 is sufficiently maintained, and a desired alignment margin is secured. Storage node electrode 1
24 will be formed.

Further, by forming the side wall surface of the bit line 120 into a forward tapered shape, the formation area of the side wall 121 is increased, and the margin for forming the storage contact hole 123 is further expanded.
The coverability of the edge of the upper surface is improved, so that the edge becomes difficult to be exposed, and the storage node electrode 124 with more insulated insulation is formed.

Further, after the bit lines 120 are formed and before the above-mentioned sidewalls 121 are formed, the protective film 127 is formed so as to cover each bit line 120, so that the stress applied to the bit lines 120 is reduced. As a result, the bit line 120 is prevented from being damaged due to strong stress.

Therefore, according to this modification, bit line 1
A memory capacitor is more easily and reliably formed on the bit line 120 so that the occurrence of a short circuit or the like between the bit line 120 and the bit line 1 is prevented by the protection film 127.
The stress that tends to be exerted on 20 is alleviated. In addition, the upper layer of the bit line 120 can be flattened and insulation between the bit line 120 and a further upper layer wiring can be sufficiently ensured. This can be realized easily and reliably without sacrificing the cost.

[0072]

According to the present invention, in response to recent demands for further miniaturization and high integration of semiconductor devices, bit lines are prevented from being short-circuited with bit lines. It is possible to easily and surely form a memory capacitor in the upper layer, and to sufficiently planarize the upper layer of the bit line and sufficiently insulate the bit line from the further upper layer wiring.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a method for manufacturing a DRAM according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention, following FIG. 1;

FIG. 3 is a schematic cross-sectional view showing a manufacturing method of the DRAM according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a schematic sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a schematic cross-sectional view showing a state in the vicinity of the upper layer wiring of the DRAM according to the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing main steps of a method of manufacturing a modification of the DRAM according to the first embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a main step of a method for manufacturing a modification of the DRAM according to the first embodiment of the present invention, following FIG. 7;

FIG. 9 is a schematic sectional view illustrating a method for manufacturing a DRAM according to a second embodiment of the present invention.

FIG. 10 is a schematic sectional view showing a method of manufacturing the DRAM according to the second embodiment of the present invention, following FIG. 9;

FIG. 11 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the second embodiment of the present invention, following FIG. 10;

FIG. 12 is a schematic cross-sectional view showing a manufacturing method of the DRAM according to the second embodiment of the present invention, following FIG. 11;

FIG. 13 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the second embodiment of the present invention, following FIG. 12;

FIG. 14 is a schematic cross-sectional view showing a state near an upper layer wiring of a DRAM according to a second embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view showing main steps of a method for manufacturing a modification of the DRAM according to the second embodiment of the present invention.

FIG. 16 is a schematic cross-sectional view showing a main step of a method for manufacturing a modification of the DRAM according to the second embodiment of the present invention, following FIG. 15;

[Explanation of symbols]

11, 111 Silicon semiconductor substrate 12, 112 Gate oxide film 13, 113 Field oxide film 14, 114 Extraction electrode 15, 115 Gate electrode 16, 116 Cap insulating film 17, 117 Side wall (of gate electrode) 18, 22, 31, 118, 122, 131 Interlayer insulating film 19, 119 Bit contact hole 20, 120 Bit line 21, 121 Side wall 23, 123 Storage contact hole 24, 124 Storage node electrode 25, 125 ONO film 26, 126 Cell Plate electrode 27, 127 Protective film M1, M3 Lower wiring M2, M4 Upper wiring

Claims (11)

[Claims] 1. A semiconductor memory device comprising: an access transistor having a gate and a pair of impurity diffusion layers; and a memory capacitor in which a lower electrode and an upper electrode are capacitively coupled to each other via a dielectric film. The memory capacitor is formed at a position substantially above a bit line connected to one of the pair of impurity diffusion layers, and a sidewall made of an insulating material is formed so as to cover a side wall of the bit line. A semiconductor memory device. 2. An interlayer insulating film that covers the bit line and the sidewall is formed on the interlayer insulating film to connect the lower electrode of the memory capacitor to the other of the pair of impurity diffusion layers. 2. The semiconductor memory device according to claim 1, wherein the opened hole is located near at least the side wall that covers a side wall of another bit line adjacent to the bit line. 3. The semiconductor memory device according to claim 2, wherein a part of said sidewall covering a side wall of said another bit line is exposed on an inner wall of said opening. 4. The semiconductor memory device according to claim 1, wherein said sidewall is a silicon nitride film or a silicon oxynitride film. 5. A protection film is formed so as to cover a surface layer of the bit line, and the side wall is formed on a side wall of the bit line via the protection film. ~ 4
7. The semiconductor memory device according to claim 1. 6. The bit line according to claim 1, wherein a side wall surface of the bit line has a forward tapered shape.
13. The semiconductor memory device according to item 9. 7. An access transistor having a gate and a pair of impurity diffusion layers, and a memory capacitor in which a lower electrode and an upper electrode face and are capacitively coupled to each other via a dielectric film, wherein the memory capacitor includes the pair of impurity diffusion layers. A method of manufacturing a semiconductor memory device formed at a position substantially above a bit line connected to one of impurity diffusion layers, wherein a first step of forming a first insulating film covering the access transistor is provided. A second step of patterning the first insulating film to form a first opening exposing a part of one surface of the pair of impurity diffusion layers; and filling the inside of the opening. A third step of patterning the bit line in a strip shape on the first insulating film, and a second step having a lower etching rate than the first insulating film so as to cover the bit line. Insulating film A fourth step of forming; a fifth step of etching the entire surface of the second insulating film to leave the second insulating film so as to cover a side wall of the bit line; A sixth step of forming a third insulating film so as to cover the second insulating film; and patterning the third and first insulating films to form a part of the other surface of the pair of impurity diffusion layers. Second to be exposed
Forming a hole in the vicinity of the second insulating film covering at least a side wall of another bit line parallel to the bit line; and forming the hole so as to fill the inside of the second hole. An eighth step of forming the lower electrode of the memory capacitor on a third insulating film;
And a method for manufacturing a semiconductor memory device. 8. The method according to claim 7, wherein, in the seventh step, the second opening is formed in a self-aligned manner so as to be defined by a distance between the pair of adjacent bit lines. 8. The method for manufacturing a semiconductor memory device according to item 7. 9. The method according to claim 7, wherein the second insulating film is a silicon nitride film or a silicon oxynitride film. 10. After the third step and before the fourth step, a fourth insulating film is formed so as to cover a surface layer of the bit line, and in the fifth step, the fourth insulating film is formed. 10. The method according to claim 7, wherein the second insulating film is left on a side wall of the bit line via the insulating film. 11. 11. The semiconductor memory according to claim 7, wherein, in the third step, the bit line is patterned so that a side wall surface thereof has a forward tapered shape. Device manufacturing method.