JPH11186902A - Timing extract circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing extract circuit that does not produce jitters at an output, independently of a state of an input signal and to provide the timing extract circuit that ensures high frequency stability without the use of a highly stable oscillator, even for a non-signal period of the input signal. SOLUTION: A phase comparator circuit 12 produces a lead signal or a lag signal depending on phase relation between an input signal and a feedback signal obtained from a voltage-controlled oscillator 18. A charge pump circuit 14 generates a control voltage signal fed to the voltage controlled oscillator 18. Thus, even if the input signal changes rapidly, the control voltage signal does not fluctuate much. Furthermore, even when no input signal is received, no jitter takes place in clock signals outputted from the voltage-controlled oscillator 18, since the charge pump circuit 14 holds the control voltage signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing extracting circuit, and more particularly to a timing extracting circuit for a clock signal in a digital signal transmission receiving circuit.

[0002]

2. Description of the Related Art In a transmission system based on an NRZ (None Return Zero) code generally used in digital signal transmission, a timing extraction circuit for extracting a clock signal for recognizing and reproducing a received signal because no clock signal is transmitted. Is required. FIG. 11 is a block diagram showing an example of a timing extraction circuit for transmitting a burst signal.

In FIG. 1, a differentiating circuit 70 is supplied with a burst-like NRZ code signal received from a transmission line.
The rising edge is detected to generate a differential signal, which is supplied to the phase comparator 72 as a reset pulse.
The phase comparator 72 is composed of a D-type flip-flop circuit. The differential signal supplied from the differentiating circuit 70 is supplied to a reset terminal, and the clock signal VCO / 2 is supplied from a 1/2 frequency dividing circuit 80 to a clock terminal. You.

The phase comparator 72 feeds the inverted signal Q output from the inverted signal output terminal back to the D terminal to perform 1/2 frequency division, and outputs the inverted signal from the Q terminal based on the clock signal and the differential signal. The supplied signal is supplied to a low-pass filter 74. The low-pass filter 74 suppresses a high-frequency component of the signal supplied from the phase comparator 72 and supplies the signal to the addition circuit 76.

[0005] When the NRZ code signal, which is the input signal, is in a non-signal section, the addition circuit 76 provides a reference voltage Ref for adjustment in order to secure the stability of the output frequency of the VCO (voltage controlled oscillator) 78. To the VCO. VCO78
Is a voltage-controlled oscillator whose output frequency changes according to the control voltage signal, and outputs a clock signal according to the control voltage signal supplied from the adder circuit 76 as a control voltage signal.

[0006] Digital signal transmission is based on RZ (Re
(Turn-to-Zero) code, a signal obtained by detecting an edge of the NRZ code by a differentiating circuit is an RZ code. Therefore, even in the case of the RZ code, the circuit of FIG. 11 can operate. . Note that RZ
The code is a code that places a non-magnetized interval between the codes, and the pulse width of the signal is shorter than the pulse interval. The NRZ code is a code having no non-magnetized interval between the codes, and the pulse width of the signal is equal to the pulse interval.

[0007]

However, FIG.
In the circuit of FIG. 12A, as shown in FIG. 12A, the section in which the signal of the NRZ code is alternately supplied with “1” and “0” and
As shown in (A), in a section in which the signal of the NRZ code is a no-signal, the duty of the output signal Q of the phase comparator 72 is constant and there is no change in the control voltage signal supplied to the VCO 78. Jitter does not occur in the clock signal to be generated.

However, the NRZ shown in FIG.
In the section where the code signal is supplied at random, the duty greatly changes and the control voltage signal supplied to the VCO 78 fluctuates greatly, so that a jitter occurs in the clock signal output from the VCO 78. The same applies to the case where the input signal is an RZ code signal. FIG. 12 is an example waveform diagram illustrating the operation of the timing extraction circuit when the signal of the NRZ code is received in a burst.
12B shows the output signal of the differentiating circuit 70, FIG. 12C shows the output signal of the 1/2 frequency dividing circuit 80, and FIG. 12D shows the signal output from the Q terminal of the phase comparator 72. FIG. 4 shows a waveform diagram of an example.

FIG. 13 is a waveform diagram illustrating an example of the operation of the timing extraction circuit when an NRZ code signal is not received. FIG. 13 (B) shows an output signal of the differentiating circuit 70, and FIG. 13 (C). The output signal of the 1/2 frequency divider 80,
FIG. 13D shows a waveform diagram of an example of a signal output from the Q terminal of the phase comparator 72. Further, in the non-signal section of the NRZ code signal and the RZ code signal, the VCO 78 appears to be in a self-running state, so that it is inevitable that the frequency changes due to a change in environmental temperature. Therefore, in order to ensure the stability in the non-signal section, the TCO (Temp
Erasure Compensated Oscil
Therefore, it is necessary to prepare a highly stable oscillator having a temperature compensation function such as a temperature compensation function.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a timing extraction circuit which does not cause jitter in output regardless of the state of an input signal. It is an object of the present invention to provide a timing extraction circuit that ensures high frequency stability without using a stable oscillator.

[0011]

Therefore, in order to solve the above-mentioned problems, the present invention according to claim 1 relates to a phase relationship between an RZ code signal supplied in a burst and a clock signal obtained from a VCO. A phase comparison circuit that generates a lead signal and a delay signal in response thereto, a charge pump circuit that generates a control voltage signal by a signal obtained from the phase comparison circuit,
Generating the clock output signal in accordance with the control voltage signal and supplying the clock signal to the phase comparison circuit;
Consists of CO.

Thus, the input RZ code signal and V
By generating an advance signal and a delay signal according to the phase relationship with the clock signal obtained from the CO, and generating a control voltage signal to be supplied to the VCO by the charge pump circuit, the RZ
Even if the code signal is supplied at random, the control voltage signal does not fluctuate greatly, and the control voltage signal is held even if the RZ code signal becomes non-signal.
No jitter is generated in the clock signal output from.

According to a second aspect of the present invention, in the timing extracting circuit according to the first aspect, a frequency dividing circuit for dividing the frequency of the RZ code signal supplied in a burst and supplying the divided signal to the phase comparing circuit. It is characterized by having. In this way, by having the frequency dividing circuit, even if the RZ code signal fluctuates in duty on the transmission path, for example, the signal can be frequency-divided by the frequency dividing circuit to make the pulse interval constant. Thus, even if the supplied RZ code signal fluctuates in duty, it is possible to prevent the timing extraction circuit from generating jitter.

According to a third aspect of the present invention, there is provided the timing extracting circuit according to the first or second aspect, further comprising an edge detecting circuit which detects a rise and a fall of the NRZ code signal and converts the signal into an RZ code signal. It is characterized by the following. As described above, in the timing extraction circuit according to claim 1 or 2, the edge detection circuit that detects the rise and fall of the signal of the NRZ code is provided before the phase comparison circuit. Item 2 enables input of an NRZ code signal to the timing extraction circuit.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention relating to a timing extracting circuit will be described below with reference to the drawings. FIG.
FIG. 3 is a block diagram of a first embodiment of the timing extraction circuit of the present invention. The edge detection circuit 10 shown in FIG. 1 is a circuit that detects the rise and fall of the NRZ code signal supplied from the outside, detects the rise and fall, generates a pulse signal, and outputs the pulse signal to the phase comparison circuit 12. Supply.

The phase comparison circuit 12 includes an edge detection circuit 10
A circuit for comparing the phase of the supplied pulse signal with the phase of the clock signal supplied from the VCO 18, generates a leading or lagging signal according to the phase relationship between the two signals, and supplies the signal to the charge pump circuit 14. I do. The charge pump circuit 14 is a circuit that generates a control voltage signal for the VCO 18 based on the advance or delay signal supplied from the phase comparison circuit 12, and supplies the generated control voltage signal to the low-pass filter 16. The low-pass filter 16 is
The high frequency component of the supplied control voltage signal is suppressed, and V
Supply to CO18. The VCO 18 is a voltage-controlled oscillator, and outputs a clock signal having a frequency adjusted by the control voltage signal supplied from the low-pass filter 16.

FIG. 2 is a block diagram showing an example of the edge detection circuit 10, and FIG. 3 is a waveform diagram showing an example of the operation of the edge detection circuit. The delay circuit 20 shown in FIG. 2 delays the supplied NRZ code signal shown in FIG. 3A for a predetermined period, generates a delayed signal shown in FIG. 3B, and supplies the delayed signal to the exclusive OR circuit 22. I do. The predetermined period is N
This is a quarter of the pulse period when the signal of the RZ code is an alternating pattern of “1” and “0”.

The exclusive OR circuit 22 determines whether one of the supplied NRZ code signal and the delay signal supplied from the delay circuit is "1" when the data signal rises and falls. A pulse signal having a quarter period of the NRZ code signal shown in FIG. 3C is generated. In this example, the amount of delay by the delay circuit 20 is set to １ ／ of the pulse period when the signal of the NRZ code is an “1” or “0” alternating pattern, but this is not necessarily required.

FIG. 4 is a block diagram of an example of the phase comparator 12, and FIG. 5 is a waveform diagram illustrating an example of the operation of the phase comparator. The NAND circuit 26 shown in FIG.
A signal obtained by inverting the clock signal supplied from the VCO 18 shown in FIG.
A pulse signal supplied from the edge detection circuit 10 shown in FIG. When only the pulse signal of the two supplied signals is "1", the NAND circuit 26 operates as shown in FIG.
An advance signal (up signal) "0" shown in (C) is output.

The NAND circuit 28 shown in FIG.
A clock signal supplied from the VCO and a pulse signal supplied from the edge detection circuit 10 shown in FIG. 4B are supplied, and when both of the two signals are "1", a signal of "0" is output. The output signal is inverted by the inverting circuit 30 and output as a delay signal (down signal) shown in FIG. The advance signal is effective in the section of “0”, and the delay signal is effective in the section of “1”. Note that the phase comparison circuit 1
2 operates so that both the leading signal and the lag signal are always invalid in the section where the edge detection pulse signal is "0".
The advance signal and the lag signal are not valid at the same time.

FIG. 6 is a circuit diagram showing an example of the charge pump circuit 14 and the low-pass filter circuit 16. here,
The configuration of the charge pump circuit 14 will be described. The charge pump circuit is configured around two transistors. The pnp transistor Tr1 has an emitter connected to the power supply V.
Connected to CC, a lead signal from the phase comparison circuit 12 is supplied to the base via the resistor R1. The base and the emitter are connected via a resistor R2, and the collector is connected to the collector of the transistor Tr2.

The npn transistor Tr2 has an emitter connected to the ground GND and a base supplied with a delay signal from the phase comparison circuit 12 via the resistor R3. Also,
The base and the emitter are connected via a resistor R4. The collector of the transistor Tr1 and the transistor T
The low-pass filter 16 is connected between the collectors of r2. The charge pump circuit is configured as described above.

The charge pump circuit 14 outputs a signal "".
When the delay signal becomes "1", the transistor Tr2 is turned on.When the delay signal becomes "1", the transistor Tr2 is turned on.
Is turned on, and charged when Tr2 is turned on. Therefore, when the advance signal becomes "0", V
The control voltage signal supplied to the CO 18 rises and the phase of the VCO 18 is controlled to advance the phase. When the delay signal becomes "1", the control voltage signal supplied to the VCO 18 decreases and the VCO 18 is controlled to delay the phase.

In a section where the advance signal and the delay signal are invalid, the charge pump circuit holds the control voltage signal of the VCO 18 up to that time. Further, the phase comparison circuit 12
With the configuration described above, the advance signal and the delay signal are not simultaneously effective. In FIG. 6, the low-pass filter is constituted by a lag-lead filter, but may be constituted by an active filter using an active circuit.

As described above, the pulse signal for detecting the rising and falling edges of the input NRZ code signal is generated, and the advance signal and the delay signal shown in FIGS. 5C and 5D are generated. By generating the control voltage signal to be supplied to the VCO by the charge pump circuit 14, the control voltage signal may fluctuate greatly even in a section where the signal of the NRZ code is randomly supplied as shown in FIG. In addition, since the control voltage signal is held even when the signal is not received, no jitter occurs in the clock signal output from the VCO.

FIG. 7 is a block diagram showing a timing extracting circuit according to a second embodiment of the present invention. Here, the second embodiment
After dividing the input NRZ code signal by the frequency dividing circuit 40,
It differs from the first embodiment in that it is input to the edge detection circuit 10. The operation of the edge detection circuit in the case where the frequency dividing circuit shown in FIG. FIG. 8 shows the NRZ code signal supplied to the timing extraction circuit.
In the case where the fluctuation of the duty as shown by the dotted line in (A) occurs, if the data signal is supplied to the edge detection circuit 10 as it is, the output of the edge detection circuit will be as shown in FIG.
As shown in (1), the pulse interval is not constant, and jitter occurs in the output signal of the edge detection circuit 10.

Here, when the frequency of the NRZ code signal is divided by 1/2 by the frequency dividing circuit 40, the waveform becomes as shown in FIG. 8B, and the pulse duty ratio can be kept constant at 50%. As described above, by adding the frequency dividing circuit 40, the pulse interval can be made constant, and the supplied N
Even if the duty of the RZ code signal fluctuates, for example, on the transmission path, it is possible to prevent the timing extraction circuit from generating jitter.

FIG. 9 is a block diagram showing a third embodiment of the timing extracting circuit according to the present invention. Here, the third embodiment is as follows.
The point that the input signal is the RZ code and the edge detection circuit 1
The difference from the first embodiment is that 0 is deleted. In the first and second embodiments, the NRZ code is differentiated by the edge detection circuit to generate the RZ code. In this embodiment, the input RZ code signal is directly input to the phase comparison circuit 50. It is possible.

Features such as suppression of jitter due to a change in the state of an input data signal and retention of frequency stability during an input non-signal period are the same as in the first embodiment of FIG. FIG. 10 shows a fourth example of the timing extraction circuit of the present invention.
FIG. 2 shows a block diagram of an embodiment. Here, the fourth embodiment is different from the third embodiment in that an input RZ code signal is divided by a frequency dividing circuit 58 and then input to an edge detecting circuit 50. Also in this case, similarly to the case described with reference to FIG. 9, when the fluctuation of the duty occurs in the signal of the RZ code supplied to the timing extraction circuit, the pulse interval is not constant, so that the jitter occurs in the output signal of the timing extraction circuit. However, by adding the frequency dividing circuit 58, it is possible to prevent the timing extracting circuit from generating jitter even if the input RZ code signal fluctuates in duty on the transmission path, for example.

[0030]

As described above, the present invention according to claim 1 provides:
An advance signal and a delay signal are generated in accordance with the phase relationship between the burst-supplied RZ code signal and a clock signal obtained from the VCO, and a charge pump circuit generates a control voltage signal to be supplied to the VCO.

Therefore, even if the RZ code signal is supplied at random, the control voltage signal does not fluctuate greatly, and the control voltage signal is held even if the RZ code signal is not received. Therefore, no jitter occurs in the clock signal output from the VCO. Claim 2
According to the invention described above, by including the frequency dividing circuit, even if the duty of the RZ code signal fluctuates, the pulse interval can be made constant by dividing the frequency of the signal by the frequency dividing circuit.

Therefore, even if the supplied RZ code signal fluctuates in duty, it is possible to prevent occurrence of jitter in the timing extraction circuit. According to a third aspect of the present invention, in the timing extraction circuit according to the first or second aspect, the rising and falling edges of the NRZ code signal are detected and converted to the RZ code signal before the phase comparison circuit. Edge detection circuit.

Therefore, it is possible to input the RZ code signal converted from the NRZ code signal to the timing extraction circuit according to claim 1 or 2.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a timing extraction circuit according to the present invention.

FIG. 2 is a block diagram illustrating an example of an edge detection circuit;

FIG. 3 is a waveform diagram illustrating an example of an operation of the edge detection circuit.

FIG. 4 is a block diagram illustrating an example of a phase comparison circuit.

FIG. 5 is an example waveform diagram illustrating an operation of the phase comparison circuit.

FIG. 6 is a circuit diagram of an example of a charge pump circuit and a low-pass filter circuit.

FIG. 7 is a block diagram of a second embodiment of the timing extraction circuit of the present invention.

FIG. 8 is a waveform diagram illustrating an example of an operation of the edge detection circuit in a case where a frequency dividing circuit is provided.

FIG. 9 is a block diagram of a third embodiment of the timing extraction circuit of the present invention.

FIG. 10 is a block diagram of a fourth embodiment of the timing extraction circuit of the present invention.

FIG. 11 is a block diagram illustrating an example of a timing detection circuit.

FIG. 12 is a waveform diagram illustrating an example of an operation of the timing extraction circuit when an NRZ code signal is received in a burst.

FIG. 13 is a waveform diagram illustrating an example of an operation of the timing extraction circuit when a signal of the NRZ code is not received.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Edge detection circuit 12 Phase comparison circuit 14 Charge pump circuit 16 Low-pass filter 18 VCO 20 Delay circuit 22 Exclusive OR 24 Inversion circuit 26 NAND circuit 28 NAND circuit 30 Inversion circuit 40 Divider circuit 50 Phase comparison circuit 52 Charge pump circuit 54 Low-pass filter 56 VCO 58 Divider circuit

Claims (3)

[Claims] A phase comparison circuit for generating an advance signal and a delay signal in accordance with a phase relationship between an RZ code signal supplied in a burst and a clock signal obtained from a voltage controlled oscillator; A charge pump circuit that generates a control voltage signal according to the obtained signal; and the clock signal is generated according to the control voltage signal.
A timing extraction circuit comprising a voltage controlled oscillator that supplies the clock signal to the phase comparison circuit. 2. The timing extraction circuit according to claim 1, further comprising a frequency divider for dividing the RZ code signal supplied in a burst form and supplying the divided signal to the phase comparison circuit. circuit. 3. The timing extraction circuit according to claim 1, further comprising an edge detection circuit that detects a rising edge and a falling edge of an NRZ code signal and converts the signal into an RZ code signal. .