JPH11185474A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a degree of integration by storing data in a pair of driver transistors comprising bulk transistors, connecting a drain region of a first transistor to an input output node and a gate electrode of a second transistor and connecting a drain region of the second transistor to a gate electrode of the first transistor and one end of a load element. SOLUTION: When a memory cell MC is not selected, a word line WLi is at a low level and a bit line BLj is turned to a source potential because of a load element Q4. An off resistance of a driver transistor Q1 is sufficiently larger than a resistance value of a resistor R1, and therefore a potential of a node N2 is sufficiently higher than a threshold value Vt of a driver transistor Q2, making the driver transistor Q2 maintained in an on state. While a memory node N1 is kept at a high level, the word line WLi is at the low level and the driver transistor Q1 is kept on and the transistor Q2 is kept off, thus enabling a constitution of a four-element memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a static random access memory device, and provides a static random access memory device having a high degree of integration.

[0002]

2. Description of the Related Art In general, a static random access memory (SRAM) is used in various electric devices such as a computer, and as the functions of those devices are improved, the static random access memory (SRAM) is used. There is an increasing demand for low power consumption and high integration.

FIG. 2 is a block diagram of a conventional SRAM disclosed in Japanese Patent Application Laid-Open No. 5-198183. Referring to FIG. 2, this SRAM 1a includes a row address signal RA0.
To RAm, a column address buffer 4 receiving column address signals CA0 to CAn,
A row decoder 5 for decoding a row address signal and selectively activating a word line, a column decoder 6 for decoding a column address signal and selecting a bit line, and a word for boosting the potential of the activated word line And a line boosting circuit 7. A large number of memory cells MC are arranged in rows and columns on a semiconductor substrate to form a memory array 8. The memory cells arranged in one column correspond to one corresponding bit line BL.
, BL2,... Are connected to the Y gate circuit 10. The memory cells arranged in one row have the corresponding 1
Are connected to the word line booster circuit 7 via the word lines WL1, WL2,.

The bit lines BL1, BL2,... Are connected to a sense amplifier 9 via a Y gate circuit 10 and an IO line 14. Y gate circuit 10 responds to a column selection signal output from column decoder 6 to store bit lines BL1, BL2,
Are selectively connected to the IO line 14. Sense amplifier 9 is activated in response to a write enable signal / WE applied via input buffer 13.
Therefore, the data signal read from the memory cell is amplified by the sense amplifier 9 and then output as the output data signal Do via the output buffer 12. On the other hand, an input data signal Di to be written is given to a memory cell via an input buffer 11, an IO line 14, and a Y gate circuit 10.

FIG. 3 shows one memory cell M shown in FIG.
It is a circuit diagram of C. Referring to FIG. 3, memory cell MC
Includes N-channel MOS transistors Q1 and Q2 as driver transistors, resistors R1 and R2 as loads, and an N-channel MOS transistor Q3 as an access gate transistor. Transistor Q1
And the resistor R1 constitute one inverter, while the transistor Q2 and the resistor R2 constitute another inverter. Therefore, a data storage circuit is constituted by the two cross-coupled inverters. Common node N1 between transistor Q2 and resistor R2
Constitute a single input / output node of the data storage circuit.
Transistor Q3 is connected between node N1 and bit line BLj, and operates in response to a signal on word line WLi. Access gate transistor Q3 receives a word line signal boosted by word line boosting circuit 7 via word line WLi.

One end of bit line BLj is connected to power supply potential V via bit line load P-channel MOS transistor Q4.
Connected to DD. The other end of bit line BLj is connected to IO line 14 via N-channel MOS transistor Q7 forming Y gate circuit 10 shown in FIG. Transistor Q7 operates in response to a column selection signal Yj output from column decoder 6.

The sources of driver transistors Q1 and Q2 are connected to ground potential GND. The other ends of the resistors R1 and R2 are connected to the power supply potential VDD.

FIG. 3 shows only one memory cell MC, but other memory cells have similar circuit connections. In particular, memory cells provided in one column are commonly connected to a single bit line BLj.

Next, the operation of the memory cell circuit will be described.

First, in a write operation, a word line WLi in a row selected by a row address signal RAw for writing has a high potential boosted by the word line booster circuit 7 shown in FIG. On the other hand, the bit line BLj selected by the column address signal CAw for writing has a high potential or a low potential based on the data signal Di to be written. Therefore, access gate transistor Q3 turns on strongly (that is, turns on with a lower resistance), and the data signal on bit line BLj is supplied to the data storage circuit via input / output node N1.
The state of the data storage circuit is determined based on a given data signal.

On the other hand, in the read operation, the word line WLi selected by the row address signal RAr for reading is brought to a high potential. Therefore, access gate transistor Q3 is turned on, so that bit line BL
The potential of j changes slightly. In response to the column address signal CAR for reading, the column decoder 6 applies a high-potential column selection signal Yj to the gate of the transistor Q7, so that the transistor Q7 is turned on. Therefore, the potential change appearing on bit line BLj is applied to sense amplifier 9 shown in FIG. 2 via transistor Q7 and IO line 14. The data signal amplified by the sense amplifier 9 is output via the output buffer 12 as an output data signal Do.

[0012]

The conventional memory cell MC shown in FIG. 3 has five elements (Q1, Q2, Q3, R
1, R2), and therefore, forming these five elements requires a large area on the semiconductor substrate. In particular, since an N-channel MOS transistor Q3 is required as an access gate transistor, an area on the substrate is occupied to form it. In addition, the high resistances represented by the resistances R1 and R2 are formed of polysilicon resistances, and have been obstacles for increasing the degree of integration.

The present invention has been made to solve such a conventional problem.

[0014]

A semiconductor memory device according to a first aspect of the present invention includes a plurality of memory cells formed on a semiconductor substrate, and word lines and bit lines connected to the memory cells. In the semiconductor memory device, each of the memory cells has a single input / output node, data storage means for storing a data signal provided via the input / output node, a bit line of a corresponding column, and A single switching means connected between the data storage means and a node and turned on in response to a row address signal;
A driver transistor comprising a pair of bulk transistors formed on the semiconductor substrate, wherein a drain region of a first transistor among the driver transistors is a second transistor among the input / output node and the driver transistor The drain region of the second transistor is connected to the gate electrode of the first transistor and one end of the load element, and the source regions of the first and second transistors are connected to one power supply. And the other end of the load element is connected to the other power supply line.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells formed on a semiconductor substrate;
In a semiconductor memory device provided with a word line and a bit line connected to the memory cell, each of the memory cells has a single input / output node and stores a data signal provided through the input / output node. Data storage means, and a single switching means connected between a bit line of a corresponding column and the input / output node and turned on in response to a row address signal. An inverter including a channel transistor and a first N-channel transistor including a bulk transistor formed on the semiconductor substrate; and a second inverter including a bulk transistor.
The input / output node is connected to the input of the inverter and the drain region of the second N-channel transistor, and the output of the inverter is connected to the gate electrode of the second N-channel transistor. And the source regions of the first and second N-channel transistors are connected to one power supply line,
The source region of the P-channel transistor is connected to the other power supply line.

Further, according to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the bit line is precharged to a power supply voltage in a standby state or a non-selected state. A high level of the input / output node is maintained by a leakage current of the switching means.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the first, second, or third aspect, the switching means is constituted by a thin film transistor, and is stacked above the bulk transistor. It is characterized by being performed.

According to a fifth aspect of the present invention, there is provided a semiconductor memory device according to the first aspect.
The load element may be constituted by a thin film transistor stacked above the bulk transistor.

Further, according to a sixth aspect of the present invention, in the semiconductor memory device according to the second aspect,
The P-channel transistor is constituted by a thin-film transistor stacked above the bulk transistor.

By activating the word line to turn on the single switching means and applying one power supply voltage to the bit line, one of the pair of driver transistors of the data storage means is turned on, and the other is turned on. Is turned off to write data to the data storage means. Further, by precharging the bit line, activating the word line and turning on the single switching means, the data of the data storage means is read out to the bit line as a potential difference. Further, in a standby state or a non-selected state, the bit line is precharged to a power supply voltage, and a high level of the input / output node is maintained by a leakage current of the switching means.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an SRA according to an embodiment of the present invention.
3 is a circuit configuration diagram of a memory cell at M. FIG.

In the figure, Q1 and Q2 denote a pair of driver transistors (N-channel MOS) constituting the memory cell MC.
Transistor), and is configured as a bulk transistor in a semiconductor substrate. Q3 is an access gate transistor (N-channel MOS transistor),
Above the bulk transistor (eg, transistor Q2
Is formed as a thin film transistor (TFT). The resistor R1 functions as a load for the driver transistor Q1. The source regions of the driver transistors Q1 and Q2 are connected to the ground potential GND, and the other end of the resistor R1 is connected to the power supply potential (VDD). The data signal is stored as a voltage at storage node N1, and the input data is supplied as a voltage to bit line BLj. Note that the resistor R1 is made of polysilicon and may be stacked above the bulk transistor (for example, above the transistor Q1), or may be formed of a thin film transistor and stacked above the bulk transistor.

One end of bit line BLj is connected to power supply potential V via bit line load P-channel MOS transistor Q4.
Connected to DD. The other end of bit line BLj is connected to IO line 14 via N-channel MOS transistor Q7 forming Y gate circuit 10 shown in FIG. Transistor Q7 operates in response to a column selection signal Yj output from column decoder 6. Access gate transistor Q3 receives a word line signal boosted by word line boosting circuit 7 via word line WLi. Although the word line voltage is boosted in the present embodiment, the present invention is not limited to this, and the word line voltage may be the power supply voltage VDD.

FIG. 1 shows only one memory cell MC, but other memory cells have similar circuit connections. In particular, memory cells provided in one column are commonly connected to a single bit line BLj.

Next, the operation of the SRAM of this embodiment will be described.

First, consider a state in which a low level is held in storage node N1 of memory cell MC. Memory cell M
When C is not selected, the word line WLi is at a low level, and the load element Q4 causes the bit line BLj to be at the power supply potential. Since the word line WLi is at a low level, the resistance of the access gate transistor Q3 is sufficiently large and is sufficiently larger than the on-resistance of the driver transistor Q2 in the on-state.
, The driver transistor Q1 maintains the off state. Driver transistor Q
Since the off resistance of 1 is sufficiently larger than the resistance value of the resistor R1, the potential of the node N2 becomes sufficiently higher than the threshold voltage Vt of the driver transistor Q2, and the driver transistor Q2 maintains the on state.

In the state where the storage node N1 of the memory cell MC holds the high level, the word line WLi is at the low level, the bit line BLj is at the power supply potential, and the off resistance of the driver transistor Q2 in the off state is , Is sufficiently larger than the off resistance of access gate transistor Q3, so that the potential of storage node N1 becomes lower than that of driver transistor Q3.
1 and becomes sufficiently higher than the threshold voltage Vt of 1, so that the driver transistor Q1 keeps the ON state. Since the on-resistance of driver transistor Q1 is sufficiently smaller than the resistance value of resistor R1, the potential of node N2 becomes sufficiently lower than threshold voltage Vt of driver transistor Q2, and driver transistor Q2 maintains the off state.

The voltage of the storage node N1 holding the high level tends to decrease due to the leak current of the driver transistor Q2, but the bit line BLj in which the sub-threshold leak current of the access gate transistor Q3 is at the power supply potential. Is supplied so that a high level can be maintained from the high level.

At present, the ratio of the on-state internal resistance to the off-state internal resistance of an N-type bulk transistor having a channel length of 0.8 to 1 μm and a channel width of 2 to 3 μm is 1: 1 × 10
It will be about ⁹ . The leakage current of the storage node N1 of the memory cell in which the bulk transistor is configured as a driver transistor is about several pA. By comparison,
The ratio between the on-state internal resistance and the off-state internal resistance of the current thin film transistor is about 1: 1 × 10 ⁶ . Therefore, a thin film transistor is used as the access gate transistor Q3, and the current supply capability in the ON state is 1
If it is set to about 00 to 150 μA, the sub-threshold leakage current at the time of OFF becomes about 100 to 150 pA, which exceeds the leakage current of storage node N1, and can keep storage node N1 at a high level.

When data is read from a state where the low level is held in the storage node N1, the bit line BLj
Is precharged to the potential of Vcc and the word line WLi goes high, the access gate transistor Q3 conducts, and a current flows through the path between the access gate transistor Q3 and the driver transistor Q2. This current causes the potential of the bit line BLj to slightly decrease. In response to a column address signal for reading, the column decoder 6
Supplies a high-level column selection signal Yj to the gate of the transistor Q7, so that the transistor Q7 is turned on. Therefore, the potential change appearing on bit line BLj is applied to sense amplifier 9 shown in FIG. 2 via transistor Q7 and IO line 14. The data signal amplified by the sense amplifier 9 is output as output data “0” via the output buffer 12.

When data is read from a state where the high level is held in the storage node N1, no current flows through the path between the access gate transistor Q3 and the driver transistor Q2, so that the potential of the bit line BLj does not change. Therefore, the data signal amplified by the sense amplifier 9 is inverted with respect to the state where the low level is held in the storage node N1, and is output as output data "1".

When data "1" is written to the memory cell MC, that is, when a high level is written to the storage node N1, when the power supply potential (VDD) is supplied to the bit line BLj and the word line WLi becomes a high level, The resistance of access gate transistor Q3 is sufficiently reduced, and a high level is written to storage node N1. This high level potential is
Since the threshold voltage Vt of the driver transistor Q1 is sufficiently higher, the driver transistor Q1 is turned on. Since the on-resistance of the driver transistor Q1 is sufficiently smaller than the resistance value of the resistor R1, the potential of the node N2 becomes equal to the threshold voltage of the driver transistor Q2. Since the voltage is sufficiently lower than Vt, driver transistor Q2 is turned off.

When data "0" is written to the memory cell MC, that is, when a low level is written to the storage node N1, a ground potential is supplied to the bit line BLj, and when the word line WLi goes to a high level, the access gate transistor The resistance of Q3 drops sufficiently, and a low level is written to storage node N1. Since this low-level potential is sufficiently lower than the threshold voltage Vt of the driver transistor Q1, the driver transistor Q1 is turned off, and the off resistance of the driver transistor Q1 is sufficiently larger than the resistance value of the resistor R1, so that the potential of the node N2 becomes Since the voltage is sufficiently higher than the threshold voltage Vt of the driver transistor Q2, the driver transistor Q2 is turned on.

Next, consider the case where, when this memory cell MC is not selected, the opposite data is written to another memory cell connected to the same bit line BLj. As described above, when the bit line BLj goes low, the high level of the storage node N1 starts to drop due to the sub-threshold leakage of the access gate transistor Q3 formed by a thin film transistor. As previously mentioned,
The sub-threshold leakage current of the thin-film transistor Q3 is set to about 100 pA, and the parasitic capacitance of the storage node N1 is set to 1
If it is about 0 fF, it takes about 10 ⁴ seconds until the voltage of the storage node N1 drops by 1V. Therefore, the high-level storage node N1 of the non-selected memory cell MC can hold the data "1" without being substantially affected by the shift of the bit line BLj to the low level. Conversely, even when the bit line BLj goes high when the storage node N1 is low, the off resistance of the access gate transistor Q3 formed of a thin film transistor is sufficiently larger than the on resistance of the driver transistor Q2. N1 does not transition from low to high.

FIG. 4 shows an SR according to another embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a memory cell in AM.

In the figure, Q1, Q2, and Q5 are driver transistors constituting the memory cell MC. Among them, Q1 and Q2 are formed as N-channel bulk transistors in a semiconductor substrate, and Q5 is It is configured as a P-channel bulk transistor in a semiconductor substrate. Q3 is an access gate transistor, and is configured as a thin film transistor (TFT) above the bulk transistor (for example, above the transistor Q2). The P-channel bulk transistor Q5 is a P-channel thin film transistor (TF) stacked above the bulk transistor (for example, above the transistor Q1).
T). The sources of the driver transistors Q1 and Q2 are connected to the ground potential. The source of the driver transistor Q5 is connected to the power supply potential. The data signal is stored as a voltage at storage node N1, and input data is supplied as a voltage to bit line BLj. The storage node N1 is connected to the input of an inverter composed of an N-channel transistor Q1 and a P-channel transistor Q5 connected in series.
Connected to the respective gates of transistors Q1 and Q5. An output node N2 of the inverter is connected to the gate of an N-channel transistor Q2.
Is connected to storage node N1.

The bit line BLj, the bit line load P-channel transistor Q4, the word line WLi, the word line boosting circuit 7, the MOS transistor Q7 forming the Y gate circuit,
The IO line 14, the column decoder 6, and the column selection signal Yj output from the column decoder 6 are the same as those in FIG.
That is, one end of the bit line BLj is connected to the bit line load P
Power supply potential VD via channel MOS transistor Q4
D is connected. The other end of bit line BLj is connected to IO line 14 via N-channel MOS transistor Q7 forming Y gate circuit 10 shown in FIG. Transistor Q7 operates in response to a column selection signal Yj output from column decoder 6. Access gate transistor Q3 is connected to word line booster circuit 7 via word line WLi.
Receives the word line signal which has been boosted. Although the word line voltage is boosted in the present embodiment, the present invention is not limited to this, and the word line voltage may be the power supply voltage VDD.

FIG. 4 shows only one memory cell MC, but other memory cells have similar circuit connections. In particular, memory cells provided in one column are commonly connected to a single bit line BLj.

Next, the operation of the SRAM of this embodiment will be described.

First, consider a state in which a low level is held in storage node N1 of memory cell MC. Memory cell M
When C is not selected, the word line WLi is at a low level, and the load element Q4 causes the bit line BLj to be at the power supply potential. Since the word line WLi is at a low level, the resistance of the access gate transistor Q3 is sufficiently large and is sufficiently larger than the on-resistance of the driver transistor Q2 in the on-state.
Becomes sufficiently lower than the threshold voltage Vt, the driver transistor Q1 maintains the off state, and the driver transistor Q5
Maintain the ON state. Therefore, the potential of node N2 becomes sufficiently higher than threshold voltage Vt of driver transistor Q2, and driver transistor Q2 maintains the on state.

When a high level is held at the storage node N1 of the memory cell MC, the word line WLi is at a low level, the bit line BLj is at the power supply potential, and the off resistance of the driver transistor Q2 in the off state is , Is sufficiently larger than the off resistance of access gate transistor Q3, so that the potential of storage node N1 becomes lower than that of driver transistor Q3.
1 becomes sufficiently higher than the threshold voltage Vt, the driver transistor Q1 maintains the on state, and the driver transistor Q1
5 maintains the off state. Therefore, the potential of node N2 becomes sufficiently lower than threshold voltage Vt of driver transistor Q2, and driver transistor Q2 maintains the off state.

The voltage of the storage node N1 holding the high level tends to decrease due to the leak current of the driver transistor Q2, but the bit line BLj having the sub-threshold leak current of the access gate transistor Q3 at the power supply potential. Is supplied so that a high level can be maintained from the high level.

At present, the ratio of the on-state internal resistance to the off-state internal resistance of an N-type bulk transistor having a channel length of 0.8 to 1 μm and a channel width of 2 to 3 μm is 1: 1 × 10
It will be about ⁹ . The leakage current of the storage node N1 of the memory cell in which the bulk transistor is configured as a driver transistor is about several pA. By comparison,
The ratio between the on-state internal resistance and the off-state internal resistance of the current thin film transistor is about 1: 1 × 10 ⁶ . Therefore, a thin film transistor is used as the access gate transistor Q3, and the current supply capability in the ON state is 1
If it is set to about 00 to 150 μA, the sub-threshold leakage current at the time of off becomes about 100 to 150 pA, which exceeds the leakage current of the storage node N1, and can keep the storage node N1 at a high level.

When data is read from a state where the low level is held in the storage node N1, the bit line BLj
Is precharged to the potential of Vcc and the word line WLi goes high, the access gate transistor Q3 conducts, and a current flows through the path between the access gate transistor Q3 and the driver transistor Q2. This current causes the potential of the bit line BLj to slightly decrease. In response to a column address signal for reading, the column decoder 6
Supplies a high-level column selection signal Yj to the gate of the transistor Q7, so that the transistor Q7 is turned on. Therefore, the potential change appearing on bit line BLj is applied to sense amplifier 9 shown in FIG. 2 via transistor Q7 and IO line 14. The data signal amplified by the sense amplifier 9 is output as output data “0” via the output buffer 12.

When data is read from a state where the high level is held in the storage node N1, no current flows through the path between the access gate transistor Q3 and the driver transistor Q2, so that the potential of the bit line BLj does not change. Therefore, the data signal amplified by the sense amplifier 9 is inverted with respect to the state where the low level is held in the storage node N1, and is output as output data "1".

When data "1" is written to the memory cell MC, that is, when a high level is written to the storage node N1, the power supply potential (VDD) is supplied to the bit line BLj and the word line WLi becomes high. The resistance of access gate transistor Q3 is sufficiently reduced, and a high level is written to storage node N1. This high level potential is
Since the voltage is sufficiently higher than the inverted voltage of the inverter, driver transistor Q1 is turned on, driver transistor Q5 is turned off, and the potential of node N2 becomes the ground potential, so that driver transistor Q2 is turned off.

When data "0" is written to the memory cell MC, that is, when a low level is written to the storage node N1, a ground potential is supplied to the bit line BLj, and when the word line WLi becomes a high level, the access gate transistor The resistance of Q3 drops sufficiently, and a low level is written to storage node N1. As a result, the driver transistor Q1 is turned off, the driver transistor Q5 is turned on, and the potential of the node N2 becomes the power supply potential (VDD), so that the driver transistor Q2 is turned on.

Next, consider the case where, when this memory cell MC is not selected, the opposite data is written to another memory cell connected to the same bit line BLj. As described above, when the bit line BLj goes low, the high level of the storage node N1 starts to drop due to the sub-threshold leakage of the access gate transistor Q3 formed by a thin film transistor. As previously mentioned,
The sub-threshold leakage current of the thin-film transistor Q3 is set to about 100 pA, and the parasitic capacitance of the storage node N1 is set to 1
If it is about 0 fF, it takes about 10 ⁴ seconds until the voltage of the storage node N1 drops by 1V. Therefore, the high-level storage node N1 of the non-selected memory cell MC can hold the data "1" without being substantially affected by the shift of the bit line BLj to a low level. Conversely, even when the bit line BLj goes high when the storage node N1 is low, the off resistance of the access gate transistor Q3 formed of a thin film transistor is sufficiently larger than the on resistance of the driver transistor Q2. N1 does not transition from low to high.

As described above, according to the present invention, by setting the ratio of the leakage current between the access gate transistor and the driver transistor having no load element to 10: 1 or more, when the access gate transistor is off, The high level of storage node N1 can be maintained by the sub-threshold leakage current of the access gate transistor. Further, in the present invention, since a memory cell is composed of four elements, the required load element (or P-channel transistor) is の of the conventional memory cell composed of five elements, and the load element (or P-channel transistor) is required. Defects during the formation of the transistor can be reduced. Thus, according to the present invention, the yield of the SRAM can be improved. In the present invention, a load element (or a P-channel transistor) is formed only on one side. The high level of the storage node N1 can be determined by the relationship between the access gate transistor and the driver transistor. In N2, by having the load element R1 (or P-channel transistor Q5), when the driver transistor Q1 is off,
A high-level potential can be supplied and maintained.

[0051]

As described above in detail, according to the semiconductor memory device of the present invention, since the memory cell is composed of four elements, the memory cell is compared with the conventional five-element type semiconductor memory device.
Higher integration can be achieved. In particular, by forming the access gate transistor and / or the load element with a thin film transistor stacked above the bulk transistor, further higher integration can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a memory cell in an SRAM according to an embodiment of the present invention.

FIG. 2 is a block diagram of an SRAM.

FIG. 3 is a circuit configuration diagram of a memory cell in a conventional SRAM.

FIG. 4 is a circuit configuration diagram of a memory cell in an SRAM according to another embodiment of the present invention.

[Explanation of symbols]

Q1, Q2 N-channel driver transistor Q5 P-channel driver transistor R1 Resistance Q3 Access gate transistor N1 Storage node WLi Word line BLj Bit line

Claims (6)

[Claims] 1. A semiconductor memory device comprising: a plurality of memory cells formed on a semiconductor substrate; and word lines and bit lines connected to the memory cells, wherein each of the memory cells has a single input / output node. A data storage means for storing a data signal applied via the input / output node, and connected between a bit line of a corresponding column and the input / output node, and turned on in response to a row address signal The data storage means is constituted by a pair of driver transistors composed of a bulk transistor formed on the semiconductor substrate, and a drain region of a first transistor among the driver transistors is A second transistor connected to a gate electrode of a second transistor among the input / output node and the driver transistor; A drain region of the first transistor is connected to a gate electrode of the first transistor and one end of a load element; source regions of the first and second transistors are connected to one power supply line; Is connected to the other power supply line. 2. A semiconductor memory device comprising: a plurality of memory cells formed on a semiconductor substrate; and word lines and bit lines connected to the memory cells, wherein each of the memory cells has a single input / output node. A data storage means for storing a data signal applied via the input / output node, and connected between a bit line of a corresponding column and the input / output node, and turned on in response to a row address signal An inverter comprising a P-channel transistor and a first N-channel transistor comprising a bulk transistor formed on the semiconductor substrate;
A second N-channel transistor formed of a bulk transistor, wherein the input / output node is connected to an input of the inverter and a drain region of the second N-channel transistor, and an output of the inverter is connected to the second N-channel transistor. Connected to the gate electrode of the N-channel transistor,
A semiconductor memory, wherein the source regions of the first and second N-channel transistors are connected to one power supply line, and the source region of the first P-channel transistor is connected to the other power supply line. apparatus. 3. In a standby state or a non-selection state,
3. The semiconductor memory device according to claim 1, wherein a bit line is precharged to a power supply voltage, and a high level of said input / output node is maintained by a leakage current of said switching means. 4. The semiconductor memory device according to claim 1, wherein said switching means comprises a thin film transistor, and is stacked above said bulk transistor. 5. The semiconductor memory device according to claim 1, wherein said load element is constituted by a thin film transistor stacked above said bulk transistor. 6. The semiconductor memory device according to claim 2, wherein said P-channel transistor is constituted by a thin-film transistor stacked above said bulk transistor.