JPH1118105A - Osd circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the output of an OSD circuit arbitrarily variable without the need for changing OSD data on a memory by providing a means for adding the respective specified multiples of Y, Cb and Cr signal outputs of the OSD circuit to the respective specified multiples of the Y, Cb and Cr signal outputs of an image-processing circuit and output them. SOLUTION: Multipliers 3-5 multiply (1-α1)β, (1-α2)β and (1-α3)β respectively with the Y, Cb and Cr signal outputs of an image-processing circuit 1 and output them. In this case, relations 0<=α1<=1, 0<=α2<=1, 0<=α3<=1 and β=0 or 1 hold. To the respective multiplied outputs, adders 9-11 add the result of multiplying the Y, Cb and Cr signal outputs of this OSD circuit 2 by α1, α2 and α3 by the multipliers 6-8 and output them. Thus, when β=0, without changing the output of the OSD circuit 2, the values of α1-α3 can be changed and the Y, Cb and Cr signal outputs 12-14 can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OSD (On Screen Display) circuit, and more particularly to an OSD (On Screen Display) circuit.
The present invention relates to a circuit for multiplexing an SD signal.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing an example of the configuration of the prior art. In FIG. 2, reference numeral 21 denotes an image processing circuit;
SD circuit, 23 to 28 are multipliers, 29 to 31 are adders,
32 is a Y signal output, 33 is a Cb signal output, and 34 is a Cr signal output.

[0003] The Y signal output from the image processing circuit 21,
The Cb signal and the Cr signal are respectively applied to multipliers 23, 24, 2
5 and multiplied by (1−α). The Y signal, Cb signal, and Cr signal output from the OSD circuit 22 are transmitted to multipliers 26, 27, and 28, respectively, and multiplied by α. The outputs of the multipliers 23 and 26, the multipliers 24 and 27, and the multipliers 25 and 28 are added by adders 29, 30, and 31, respectively, so that a Y signal output 32, a Cb signal output 33,
A signal output 34 is obtained.

In the above-mentioned prior art, a mixed output is made by [image processing output] · (1−α) + [OSD output] · α using a coefficient α.

That is, by changing the value of the coefficient α stepwise (however, 0 ≦ α ≦ 1), the image processing circuit 21
And the output of the OSD circuit 22 can be adaptively mixed.

When only the output of the OSD circuit 22 is output, α = 1.

The OSD data of the OSD circuit 22 is usually
Stored in a bitmap format on a memory (not shown),
When changing the value of SD, it is necessary to rewrite the bitmap data on the memory.

[0008]

In the prior art described above, when only the OSD signal is output without blending (mixing) the output from the OSD circuit 22 with the output from the image processing circuit 21, the output of the OSD signal is reduced. In order to change the value, it is necessary to change the OSD value itself. And
As described above, generally, OSD data is often stored in a memory as bitmap data.

For this reason, in the above prior art, the OS
In order to rewrite the D data, it is necessary to perform a process of rewriting all data in the memory.

[0010] Therefore, the present invention has been made in view of the above problems, and has as its object the purpose of
An object of the present invention is to provide an OSD circuit capable of arbitrarily changing an OSD output without changing D data.

[0011]

In order to achieve the above object, the OSD circuit of the present invention comprises (1-α1) · β times the Y signal output of the image processing circuit and (1-α2) · β times the Cb signal output.
β times, (1-α3) · β times of Cr signal output (0 ≦ α1 ≦
1, 0 ≦ α2 ≦ 1, 0 ≦ α3 ≦ 1, β = 0 or 1), respectively, α1 times the OSD output Y signal output, C
It has means for adding and outputting α2 times the b signal output and α3 times the Cr signal output.

[0012]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, in the preferred embodiment, the coefficients αi and β are used to calculate [output of image processing circuit] · (1−αi) · β + [output of OSD circuit] · αi (where 0 ≦ αi ≦ 1 , Β are 0 or 1) as mixed output. According to the embodiment of the present invention, by independently varying the value of each coefficient αi with β = 0, the value of the OSD output can be varied without changing the contents of the memory storing the OSD value. .

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. In FIG. 1, 1 is an image processing circuit, 2 is an OSD
Circuits, 3 to 8 are multipliers, 9 to 11 are adders, 12 is a Y signal output, 13 is a Cb signal output, and 14 is a Cr signal output.

The Y signal output from the image processing circuit 1 is
It is multiplied by (1−α1) · β by the first multiplier 3 and becomes the input of the first adder 9. The Y signal output from the OSD circuit 2 is multiplied by α1 in the fourth multiplier 6 and is input to the first adder 9. Here, 0 ≦ α1 ≦ 1, β = 1.

Similarly, the C output from the image processing circuit 1
The b signal is multiplied by (1−α2) · β in the second multiplier 4,
It becomes the input of the second adder 10. The Cb signal output from the OSD circuit 2 is multiplied by α2 in the fifth multiplier 7 and is input to the second adder 10. Here, 0 ≦ α2 ≦ 1, β =
It is one.

Further, the Cr output from the image processing circuit 1
The signal is multiplied by (1−α3) · β in the third multiplier 5, and is input to the third adder 11. The Cr signal output from the OSD circuit 2 is multiplied by α3 in the sixth multiplier 8 and is input to the third adder 11. Here, 0 ≦ α3 ≦ 1, β =
It is one.

The output of the first adder 9 is a Y signal output 12,
The output of the second adder 10 is a Cb signal output 13 and the output of the third adder 11 is a Cr signal output 14.

In this embodiment, when β = 1, it functions as a mixing circuit of the output of the image processing circuit 1 and the output of the OSD circuit 2.

On the other hand, when β = 0, the first, second and third
The outputs of the multipliers 3, 4, and 5 are 0.

For this reason, the Y signal output 12 is connected to the OSD circuit 2
The Cb signal output 13 is converted to a signal obtained by multiplying the Cb signal output of the OSD circuit 2 by α2,
The signal output 14 is a signal obtained by multiplying the Cr signal output of the OSD circuit 2 by α3.

That is, when β = 0, by changing the values of α1, α2, and α3 without changing the output of the OSD circuit 2, the Y signal output 12, the Cb signal The values of the output 13 and the Cr signal output 14 can be changed.

In the above embodiment, the case where the output of the image processing circuit takes the Y, Cb, Cr signal format has been described, but the output of the image processing circuit has R, G,
The present invention can be applied to the case of taking the B signal format. That is, as a second embodiment of the present invention,
The case where the output of the image processing circuit takes the R, G, and B signal formats will be described. A first multiplier for multiplying the R signal output of the image processing circuit by (1−α1) · β, and the G signal output by ( 1−α2) · β, and a third multiplier that multiplies B signal output by (1−α3) · β (0 ≦ α)
1 ≦ 1, 0 ≦ α2 ≦ 1, 0 ≦ α3 ≦ 1, β = 0 or 1), a fourth multiplier that takes α1 times the R signal output from the OSD circuit, and a G signal output A fifth multiplier that takes α2 times the B signal output and a sixth multiplier that takes α3 times the B signal output. The first and fourth multipliers, the second and fifth multipliers, the third and The outputs of the six multipliers are added and output by first, second, and third adders, respectively. The output of the first adder is an R signal output, the output of the second adder is a G signal output, and the output of the third adder is a B signal output.

[0023]

As described above, according to the present invention, O
The value of the OSD output can be changed without changing the SD value.

The reason is that, in the present invention, for example, the values of Y, Cb, and Cr are changed without changing the OSD value by independently changing the values of α1, α2, and α3 with β = 0. This is because it is configured to be able to be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image processing circuit 2 OSD circuit 3, 4, 5, 6, 7, 8 Multiplier 9, 10, 11 Adder 12 Y signal output 13 Cb signal output 14 Cr signal output 21 Image processing circuit 22 OSD circuit 23, 24, 25, 26, 27, 28 Multiplier 29, 30, 31 Adder 32 Y signal output 33 Cb signal output 34 Cr signal output

Claims (3)

[Claims] An image processing circuit mixes an output of an image processing circuit with an on-screen display ("OSD") signal.
In the SD circuit, (1-α1) · β times the Y signal output of the image processing circuit;
(1−α2) · β times the Cb signal output and (1−α3) · β times the Cr signal output (where 0 ≦ α1 ≦ 1, 0 ≦ α2 ≦
1, 0 ≦ α3 ≦ 1, β = 0 or 1) means for adding and outputting α1 times the Y signal output of the OSD signal, α2 times the Cb signal output, and α3 times the Cr signal output of the OSD signal, respectively. An OSD circuit comprising: 2. An on-screen display ("OSD") signal is mixed with the output of the image processing circuit.
In the SD circuit, (1-α1) · β times the R signal output of the image processing circuit;
(1-α2) · β times the G signal output, and (1-α2) times the B signal output.
α3) · β times (however, 0 ≦ α1 ≦ 1, 0 ≦ α2 ≦ 1, 0
≦ α3 ≦ 1, β = 0 or 1), respectively, α1 times the R signal output of the OSD signal and α2 times the G signal output.
An OSD circuit comprising means for adding and multiplying the output of the B signal by a factor of 3 and an output of α3 times. 3. The method of claim 1, wherein the output of the image processing circuit is mixed with an on-screen display ("OSD") signal.
In the SD circuit, for each output of the image processing circuit, the output is calculated as (1-αi) ·
a multiplier that multiplies by β (0 ≦ αi ≦ 1, where α is an integer between 1 and the number of outputs of the image processing circuit, β = 0 or 1), and a multiplier for each output of the OSD signal. A multiplier that multiplies the output by αi, outputs a value obtained by adding the outputs of these two multipliers by an adder, and varies the value of each coefficient αi independently to vary the value of the OSD output. An OSD circuit characterized by being made possible.