JPH1117702A - Packet data memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with the congestion of queues by exchanging queue priority by storing the queue read priority, which is different from a packet data memory circuit having plural queues, one by one or as a data base, generating a queue number and selecting a priority number. SOLUTION: N pieces of queue number generating circuits 3 (3-1 to 3-n) respectively store different queue read priority #1...#n. The queue number selecting circuit 3 selected by an enable signal from a selector circuit 4 selects the queue of the highest queue read priority, for which the number of stored packet data in queue information is not '0'. and outputs it to a memory read managing circuit 2 according to the priority. According to a timing signal from the outside, the memory read managing circuit 2 updates the queue information to the selector circuit 4 and the queue number generating circuits 3 and controls the queue read side of a packet data memory circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet data sequence which has recently been multiplexed by packet multiplexing information having different traffic characteristics, such as data, voice, image, etc., and transmitted and received over a single network. The present invention relates to a packet data memory device which stores packet data strings in which a plurality of traffic classes classified for each class are stored in queues classified for each traffic class, and reads out packet data in synchronization with an external timing signal.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional packet data memory device. Table 1 shows an example of the queue read priority realized by the conventional packet data memory device shown in FIG.

[0003]

[Table 1]

The conventional packet data memory device comprises a packet data memory circuit 1, a memory read management circuit 2, and a queue number generation circuit 3 for generating a unique queue number. The queue number generating circuit 3 stores only one read priority. Since there is no remarkable difference in characteristics between traffic classes in the conventional traffic, the provision of only one queue number generation circuit 3 can sufficiently satisfy the performance required only by one read priority. There are m traffic classes classified according to the characteristics of the traffic in the packet data stream from the outside. The traffic characteristics are characteristics that appear for each content of the packet data string. In the example of Table 2, both data of traffic class 1 and traffic class 2 are VB data.
R (Variable Bit Rate) is a class in which a large amount of data is generated instantaneously and low discarding is required. However, the discard rate of traffic class 1 can be suppressed lower than that of traffic class 2. Required.

[0005]

[Table 2]

[0006] The packet data memory circuit 1 is composed of m queues. Different numbers are assigned to these queues, and the number m of queues is the number m of existing traffic classes. That is, the queue and the traffic class have a one-to-one correspondence. The packet data stream from the outside is classified by traffic class,
Each packet is stored in the corresponding queue of the packet data memory circuit 1. The queue number generating circuit 3 stores only one read priority, and selects a queue in which the number of stored packet data included in the queue information is not 0 and the queue read priority is the highest according to the priority,
The queue number is generated for the memory read management circuit 2. The memory read management circuit 2 generates queue information for the queue number generation circuit 3 according to an external timing signal, and controls the queue read side of the packet data memory circuit 1.

[0007]

Since there is no significant difference in characteristics between the traffic classes in the conventional traffic, the performance required by only one read priority can be sufficiently satisfied. In the example of Table 2, the data of traffic class 1 and traffic class 2 are both VBR data, a class in which a large amount of data is generated instantaneously and low discarding is required. The rate is required to be kept lower than the traffic class 1 drop rate. Therefore, the packet data of the traffic class 2 queue need only be transmitted in priority to the packet data of the traffic class 1 queue, and as shown in the example of Table 1, the performance required by only one read priority. Satisfied enough.

[0008] However, in recent years, a remarkable difference in characteristics between traffic classes has been observed. Taking the example of Table 3, CBR of traffic class 1
(Constant Bit Rate) Data is a class in which packet data is generated at a constant speed and low delay is required.
The traffic class 2 VBR data is a class in which a large amount of data is instantaneously generated and low discarding is required.

[0009]

[Table 3]

When the conventional method is adopted for such traffic, that is, the traffic class 1 in Table 2 is the voice and image service of the traffic class 1 in Table 3, and the traffic class 2 is the IP packet of the traffic class 2 in Table 3. In the case where the service is used, the packet data of the traffic class 1 queue is transmitted in preference to the packet data of the traffic class 2 queue in a situation where the traffic class 2 queue is not congested. Traffic class 1 CBR
This prevents delay of packet data for voice and image services as data. However, VB of traffic class 2
Even when congestion occurs in the queue of R, the queue packet data of the traffic class 1 CBR is transmitted prior to the packet data of the traffic class 2 VBR queue. Therefore, in the conventional packet data memory device, not only is there no means for recovering the congestion of the packet data of the IP packet service which is the VBR data of the traffic class 2 in Table 3, but also the congestion situation of the packet data of the traffic class 2 is further deteriorated. Will be. That is, since one type of priority is fixed, there is a drawback that it is not possible to cope with a case where it is desired to change the queue read priority depending on the traffic situation.

An object of the present invention is to provide a packet data memory device capable of coping with queue congestion by changing the queue read priority.

[0012]

In order to achieve this object, a packet data memory device according to the present invention comprises: a packet data memory circuit having a plurality of queues, which constitutes a conventional packet data memory device; A memory read for generating an address signal and a read signal to a packet data memory circuit in accordance with a signal and a queue number generated by a queue number generating circuit to control a read side of the queue and generating queue information to the queue number generating circuit In addition to the management circuit, a plurality of queue number generating circuits for storing different queue read priorities one by one or as a database and generating queue numbers in accordance with the packet data accumulation number and queue read priority which are one of the queue information. Memory read when the number of packets exceeds the threshold Management circuit generates has a configuration in which a selection circuit for selecting a queue number generation circuit which stores (one is the queue information) queue read priority to be selected from the congestion indication, the.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The packet data memory device according to the present invention can select a queue read priority according to the queue congestion status, and can read packet data according to the selected queue read priority. In the example of FIG. 1 and Table 4, at normal time when there is no congestion, the queue number generation circuit # 1 is enabled and selects a queue number according to the priority # 1, and the memory read management circuit 2 selects a data packet according to the queue number. By reading the packet data from the packet data memory circuit 1 and sending it to the outside, it is possible to prevent packet data in the queue of the traffic class 1 from being delayed. For example, when the data packet of the traffic class n is congested, the queue number generation circuit #n is enabled and selects a queue number according to the priority #n, and the memory read management circuit 2 transfers the packet data according to the queue number. By reading the packet from No. 1 and sending it to the outside, it is possible to avoid the deterioration of the queue congestion situation of the traffic class n.

[0014]

FIG. 1 is a block diagram showing a case in which a plurality of queue number generating circuits, such as 3-1,..., 3-n, in which one queue reading priority is fixedly assigned to one queue number generating circuit. 1 is a first embodiment of a packet data memory device according to the present invention. Table 4 shows an example of the queue read priority realized by the packet data memory device of FIG. The packet data memory device includes a packet data memory circuit 1, a memory read management circuit 2, a selection circuit 4, and a plurality of queue number generation circuits 3 (3-1, 3-2) for generating queue numbers.
.., 3-n).

[0015]

[Table 4]

There are m traffic classes classified according to "traffic class characteristics" in the packet data stream from the outside. The "traffic characteristics" are characteristics that appear for each content of the packet data sequence. In the example of Table 3, CBR (Constant Bit Rate) data generates packet data at a constant speed and requires low delay. VBR (Variable Bit Rate) data is a class in which a large amount of data is instantaneously generated and low discarding is required. The queue read priority P is assumed to be r
Are defined for each “traffic situation”, and if the number of traffic classes is m, r ≦ _m P _m
= M! Becomes “Traffic status” is a combination of traffic conditions defined in each traffic class. Also, the number n of the queue read priorities can be n = r, so that n ≦ m! Becomes

FIG. 2 shows a second embodiment of the present invention of a packet data memory device having two traffic classes shown in Table 3.
Table 5 shows the queue number selection logic in each traffic situation in FIG.

[0018]

[Table 5]

In Table 5, "congestion" and "no congestion" are shown as traffic states in the two traffic classes.
Are adopted, four traffic conditions are defined by a combination of the traffic conditions of CBR and VBR, and the read priority of the traffic class is defined for each traffic condition. In the example of Table 5, the queue read priority selected when the traffic status is "status 2" is "priority 2", and when the traffic status is other than that, "priority 1" is selected. You. In the example of Table 5, the packet data memory device of the present invention has two queue read priorities.

The circuits constituting the first and second embodiments of the present invention shown in FIGS. 1 and 2 will be described below. In the first embodiment of FIG. 1, the packet data memory circuit 1 is composed of m queues. Different numbers are assigned to these queues, respectively, and (the number of queues in the packet data memory circuit) = m = (the number of traffic classes). The queue of the packet data memory circuit 1 corresponds to the traffic class on a one-to-one basis.
An external packet data sequence is classified for each traffic class, and is stored in a corresponding queue of the packet data memory circuit 1, respectively.

In the first embodiment shown in FIG. 1, n queue number generating circuits 3 (3-1,..., 3-n) have different queue read priorities # 1, # 2,. n is stored. The queue number generation circuit 3 selected by the enable signal from the selection circuit 4 according to the queue read priority stored in the queue number generation circuit 3 ,
A queue in which the packet data accumulation number of the queue information is not 0 and the queue read priority is the highest is selected, and the queue number is generated for the memory read management circuit 2.

In the first embodiment shown in FIG. 1, the memory read management circuit 2 updates the queue information generated for the selection circuit 4 and the queue number generation circuit 3 according to an external timing signal, and updates the packet data memory. The circuit 1 performs “control of the queue read side”. Table 6 shows an example of the queue information.

[0023]

[Table 6]

The "control of the queue read side" by the memory read management circuit 2 means that the "next packet data read address signal" and "read signal" are read based on the queue number in accordance with the external timing signal. , One packet is read from the queue, and the read queue information is updated. "Queue information update processing"
The “number of accumulated packet data” is decremented, and the “next packet data read address” is set to the first address of the memory area where the next packet data is stored or will be stored. "Congestion display"
Displays "congestion present" when the "number of stored packet data" exceeds the "congestion determination threshold value". If the "number of accumulated packet data" is equal to or less than the "congestion determination threshold value", "no congestion" is displayed.

In the first embodiment shown in FIG. 1, the selection circuit 4 determines the current traffic condition based on the "congestion indication" in the queue information from the memory read management circuit 2, and selects the queue to be selected at the present time. Read priority # 1,... Or #
n storing the queue number generating circuit (3-1,...,.
Or 3-n) is selected by the enable signal.

FIG. 2 shows CBR and VBR as shown in Table 3.
A second embodiment of the packet data memory circuit (m = FIG. 1) configured when there are two types of traffic classes and a traffic situation as shown in the example of Table 5 is assumed.
2, n = 2).

In the second embodiment shown in FIG. 2, the packet data memory circuit 1 is composed of two queues. These queues are assigned different numbers, and in the example of Table 3, the traffic class is CB.
Since there are two R and VBR, (the number of queues in the packet data memory circuit 1) = 2 = (the number of traffic classes). The queue of the packet data memory circuit 1 corresponds to the traffic class on a one-to-one basis. The packet data string from the outside is classified into CBR and VBR, and the packet data string of CBR is stored in the CBR queue of the packet data memory circuit 1, and the packet data string of VBR is stored in the VBR queue of the packet data memory circuit 1. ing.

In the second embodiment shown in FIG. 2, the queue number generating circuit 5 comprises two (5-1, 5-2)
Different queue read priorities are stored. When the queue number generation circuit 5-1 storing “priority 1” is selected by the enable signal from the selection circuit 4, that is, the traffic status = “status 1”
Alternatively, in "Situation 3" or "Situation 4", in the situation where the number of packet data stored in the CBR queue is 0 and the number of packet data stored in the VBR queue is not 0, the VBR queue is selected as the read queue. C
The BR queue is selected as a read queue, and the queue number of the selected queue is generated for the memory read management circuit 2. Queue number generation circuit 3-2 storing "priority 2" in response to an enable signal from selection circuit 4.
Is selected (traffic status = “status 2”), the VBR queue is selected as the read queue, and the queue number of the selected queue is generated for the memory read management circuit 2.

In the second embodiment shown in FIG. 2, the memory read management circuit 2 updates the queue information generated for the selection circuit 4 and the queue number generation circuit 5 according to an external timing signal, and The reading side of the queue of the memory circuit 1 is controlled.

In the second embodiment shown in FIG. 2, the selection circuit 4 determines the current traffic situation based on the congestion indication in the queue information, and stores the queue read priority to be selected at the present time. Queue number generating circuit 5-1
Alternatively, 5-2 is selected by the enable signal. CBR
Both congestion display of queue and VBR queue are "no congestion"
If so, the traffic status is determined to be "status 1", and the queue number generating circuit 5-1 storing "priority 1" is enabled. If the congestion indication of the CBR queue is "no congestion" and the congestion indication of the VBR queue is "congestion", the traffic situation is determined to be "situation 2" and the queue number generation circuit storing "priority 2" Enable 5-2. If the congestion indication of the CBR queue is “congested” and the congestion indication of the VBR queue is “no congestion”, the traffic situation is determined as “situation 3” and “priority 1”
Is enabled. If the congestion indication of the CBR queue is "congested" and the congestion indication of the VBR queue is "congested", the traffic situation is determined to be "situation 4" and the queue number generation circuit storing "priority 1" Enable 5-1.

FIG. 3 shows an operation sequence of the embodiment of FIG. 1 or FIG. After the operation starts (S1), the memory read management circuit 2 responds to the external timing signal (S1).
2) Queue information is generated (S3). In the example of FIG. 2 and Table 5, if the traffic status is status 2 (no CBR congestion, VBR congestion), the selected read priority is priority 2. The selection circuit 4 generates the queue number generation circuit 3 or
5 is selected by the enable signal (S4). The selected queue number generating circuit 3 or 5 selects a queue according to the read priority and the number of stored packet data stored in its own circuit, and generates the queue number (S5). In the example of FIG. 2 and Table 5, the selected cue number generation circuit
If 5 is the circuit 5-2, the queue number 2 is selected and generated based on the read priority 2 and the number of packet data stored in the queue information. The memory read management circuit 2 generates a next packet data read address signal and a read signal according to the queue number, reads the packet data from the packet data memory circuit 1, and sends the packet data to the outside (S
6). After the reading, the queue information related to the read queue is updated (S7).

FIG. 4 shows a third embodiment of the packet data memory device of the present invention in which a plurality of queue read priorities are stored in a database and stored. The packet data memory device of FIG. 4 includes a packet data memory circuit 1, a memory read management circuit 2, a priority selection circuit 4a, a priority database 6, and a queue number generation circuit 7.
There are m traffic classes classified according to the characteristics of the traffic class in the packet data stream from the outside. The queue read priority is defined for each of r assumed traffic situations. If the number of traffic classes is m, r ≦ _m P _m = m! Becomes
Also, the number n of the queue read priorities can be n = r, so that n ≦ m! Becomes The packet data memory circuit 1 includes m queues. These queues are assigned different numbers, respectively (the number of queues in the packet data memory circuit 1) =
m = (the number of traffic classes). Further, the queue of the packet data memory circuit 1 corresponds to the traffic class on a one-to-one basis. An external packet data sequence is classified for each traffic class, and is stored in a corresponding queue of the packet data memory circuit 1, respectively.

The queue number generating circuit 7 determines the priority of the queue read by the priority selecting circuit 4a.
The queue having the highest number of packet data stored in the queue information is selected, and the queue number is stored in the memory read management circuit 2
Occurs for The memory read management circuit 2 updates the queue information generated for the priority selection circuit 4a and the queue number generation circuit 7 in accordance with an external timing signal, and manages the read side of the queue of the packet data memory circuit 1. This is performed in the same manner as in one embodiment.

The priority selection circuit 4a determines the current traffic condition based on the congestion display in the queue information, selects a queue read priority to be selected at the present time from the priority database 6, and selects the selected queue read priority. The degree is notified to the queue number generation circuit 7. Priority database 6
Stores a plurality of queue read priorities, and one of the queue read priorities is selected by the priority selection circuit 4a.

[0035]

As described above in detail, in the conventional packet data memory circuit, since one type of priority is fixed, there is a drawback that it is not possible to cope with the case where it is desired to change the queue read priority depending on the traffic situation. According to the present invention, there is an effect that packet data stored in a queue of a traffic class having the highest priority at the present time can be transmitted to the outside according to a traffic situation. For example, when the packet data of the traffic class 2 is congested, the packet data of the traffic class 2 is transmitted with priority over the packet data of the other traffic classes, the congestion of the packet data of the traffic class 2 is recovered, and the packet data is discarded due to the congestion. In normal times, the packet data of the traffic class 1 is transmitted with higher priority than the packet data of the other traffic classes as in the conventional case, so that the transfer delay of the packet data of the traffic class 1 can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention in which traffic shown in Table 3 is considered.

FIG. 3 is an example of an operation sequence of a circuit realized by the present invention.

FIG. 4 is a block diagram showing an embodiment of the present invention in which queue read priority data is stored in a database in consideration of the traffic shown in Table 3.

FIG. 5 is a block diagram showing a conventional example.

[Description of Signs] 1 packet data memory circuit 2 memory read management circuit 3 , 3-1,..., 3-n, 5 , 5-1 5-2, 7 queue number generation circuit 4 selection circuit 6 priority database

Claims (2)

[Claims] 1. A queue for reading out stored packet data in synchronization with an external timing signal from a packet data memory circuit which is divided into a plurality of queues having different queue numbers and sequentially stores packet data. A packet data memory device for selecting and reading the packet data, wherein the packet data memory device generates an address signal and a read signal to the packet memory circuit according to the external timing signal and the queue number, and outputs the address signal and the read signal to the packet data memory circuit. A congestion indication indicating that the number of allowed storages for accumulating the packet data has exceeded a predetermined congestion determination threshold value for determining congestion of the packet data and stored in the packet data memory circuit. Queue information to include the number of stored packet data A plurality of queue read priorities which are generated and different from the memory read management circuit that controls the read side of the queue in the packet data memory circuit are stored one by one, and the queue read priority corresponding to each queue read priority is stored. A plurality of queue number generation circuits for generating a queue number until the packet data accumulation number of the corresponding queue becomes zero and supplying the packet data to the memory read management circuit; and a queue number corresponding to the congestion display of the queue information. A selection circuit that selects the queue number generation circuit that stores the queue read priority that is predetermined and generates the corresponding queue number until the packet data accumulation number of the corresponding queue becomes zero. A packet data memory device comprising: 2. A queue for reading out the stored packet data in synchronization with an external timing signal is selected from a packet data memory circuit which is divided into a plurality of queues each having a different queue number and sequentially stores the packet data. A packet data memory device for reading the packet data, generating an address signal and a read signal for the packet memory circuit according to the external timing signal and the queue number, and A congestion indication indicating that the number of permitted storages for accumulating packet data exceeds a predetermined congestion determination threshold value for determining congestion of the packet data, and is stored in the packet data memory circuit. Queue information to include the number of stored packet data A memory read management circuit for controlling the read side of the queue in the packet data memory circuit, a priority database storing a plurality of queue read priorities, and the priority database of the queue information A plurality of queue number generating circuits for generating the queue numbers corresponding to the queue read priorities supplied from the queue until the packet data accumulation number of the corresponding queue becomes zero and supplying the packet data to the memory read management circuit And selecting one of the plurality of queue read priorities predetermined to correspond to the congestion display from the priority database by the congestion display of the queue information and storing the packet data in the queue. And a priority selection circuit for outputting until the output becomes zero. Moly equipment.