JPH11175578A - Generation supporting method and device for register transfer level description module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load of a designer, and to shorten a designing period by supporting the division and merge of an RLT(register transfer level) by a designer, and easily preparing an RTL description module in a circuit scale suited to the following logical synthesis. SOLUTION: In dividing and merging an applied register transfer level description module, one part of the register transfer level descriptions of a module to be divided or merged is extracted so that a new module to be generated after the division or merger can be obtained in a circuit scale suited for the following logical synthesis, and then a new module is automatically generated from the extracted description part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CAD (Comp
More particularly, the present invention relates to a method and an apparatus for supporting generation of a module represented by a register transfer level description in a function design in a method of designing a semiconductor integrated circuit using a Uter Aided Design (computer-assisted design).

[0002]

2. Description of the Related Art The number of gates is increasing with the increase in the scale and integration of a logic LSI (hereinafter, the term LSI is used as a generic term including VLSI, ULSI, etc.). Therefore, in the design of the logic LSI, the functions of the system are divided into appropriate blocks, and each block is divided into a system design, a function design, a logic design,
Hierarchical design for performing detailed design in stages is generally performed by dividing into a plurality of design stages of circuit design and layout design, and a number of various CAD tools suitable for each design stage have been developed. .

[0003] As described above, the hierarchical design includes, as a basic stage, a system design for determining what kind of functional block is divided into the whole system and how it is operated in order to realize the system specifications. Register transfer level (R
egistor Transfer Level: RT
L) A functional design for designing, a logical design in which each functional block is composed of a combination of basic gates (NAND, NOR, etc.) based on a register transfer level description (hereinafter referred to as an RTL description), and a circuit specification based on the logical design In order to satisfy the requirements, circuit design to determine the characteristics of gate-level electronic circuits and devices, and layout design to convert the circuit diagram into placement and wiring of devices with physical shapes and dimensions, usually at each design stage Computer simulation and verification are performed.

Here, at the above-mentioned function design stage, specifically, basically, at the discretion of the designer, each function block is further a unit having a united logical function as one component. (Hereinafter, referred to as modules), and each module is described in the RTL, which is a level that mainly describes data transfer between registers, and an RTL description module is created. Then, at the logic design stage, logic synthesis for generating a detailed gate level is performed for each RTL description module.

[0005]

As described above, in the design and development of a logic LSI, RTL description modules are created hierarchically by functional design, and logic synthesis is performed for each RTL description module. Then, a layout is generated from the gate circuit. However, in the current CAD tool, a reasonable circuit scale for logic synthesis in logic design is about several K to 10K gates, and floor planning in layout design is required.
Since an appropriate circuit size is, for example, 200K gates, if the circuit size of each RTL description module is too large, logic synthesis and floor planning cannot be performed by a CAD tool. Therefore, it is necessary to further divide the RTL description module into a plurality of small-scale RTL description modules to reduce the circuit scale of one RTL description module so that the CAD tool can be used.

Specifically, for example, in an RTL description module hierarchical structure as shown in FIG.
When logic synthesis is not completed properly because the circuit size of the description module M112 is 20K gates, as shown in FIG. 12B, the number of gates is several K to 10K, which is a circuit size appropriate for the above-described logic design. The RTL description module M112 and the RTL description modules M112A and M1
There is a need to split into two RTL description modules, 12B.

Further, in the RTL description module hierarchical structure as shown in FIG. 13 (a), when floor planning is performed for each of the RTL description modules M1, M2,.
In the case of a 0K gate, the above-mentioned reasonable circuit size of 2
Since it exceeds the 00K gate, high-performance arrangement and wiring cannot be performed. Therefore, it is necessary to perform logic synthesis again so as to reduce the circuit scale, that is, to divide the circuit into two, and to optimize the logic synthesis.
It is necessary that the RTL description module M2 itself is divided into two (see FIG. 13B). Further, the gate-level netlist itself, which is the result of logic synthesis, may be divided into two.

On the other hand, contrary to the above-described division of the RTL description, there is a case where merging must be performed. For example, if the RTL description module is created by classifying it too finely for each functional element, the result of logic synthesis may violate the timing constraints as a whole, and may even increase the number of gates. . Therefore, in such a case, some RTL description modules may need to be merged and one RTL description module must be newly created.

Further, the above-described division / merge is performed by manual input by a designer, and at that time, an input error may occur.

As described above, once the logic synthesis is completed, if the RTL description module (or netlist) needs to be re-analyzed and re-created, that is, the hierarchical structure needs to be reviewed, an error occurs in the re-creation. In some cases, these factors increase the burden on the designer, resulting in a longer design period and a delay in product development as a whole.

[0011] In particular, L of future deep submicron generation
In SI design development, floor planning is performed at a function design stage (RTL) before logic synthesis, and logic synthesis and subsequent floor planning, placement, wiring (ro) are performed using the floor plan information.
) is needed to converge the design. However, when the RTL description modules are divided and merged as described above for each step of logic synthesis and floor planning, the design flow from the upper level to the lower level (system design, function design, logic design,
In the case where the consistency (consistency) of division / merge in circuit design and layout design cannot be maintained, it becomes a serious problem when the design flow is repeated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to support a designer in dividing and merging RTL description modules, and to provide a circuit-scale RTL description module suitable for subsequent logic synthesis. It is an object of the present invention to provide an RTL description module creation support method and apparatus which facilitates creation of an RTL description module, thereby reducing the burden on a designer and thereby shortening the design period.

[0013]

According to the present invention, when a given register transfer level description module is divided or merged, a new module generated after the division or merging is used. A feature is that a part is extracted from the register transfer level description of a module to be divided or merged so as to have a gate scale, and a new module is automatically generated from the extracted description part.

That is, if each module represented by the register transfer level description created based on the given specification does not have a gate scale suitable for logic synthesis and floor planning performed for each module thereafter, A part of the register transfer level description of a module whose gate size is too large or too small is extracted, and a new module having a gate size suitable for logic synthesis etc. is automatically extracted from the extracted description part and the remaining description part. That can be generated.

Whether the gate scale is suitable for logic synthesis or the like is determined by, for example, the number of gates of a module to be divided or merged, the number of gates of its lower modules, and the extracted number. It is possible to estimate the number of gates in the description portion and the number of gates in the lower module, respectively, and to judge from the estimation results.
Further, this estimation can be obtained without actually performing logical synthesis or the like, and even if it is repeatedly performed until the estimation result becomes an appropriate value, complicated processing is not performed.

Further, when a new module is actually generated from the extracted description part, the input signal and the output signal of the statement group constituting the extracted description part are grasped and grasped. Determine and classify the component types of the input signal and the output signal, create a declaration part indicating the component type of each of the determined and classified input signal and the output signal, and create a declaration part extracted from the created declaration part. Describing the statement group, creating one module from the extracted description part, grasping the input signal and output signal of the statement group that constitutes the remaining description part after extraction, and grasping the grasped input Determine the component type of signal and output signal
Classify, create a declaration part indicating the component type of each of the input signal and the output signal determined and classified,
Describe the statement group of the remaining description part after extraction in the created declaration part, create one module from the remaining description part after extraction, and further subject to splitting or merging If a higher-level module exists in the module, the register transfer level description of the higher-level module may be modified according to the result after division or merging.

According to the present invention having such a configuration, when the gate scale of the created RTL description module is too large or too small to perform the logic synthesis or the like, before the logic synthesis or the like is actually performed, Dividing is performed for a module that is too large, and merging is performed for a module that is too small. In addition, since the number of gates of each module and its lower modules, and the scale of the divided or merged module and its lower modules are determined by estimating the number of gates, appropriate division and division are performed before logic synthesis or the like is performed. Merging can be performed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a processing procedure of a register transfer level (RTL) description module generation support method according to an embodiment of the present invention. The processing procedure shown in FIG. 1 is composed of seven processing steps. Prior to this processing, an RTL description of a module hierarchical structure, which constitutes the entire target semiconductor integrated circuit, is once determined based on given knowledge and experience of a designer from given specifications. Shall be.

As shown in FIG. 1, first, in step 1, the once determined RTL description is read.

Next, in step 2, the module hierarchical structure of the RTL description read in step 1 is traced.

Next, in step 3, the module hierarchical structure traced in step 2 is displayed.
Then, at least one or more modules to be divided or merged are specified based on the displayed module hierarchical structure. Further, a specific RTL description of the specified module is displayed.

Next, when the division is performed in step 4, the part is actually taken out of the RTL description displayed in step 3 and a part thereof as a new separate module is designated. On the other hand, when performing merging, a part to be actually merged is specified from the displayed plurality of RTL descriptions.

Next, in step 5, the number of gates of the module specified in step 3 and lower modules below the module, and the number of gates of the description part specified in step 4 are estimated. Also,
If there is a lower module in them, the number of gates of the lower module is also estimated. Here, there are various methods for estimating the number of gates of the circuit represented by the RTL description, and for example, the method described in the document “David E. Wallace and Mand”
alagiri S. Chandrasekhar,
“High-Level Delay Estimat
ion for Technology-Indepe
dent Logic EQs, "Pro
ceedings of IEEE Internet
ionical Conference Comput
er-Aided Design, ICCAD-90,
pp. 188-191. And the literature "Mehrdad Nourani and Chri"
stos Papachristou, “A Layo
out Estimation Algorithm f
or RTL Datapaths, "Proceed
ings of the 30th ACM / IEEE
Design Automation Conference
ence, June 1993, pp. 139-143. 154-15
9. And the like.

Next, in step 6, it is determined from the estimation result obtained in step 5 whether or not the circuit size of the module after division / merging becomes appropriate.
Here, whether or not it is appropriate is, for example, as described in the prior art, that the estimation result is a reasonable circuit scale of about several K to 10K gates in logic synthesis, and an appropriate result in floor planning. The circuit scale is 200
Judgment can be made based on whether or not it is about K gates.

Next, if it is determined in step 6 that the data is not valid, the process returns to step 3 again, and steps 6 to 5 are repeated until the data is determined to be valid in step 6.

Finally, if it is determined in step 6 that the validity is obtained, in step 7, the RTL description of the module designated to be divided / merged in step 4 is actually divided / merged.

Next, the method of dividing / merging the RTL description of the module specified to be divided / merged in step 7 will be described. FIG. 2 is a flowchart illustrating a processing procedure of an RTL description division / merge method of a module for which division / merge is specified. The processing procedure shown in FIG. 2 includes seven processing steps.

First, the RTL description of the module to be divided / merged will be briefly described. FIG.
FIG. 3 is a diagram illustrating an example of a module represented by an RTL description. Although this description is described in verilog-HDL, which is a hardware description language, the present invention is not limited to the case where the description is made in this language. However, the same effect can be obtained.

"Module M2" shown in FIG. 3 represents a module name represented by this description, and the module name of this description is M2. In addition, "(c
k, keyck, ..., stst) "is the module M
2 shows an input signal and an output signal (see a portion indicated by an arrow in a in the figure).

The part indicated by b in FIG.
2, the input signal and the output signal are converted to a signal corresponding to the input terminal,
A signal corresponding to the output terminal, a signal corresponding to the bidirectional terminal,
It is a part that is classified and declared as a component type such as a signal corresponding to a connection signal and a signal corresponding to a storage element such as a register. For example, "output" declares a signal corresponding to the output terminal of the module M2. In this case, the following "res, stst" is the signal.

On the other hand, the portion indicated by c in FIG.
2 represents the operation of the module M2 as a basic operation based on data transfer and operation between registers. This part is composed of a plurality of statements (statements) representing one integrated operation. For example, a part indicated by an arrow in the figure d is one statement.

Next, a method of dividing / merging the RTL description of a module for which division / merge is specified will be described with reference to FIG.

As shown in FIG. 2, first, in step 11, in the description of the module to be split / merged, the statement of the description part specified in step 4 of FIG. Analyze the reference relationship between the input signal and the output signal of the module and input signals for the statement group of the specified description part (signals are substituted in statements of other parts and refer to the signals. ) And the output signal (the signal in which the signal is substituted in the statement, and the other signal is referenced in other parts).

Next, in step 12, the component types of the input signal and the output signal of the statement group of the designated description portion, which are grasped in step 11 described above, for example, the signal corresponding to the input terminal, the output terminal A corresponding signal, a signal corresponding to a bidirectional terminal, a signal corresponding to a connection signal, a signal corresponding to a storage element such as a register, and the like are determined and classified.

Next, in step 13, a declaration portion indicating the component type of each signal determined and classified in step 12 is created. Specifically, the input signal, the input terminal, the bidirectional terminal, the signal corresponding to the connection signal, the signal corresponding to the storage element such as the register, etc. of the original module, and the input signal of the statement group of the specified description portion And a signal serving as an output signal, and a signal which is a statement group in which a statement group of a specified description section is exchanged with a statement group other than a specified statement section, and is a new input of a statement group of the specified description section. Create declarations for signals that will be terminals, output terminals, and bidirectional terminals. That is, in this step 13, when the statement group of the specified description portion is divided or merged from the original module to form a new module, a portion that becomes a declaration portion of the new module is created. become.

Next, at step 14, the statement group of the specified description portion is extracted from the description of the original module, and is described following the declaration portion created at step 13 above. Here, one new module is created.

Next, in step 15, the statement portion of the description portion other than the specified portion of the description of the module to be divided / merged is created in the same manner as described above.

Next, in step 16, the statement group of the description portion other than the designated portion is extracted from the description of the original module, and is described following the declaration portion created in step 15 above.

Finally, the description of the upper module of the module to be split / merged is corrected after the split / merge, and the process ends.

Next, an RT having a specific module hierarchical structure will be described.
The division / merge method will be further described using an L description. Here, the case of division will be described.

For example, based on given specifications, FIG.
It is assumed that the RTL description of the module hierarchical structure shown in FIG. Here, “TOP, M1 to M” in FIG.
4, M11 to M14, M21 to M24, M31 to M3
3, M41 to M43 "mean modules, respectively.
“TOP” is the top module, “M1 to M4” is the module below it, “M1 to M4, M11 to M14, M2”
1 to M24, M31 to M33, and M41 to M43 "are the lowest modules.

First, the steps shown in FIG.
Then, the RTL description shown in FIG. 4 is read, and its hierarchical structure is traced.

Then, in the step 3, the traced module hierarchical structure is displayed, and a module to be divided is specified based on the displayed hierarchical structure. Here, if the module M2 is designated, the module M2
2 are displayed as shown in FIG.

From the displayed RTL description of the module M2, for example, the designer designates a part to be divided into one new module based on his / her knowledge and experience.
Here, it is assumed that the portion indicated by e in the figure is designated. The designated part is displayed in reverse video.

Next, the module M2 designated as a division target in step 5 and the modules M21, M22, M23, M2 which are lower modules of the module M2.
The number of gates of 4 is estimated. FIG. 6 shows the number of gates of the module M2 and its lower modules M21 to M24 for each module. Here, in the display of the number of gates of the module M2, "405K" (portion indicated by f in the figure) shown in the upper part thereof is the module M2.
Is the total number of gates of all the lower modules and components and statements existing in the module M2, that is, the total number of gates of the circuit components of the module M2. Further, “(350K)” (the portion indicated by g in the figure) shown in the lower part is the total number of gates of all lower modules included in the module M2. On the other hand, FIG. 7 is a display of the number of gates of the description portion e specified in step 4 above. “55K” (portion indicated by l in the figure) indicates all lower-level modules included in the statement group of the description portion e and their lower-level modules. This is the total number of gates of both components and statements existing in the statement group, that is, the total number of gates of the circuit components of the description part e. Also, "(0K)" (portion indicated by m in the figure)
Is the total number of gates of all lower modules included in the statement group of the description part e. Then, from the estimation results as shown in FIGS. 6 and 7, it can be determined whether or not the circuit scale after division is appropriate. FIG. 8 divides a portion indicated by e in FIG.
FIG. 9 is a diagram showing an RTL description of a new module, and FIG. 9 is a diagram showing an RTL description of a new module obtained by dividing the portion shown by e in FIG. As shown in FIGS. 8 and 9, a portion indicated by e in FIG. 5 is a module M2A (see a portion indicated by n in FIG. 8), and the other portion is a module M2B (a portion indicated by o in FIG. 9). reference). Further, as shown in FIG. 10, the RT of the module TOP, which is an upper module of the module M2,
Part of the L description is modified. That is, the part indicated by p in FIG. 10 is a description about the module M2 before the division, but is a description about the module M2A and the module M2B.

The RTL description module generation support method according to the present embodiment described above can be realized by, for example, an apparatus having a hardware configuration and a software configuration as shown in FIG. The hardware configuration includes a central processing unit CPU (not shown) for performing various processes, an input device 3 such as a keyboard, a mouse, a light pen, or a flexible disk device, and external storage such as a memory device and a disk device. An ordinary computer system including the device 5 and the output device 7 such as a display device and a printer device may be used. The central processing unit CPU includes an arithmetic unit that performs various types of processing, and a main storage unit that stores instructions for the processing.

On the other hand, the software configuration includes RTL description reading means 9 for reading the once determined RTL description,
A module hierarchical structure tracing means 11 for tracing the module hierarchical structure of the read RTL description, and an RTL for displaying a specific RTL description of the specified module
Description display means 13, gate number estimating means 15 for estimating the number of gates of a predetermined module and its lower modules, and the number of gates of a predetermined statement group and its lower modules, and a gate number evaluation result based on a predetermined criterion A gate number estimation result determining means 17 for determining whether or not it is appropriate; and an R for actually dividing / merging the RTL description
TL description division / merge means 19.

As described above, according to the present embodiment, an RTL description module having a hierarchical structure once determined by a designer based on given specifications is divided and merged before logic synthesis or floor planning, and these are merged. By making the circuit scale suitable for logic synthesis and floor planning, logic synthesis and floor planning can be performed easily and quickly.

[0049]

As described above, according to the present invention,
If the gate scale of the RTL description module once created is not appropriate for performing logic synthesis and floor planning, division or merging is performed before actually performing logic synthesis or the like, and a gate scale suitable for logic synthesis or the like is performed. Modules can be automatically generated.

Furthermore, since the division / merging is performed before the actual logical synthesis is performed, the design time can be reduced as compared with the conventional case where the logical synthesis is performed once and then the division / merge is performed. And the consistency of splitting / merging will be maintained.

With the increase in the scale of the logic LSI, it is becoming difficult to perform division and merging manually, and the present invention is very effective in improving design efficiency.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure of a register transfer level (RTL) description module generation support method according to an embodiment of the present invention.

FIG. 2 is an RTL of a module in which division / merge is specified;
9 is a flowchart illustrating a processing procedure of a description dividing / merging method.

FIG. 3 is a diagram illustrating an example of a module represented by an RTL description.

FIG. 4 is a diagram illustrating an example of a module hierarchical structure of an RTL description.

FIG. 5 is a diagram showing an example of a case where a specific RTL description of a module specified in step 3 of FIG. 1 is displayed.

FIG. 6 is a diagram showing an example in which the result of estimating the number of gates of the module M2 and the number of gates of lower-order modules in step 5 of FIG. 1 is displayed.

FIG. 7 is a diagram showing an example in which an estimation result of the number of gates of a description portion e designated in step 4 of FIG. 1 is displayed.

FIG. 8 is a diagram showing an RTL description of a new module obtained by dividing the portion indicated by e in FIG. 5;

FIG. 9 is a diagram showing an RTL description of a part obtained by dividing a part indicated by e in FIG. 5 as a new module;

FIG. 10 is a diagram showing a result of correcting a part of an RTL description of a module TOP which is an upper module of the module M2.

FIG. 11 is a diagram showing a configuration of a register transfer level description module generation support device according to an embodiment of the present invention.

FIG. 12 is a diagram for explaining a problem of the related art.

FIG. 13 is a diagram for explaining a problem of the related art.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 register transfer level description module generation support device 3 input device 5 external storage device 7 output device 9 RTL description reading means 11 module hierarchical structure tracing means 13 RTL description display means 15 gate number estimation means 17 gate number estimation result determination means 19 RTL description Split / merge means

Claims (4)

[Claims] When a given register transfer level description module is divided or merged, a module to be divided or merged is divided so that a new module generated after the division or merging has a predetermined gate size. A register transfer level description module generation supporting method, wherein a part is extracted from a register transfer level description, and a new module is automatically generated from the extracted description part. 2. When a given register transfer level description module is divided or merged, the number of gates of a module to be divided or merged, the number of gates of lower modules thereof, and the number of gates of a module to be divided or merged are defined. A process of extracting a part of the register transfer level description and estimating the number of gates of a module newly generated and the number of gates of its lower modules from the extracted description part is performed. A method for automatically generating a new module from a description portion extracted as a result, the register transfer level description module generation method. 3. When a new module is generated from the extracted description part, an input signal and an output signal of a statement group constituting the extracted description part are grasped, and the grasped input signal and Determines and classifies the component type of the output signal, creates a declaration portion indicating the component type of each of the determined and classified input signal and output signal, and generates a statement group of the description portion extracted from the created declaration portion. Write and create one module from the extracted description parts, grasp the input signals and output signals of the statement group that constitutes the remaining description part after being extracted, and grasp the grasped input signals and output signals. The component types of the input signal and the output signal that have been determined and classified are indicated. Create a declaration part, describe the statements of the remaining description part after extraction in the created declaration part, create one module from the remaining description part after extraction, and further divide 3. The register according to claim 1, wherein when a higher-level module is present in the module to be merged, the register transfer level description of the higher-level module is modified in accordance with a result after division or merging. Generation support method of transfer level description module. 4. A register transfer level description reading means for reading a given register transfer level description, a module hierarchical structure tracing means for tracing a module hierarchical structure of the read register transfer level description, and a register transfer of a specified module. Register transfer level description display means for displaying the level description, the number of gates of the specified module and its lower modules, and the number of gates of the description part extracted from the register transfer level description of the specified module and its lower module Means for estimating the number of gates, means for estimating the number of gates, and means for estimating the result of the number of gates for judging whether or not the result of the number of gates has a predetermined gate size; Register transfer level description module generation supporting apparatus characterized by having a register transfer level description division and merging means for performing split or merge.