JPH11175459A - Bus operation transfer method, system therefor and computer readable medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform fast transfer of a bus operation that is strictly ordered by deciding whether or not at least one processor receives the 1st response to the 1st bus operation. SOLUTION: Plural bus operation, e.g. storage elements are issued from processors 102a to 102c. When the 1st response which shown that one of the bus operations should be issued again is received by the processor 102a to 102c and when it shows that one of issued bus operations is issued again, 2nd response which shows that at least another of the issued bus operations is issued again is issued from the processors 102a to 102c. The 2nd response is called self-retrial response. The processor 102a to 102c provide self-retrial response to all of bus operation requests that are issued after bus operation requests which are issued after a bus operation request that receives the first retrial response.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the transfer of information in a processing system, and more particularly, to a system and method for rapidly transferring bus operations, which are preferably strictly ordered.

[0002]

2. Description of the Related Art Multiprocessor systems are now commonly used in business and research environments. When a processor in a multiprocessor system requests access to memory, an arbiter is typically used to determine which data requests are granted and in what order. These requests from the processor and grants from the arbiter are usually carried by the system bus.

[0003] Information is usually marked with either "cacheable", "cache prohibited" or "write-through". If the information is marked as cacheable, the data can be stored in cache without having to transfer it to system memory. However, if the information is marked as non-cacheable,
The data cannot enter the cache and must be transferred somewhere else, for example, to system memory. An example of an application that frequently uses cache-inhibited store instructions is a graphics application. If the information is marked write-through, the information goes to its destination as well as the cache. Some of the cache inhibit or write-through information is usually a strictly ordered bus operation.

[0004] Computer systems that use the PowerPC ™ processor employ a strictly ordered bus architecture.
It must be ensured that the operations are issued to the receiving device in exactly the same order as they are performed from the processor. Computer systems using Amazon PowerPC ™ may require a strict ordering of all operations.

A typical bus interface device (BI)
U) The design queues strictly ordered bus operations, such as cache-inhibited storage, requests buses for address and data transfers, issues a first bus operation when given a bus, and responds. Wait for. If the address is accepted (not retried) and the data has been transferred, the BIU requests the bus for the next sequential bus operation. The number of cycles that the BIU must wait for a response is usually system dependent. However, the delay between transfers of ordered bus operations is directly reflected in sub-optimal performance. Furthermore, if the system can achieve good throughput of ordered bus operations, the system can achieve higher industry standard benchmarks.

[0006]

Therefore, what is needed is a system and method for high speed transfer of strictly ordered bus operations. The present invention addresses such a need.

[0007]

SUMMARY OF THE INVENTION A system and method are provided for high speed transfer of bus operations, which are preferably strictly ordered in a processing system. The system and method of the present invention provide for issuing multiple bus operations by a processor and determining whether a first response indicating that one of the multiple bus operation requests should be reissued is received by the same processor. Judge. And
If the first response is received, the processor issues a second response indicating that at least another one of the issued bus operation requests should be reissued.

[0008] In another aspect of the invention, a system and method for transferring bus operations using a bus in a processing system includes at least one processor capable of gaining control of the bus. The system and method of the present invention include issuing a plurality of bus operation requests by at least one processor, issuing a bus operation, and providing a response indicating that the issued bus operation should be reissued. Determining whether it has been received by at least one processor;
Holding control of the bus by the plurality of processors and, if a response is received indicating that the bus operation is to be reissued, reissuing the bus operation.

In yet another aspect of the present invention, a system and method for transferring bus operations in a processing system including at least one processor includes:
The at least one processor issues a plurality of ordered bus operations including a first bus operation and a second bus operation, issues a first bus operation, and then issues a second bus operation. Including emitting in this manner. This also indicates that a first response to the first bus operation is received by the at least one processor, indicating that the first bus operation can be transferred before issuing the second bus operation. Judge whether or not. If a first response to the first bus operation is received by at least one processor before issuing the second bus operation,
A signal is issued with the second bus operation, wherein the signal indicates that the processor does not issue a second response to the second bus operation, and the second response is a second bus operation. Should be reissued.

[0010] The systems and methods of the present invention significantly improve bus operation performance.

[0011]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system and method for high-speed transfer of bus operations, preferably strictly ordered bus operations, in a processing system. The following description is presented to enable one of ordinary skill in the art to make and use the invention, and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the general principles disclosed herein may be applied to other embodiments. Accordingly, the present invention is not limited to the embodiments shown, but has the broadest application consistent with the principles and features described herein.

For purposes of illustration, the present disclosure will refer to a cache-inhibited store operation as an example of a strictly ordered bus operation. It will be understood, however, that the discussion of cache-inhibited store operations is merely an example of the method and system of the present invention, and that the methods and systems described herein apply generally to strictly ordered bus operations.

FIG. 1 is a block diagram of a multiprocessor system to which the present invention is applied. System 100
Are processors each including a cache (hereinafter referred to as processors 102a to 102c), a system bus 1
04, a memory controller 106, an arbiter 108, and a memory 110.

Computer systems using multiple processors 102a-102c often have a memory controller 106 via a heavily loaded address bus 104.
, And is designed with a number of bus masters, which may be processors 102a-102c. Each bus master has one processor 102a-102c
Or a combination of the processor 102 and a cache that must communicate with the memory controller 106 via a bus interface device, also called an arbiter 108, which must be arbitrated for memory resources. The arbiter 108 may be internal or external to the memory controller 106. The memory controller can be coupled to a network.

The system 100 shown in FIG. 1 can be referred to while considering the flowchart shown in FIG. FIG.
4 is a flowchart of a conventional method for transferring a cache-inhibit storage instruction. First, in step 200, an address request is issued from the processor. Some time later, at step 202, the processor receives address permission. Then, step 20
The processor issues an address at 4 and waits until an address response is received at step 206. Address responses for cache-inhibited storage are typically either "clean" or "retry". A "clean" response indicates that the bus operation can be transferred. A "retry" response indicates that the bus operation should be reissued.

Then, in step 208, it is determined whether the address response is "clean". If the response is not "clean", at step 210, the processor retries sending the address. But step 2
If the response is "clean" at 08, step 21
At 2, it is determined whether data for the address has been issued. At step 212, if data for the address has not yet been issued, the system waits until it has been issued. When data for an address is issued,
At step 214, a next address request can be issued.

FIG. 3 is a timing chart of the conventional method shown in FIG. The processor issues an address request as indicated by signal 300. After a while, address permission is received via signal 302. Then, an address is issued via a signal 304. After some time, an address response is received by the sending processor. In this example, a "clean" response is received via signal 312.

The processor may issue a data request via signal 306 either simultaneously with or after the address request. Later, at step 308, a data permission is received and the processor emits the data via signal 310. Only after the data 310 and the "clean" address response 312 have been received by the processor can the next address request be issued via signal 314.

As mentioned earlier, this delay is directly reflected in sub-optimal performance. What is required is
A system and method for high-speed transfer of ordered bus operations in a processing system, such as cache-inhibited store instructions. The present invention addresses such a need.

FIG. 4 is a flow chart of the method of the present invention. At step 400, a plurality of bus operations, such as a storage request, are issued by a processor. As discussed above, bus operations, eg, store-inhibit cache instructions, are preferably strictly ordered. Then, at step 402, the plurality of buses
It is determined whether a first response has been received by the processor indicating that one of the operations should be reissued. If the first response is received indicating that one of the issued bus operations should be reissued, then at step 404, at least another one of the issued bus operations should be reissued. A second response is issued from the processor indicating that This second response from the processor indicating that at least another one of the issued bus operations should be reissued is referred to herein as a "self retry" response. Preferably, the processor provides a "self retry" response for all bus operation requests issued after the first "retry" response received bus operation request. The method of the present invention is particularly useful for use with cache-inhibited store instructions.

FIG. 5 is a timing diagram of the method of the present invention. The processor in the processing system receives an address request 500
a to 500b constantly emitted. The processor then receives address permissions 500a-500b. afterwards,
The processor issues addresses 500a-500b.

In the example shown in the timing diagram of FIG. 5, a "clean" address response 506a is
Is received by the processor at about the same time that is issued. However, at the same time that the address request 500d is issued, a "retry" address response 506b is received. Once the "retry" response 506b is received, the next address request 500b 'is again provided. Request 500
b 'corresponds to the same address that received the first "retry" response 506b. In other words, the same address is emitted again by signal 504b '. Furthermore,
The sending processor may also receive a "self retry" response 5 for any other address issued before or at about the same time as the first "retry" response 506b received by the sending processor.
08b. It is noted that the sending processor itself provides its own "self retry" response 508a.

The sending processor sends the address 504b '
Again, then re-issue another address that was issued before or at about the same time as receiving the first "retry" response 506b. Therefore, addresses 504c 'and 5
04d 'is reissued, preferably in the first order in which it was issued.

Once a clean response 506c is received, a next address request 500e is issued.

The data request 510 is an address request 500
Issued at the same time or later. Data permission 51
2 are received after their corresponding request 510 has been issued. Thereafter, data 514 can be emitted.

It will be noted that the "self-retry" responses 508a-508b maintain address ordering and data integrity. In contrast, the conventional method
Ordering is maintained by not presenting a new address until both a "clean" response and a data transfer have occurred.

The system and method of the present invention maintains bus operation ordering while significantly improving ordered bus operation performance, eg, cache-inhibited storage performance. The use of pointers allows the bus interface device to issue operations, such as address recording and data storage, independently and as quickly as the bus protocol allows. If a "retry" occurs, the pointer resets and returns to the retried storage address and data entry and starts over. Then, after the first "retry" has been received, the BIU will retry the address it originated.

FIG. 6 is a flowchart of the second embodiment of the present invention. A second embodiment is a system that operates with a bus master, such as a processor, that issues a bus operation, such as a 60X bus, of a type designed to allow a processor to retain control of the bus until it abandons. Is the way. Other types of buses, such as the 6xx bus, typically allow a bus master to hold use of the bus for a limited period of time, for example, one cycle.

According to a second embodiment, a bus master,
For example, the requesting processor issues a request for the current address as well as a request for the next address in the queue to issue. The bus control is maintained until the processor receives a response. By the time the response is received, a request for the next address should have already been issued and the address is
Either the permit has been issued or it is already being issued. In this way, the system and method of the second embodiment improves bus operation transfer performance.

As shown in the flowchart of FIG.
At 0, first and second bus operation requests are issued by the processor. Then, in step 602, a first bus operation is issued. Then, in step 604, it is determined whether a response has been received by the processor, and the process of obtaining control of the bus to initiate another bus operation begins prior to receiving the response.

FIG. 7 is a timing chart for explaining the second embodiment of the present invention. As shown by the timing diagram, two address requests are issued sequentially, and as shown, address grants are received sequentially. Address A is issued and the bus master, in this example, the sending processor, retains control of the bus until it receives a response to address A, in this example, a "clean" response.

The next address request 700b is issued between the time when the requesting processor issues the address request 700a for the address A and the time when the response 702a for the address A is received. In this example, the provisional address permission 70 of the address request 700b is not received until the response 702a is received.
4 have been received. As a result, the requesting processor
Control of the bus of the address B can be promptly obtained.

Another request 700c has been issued before the response 702b of the address B is received. Since the response of address B is "retry", control of the bus is held until address B is issued again and the next response 702c is received.

This process continues until the last address in the queue has been issued. In this example, the last address is specified. After an address request for address D is issued, no further requests are issued unless another address is enqueued to issue or address D receives a "retry" response.

FIG. 8 is a flowchart of the third embodiment of the present invention. This third embodiment works with the first embodiment shown in FIGS. After the requested address has been issued, the memory controller 106 of FIG. 1 can send the address as soon as possible, for example to a network. However, according to the first embodiment shown in FIGS. 4 and 5, there is an opportunity for the address to be "self-retrialed" by the sending processor. If the address is "self-retried" after the memory controller has transferred the address, problems may arise with regard to address ordering.

A third embodiment of the present invention avoids this problem by adding a signal to the selected address to indicate to the memory controller that the selected address is not "self retried". I do. Therefore, the memory controller can transfer the selected bus operation as quickly as possible. It will be noted that the memory controller can still send a "retry" response to the sending processor for the selected address. In this manner, strict ordering can be maintained while transferring ordered bus operations quickly.

As shown in FIG. 8, at step 800, a plurality of bus operations are issued by a bus master, in this example, a processor. As in other embodiments,
The bus operations are preferably strictly ordered. The plurality of ordered bus operations includes first and second bus operations, where a first bus operation is issued followed by a second bus operation. And step 8
At 02, before issuing a second bus operation, it is determined whether a "clean" response of the first bus operation has been received and recognized by the processor. "Recognize" means that the processor has enough time to note that it has received a "clean" response and can stop further dispatching of further addresses. Before issuing the second bus operation,
If a "clean" response for the first bus operation has been received and recognized by the processor, a signal is issued at step 804 along with the second bus operation. The signal indicates that the processor does not issue a "self retry" for the second bus operation.

FIG. 9 is a timing chart of the third embodiment shown in FIG. For address A, an address request is issued and an address grant is issued. Then, a "clean" address response is received. After a "clean" response is received and recognized by the processor, an address request and an address grant for address B are issued by the processor. Then, a signal 900 is transmitted together with the address B, and the master controller issues an address B
May not be "self retried". Signal 900 is preferably sent with an address only if a "clean" response has been received and recognized by the processor before issuing the next address. Thereafter, addresses C, D and E are issued by the processor and again with a "retry" response for address C. Note that because there is no "clean" response received and recognized by the processor before issuing the next address, addresses C, D and E are not accompanied by a signal indicating that these addresses are not "self-retried". To do. Thus, a signal indicating that a "self retry" response will not be issued is preferably not issued, but only associated with an address that is issued after a sufficient time to receive and recognize a "clean" response. .

A system and method for high-speed transfer of ordered bus operations has been disclosed. Software written in accordance with the present invention may be stored on some form of computer readable medium, such as a memory or CD-ROM, or transmitted over a network and executed by a processor.

Although the invention has been described with reference to the illustrated embodiments, those skilled in the art will readily recognize that modifications to the embodiments are possible and that such modifications fall within the spirit and scope of the invention. Will do. Accordingly, many modifications may be made by one skilled in the art without departing from the spirit and scope of the appended claims.

In summary, the following matters are disclosed regarding the configuration of the present invention. (1) A method for transferring a bus operation in a processing system including at least one processor, the method comprising: (a) including, by the at least one processor, a first bus operation and a second bus operation. Issuing a plurality of ordered bus operations such that the first bus operation is issued and then the second bus operation; and (b) prior to issuing the second bus operation. Determining whether a first response to the first bus operation has been received by the at least one processor, indicating that the first bus operation can be transferred; (c) ) A step for signaling with said second bus operation; Wherein the signal indicates that the processor does not issue a second response to the second bus operation, and the second response re-initiates the second bus operation. Indicating that a signal should be issued and providing the signal if the first response to the first bus operation is received by the at least one processor before issuing the second bus operation. Method. (2) The method of (1), wherein the plurality of bus operations are strictly ordered. (3) The method according to (1), wherein said bus operation is a store operation. (4) The method according to (1), wherein the bus operation is a cache-inhibited storage operation. (5) A computer-readable medium containing program instructions for transferring bus operations in a processing system including at least one processor, the program instructions comprising:
(A) generating, by the at least one processor, a plurality of ordered bus operations including a first bus operation and a second bus operation, the second bus operation after issuing the first bus operation; Means for issuing such a bus operation; and (b) said first bus operation indicating that said first bus operation can be transferred prior to issuing said second bus operation. Means for determining whether a first response to an operation has been received by the at least one processor;
(C) means for issuing a signal with the second bus operation, wherein the signal does not cause the processor to emit a second response to the second bus operation. The second response indicates that the second bus operation should be reissued, and the first response to the first bus operation prior to issuing the second bus operation. A computer readable medium providing said signal if said response is received by said at least one processor. (6) A system for transferring bus operations in a processing system including at least one processor, the system comprising:
For issuing a plurality of ordered bus operations, including a first bus operation and a second bus operation, such that the first bus operation is issued and then the second bus operation is issued. Means for transmitting the first bus operation prior to issuing the second bus operation, wherein the first response to the first bus operation indicates that the at least one bus operation can be transferred. To determine if it was received by the processor,
Means coupled to the means for issuing, and means for emitting a signal with the second bus operation, wherein the signal is transmitted to the processor by the processor for a second signal to the second bus operation. And the second response indicates that the second bus operation should be reissued, and the first bus before issuing the second bus operation.・
If the first response to an operation is received by the at least one processor, the signal is provided and the originating means is coupled to the determining means. (7) A method for transferring a bus operation in a processing system including at least one processor, the method comprising: (a) including, by the at least one processor, a first bus operation and a second bus operation. Issuing a plurality of ordered bus operations such that the first bus operation is issued and then the second bus operation; and (b) one of the plurality of bus operations is issued. Determining if a first response indicating that it should be reissued has been received by the at least one processor; and (c) if the first response has been received, the issued bus A second response indicating that at least another one of the operations should be reissued; Issuing from at least one processor; and (d) for said first bus operation indicating that said first bus operation can be transferred prior to issuing said second bus operation. Determining whether a third response has been received by the at least one processor; and (e) issuing a signal with the second bus operation, wherein the signal is transmitted by the at least one processor. Indicating that the processor does not issue the second response to the second bus operation, and the response to the first bus operation is less than the at least If received by one processor,
A method for providing the signal. (8) A computer-readable medium including program instructions for transferring bus operations in a processing system including at least one processor, the program instructions comprising:
(A) generating, by the at least one processor, a plurality of ordered bus operations including a first bus operation and a second bus operation, the second bus operation after issuing the first bus operation; Means for issuing such a bus operation; and (b) whether a first response indicating that one of said plurality of bus operations should be issued again is received by said at least one processor. Means for determining if the first response has been received, the second response indicating that at least another one of the issued bus operations should be reissued. Means for issuing from one processor; and (d) prior to issuing said second bus operation, said first bus. Means for determining whether a third response to the first bus operation has been received by the at least one processor, indicating that the operation can be transferred; and (e) the second bus. Means for issuing a signal with operation, said signal indicating that said at least one processor does not emit said second response to said second bus operation, If the response to the first bus operation is received by the at least one processor before issuing a second bus operation,
A computer readable medium providing the signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiprocessor system to which the present invention is applied.

FIG. 2 is a flowchart of a conventional bus operation transfer method.

FIG. 3 is a timing chart of the conventional method shown in FIG. 2;

FIG. 4 is a flow chart of the method of the present invention for high-speed transfer of ordered bus operations.

FIG. 5 is a timing diagram of the method of the present invention.

FIG. 6 is a flowchart of a second embodiment of the present invention.

FIG. 7 is a timing chart of the second embodiment of the present invention.

FIG. 8 is a flowchart of a third embodiment of the present invention.

FIG. 9 is a timing chart of the third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 100 system 102a to 102c processor 104 system bus 106 memory controller 108 arbiter 108 110 memory

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification FI G06F 15/16 360 G06F 15/16 360Z (72) Inventor John Stephen Dotson United States 78660 USA Fraggerville Bell Rock, TX Circle 1205 (72) Inventor Ravi Khmer Al-Milli, United States 78759, Austin, TX Spicebrush Drive 9221

Claims (8)

[Claims] 1. A method for transferring a bus operation in a processing system including at least one processor, comprising: (a) a first bus operation and a second bus operation by the at least one processor; Issuing a plurality of ordered bus operations including issuing the first bus operation and then issuing the second bus operation; and (b) issuing the second bus operation. Before firing
Determining whether a first response to the first bus operation has been received by the at least one processor, indicating that the first bus operation can be transferred; and Issuing a signal with a second bus operation, the signal indicating that the processor does not issue a second response to the second bus operation; Indicates that the second bus operation should be reissued, and the first response to the first bus operation is prior to issuing the second bus operation. Providing the signal if received by 2. The method of claim 1, wherein said plurality of bus operations are strictly ordered. 3. The method of claim 1, wherein said bus operation is a store operation. 4. The method of claim 1, wherein said bus operation is a cache inhibited store operation. 5. A computer readable medium containing program instructions for transferring bus operations in a processing system including at least one processor, the program instructions comprising: (a) A plurality of ordered bus operations, including a first bus operation and a second bus operation, are issued by the at least one processor to the second bus operation after issuing the first bus operation. Means for issuing in such a manner that: (b) prior to issuing said second bus operation,
Means for determining whether a first response to the first bus operation has been received by the at least one processor, indicating that the first bus operation can be transferred; and (c) Means for issuing a signal with a second bus operation, the signal indicating that the processor does not emit a second response to the second bus operation; The second response indicates that the second bus operation should be reissued, and the first response to the first bus operation is prior to issuing the second bus operation. A computer-readable medium that provides the signal if received by at least one processor. 6. A system for transferring bus operations in a processing system including at least one processor, wherein the at least one processor causes a first bus to be transferred.
Means for issuing a plurality of ordered bus operations including an operation and a second bus operation, such that the first bus operation is issued and then the second bus operation is issued; and Whether a first response to the first bus operation was received by the at least one processor indicating that the first bus operation can be transferred before issuing a second bus operation Means for determining whether to issue a signal in conjunction with the means for emitting; and means for emitting a signal with the second bus operation, wherein the signal is transmitted by the processor to the second bus. Indicating that a second response is not issued to the operation, wherein the second response is Indicating that the second bus operation should be reissued, wherein the first response to the first bus operation is received by the at least one processor before issuing the second bus operation. If so, the signal is provided and the transmitting means is coupled to the determining means. 7. A method for transferring a bus operation in a processing system including at least one processor, comprising: (a) a first bus operation and a second bus operation by the at least one processor. Issuing a plurality of ordered bus operations including issuing the first bus operation and then issuing the second bus operation; and (b) one of the plurality of bus operations. Determining whether a first response indicating that one should be reissued has been received by the at least one processor; and (c) if the first response has been received, issuing the first response. A second response indicating that at least another one of the failed bus operations should be reissued. A step of emitting from the at least one processor, prior to issuing (d) is the second bus operation,
Determining whether a third response to the first bus operation has been received by the at least one processor indicating that the first bus operation can be transferred; and Issuing a signal with a second bus operation, the signal indicating that the at least one processor does not emit the second response to the second bus operation; Prior to issuing the second bus operation, the response to the first bus operation may be
Providing the signal if received by a plurality of processors. 8. A computer-readable medium containing program instructions for transferring bus operations in a processing system including at least one processor, the program instructions comprising: (a) A plurality of ordered bus operations, including a first bus operation and a second bus operation, are issued by the at least one processor to the second bus operation after issuing the first bus operation. And (b) determining whether a first response indicating that one of the plurality of bus operations should be reissued has been received by the at least one processor. (C) if the first response is received, the Means for issuing from the at least one processor a second response indicating that at least another one of the selected bus operations should be reissued; and (d) prior to issuing the second bus operation. ,
Means for determining whether a third response to the first bus operation has been received by the at least one processor, indicating that the first bus operation can be transferred; and (e) Means for issuing a signal with a second bus operation, said signal not causing said at least one processor to emit said second response to said second bus operation. A computer readable medium for providing the signal if the response to the first bus operation is received by the at least one processor prior to issuing the second bus operation.