JPH11168178A - Integrated circuit element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformize wiring path lengths of multifingered FETs by a method wherein the source, gate and drain electrodes of a plurality of selected circuit FETs are respectively connected commonly with each multifinger FET to constitute a plurality of the multifingered FETs, and the unit FETs adjacent to each other in FET rows are constituted as ones to belong to the different multifingered FETs. SOLUTION: Multifingered FETs 101 to 104 are respectively constituted of four unit cells of a unit cell 101 (a to e), a unit cell 102 (a to e), a unit cell 103 (a to e) and a unit cell 104 (a to e). The order of the arrangement of the unit cells are set in the order of the unit cells 101a, 102a, 103a, 104a, 101b, 102b and 103b. Drain electrodes of the multifingered FETs 101 to 104 are connected with a drain terminal 110 which is wired in common, gate electrodes 121 to 124 of the FETs 101 to 104 are connected with a gate resistor, and source electrodes 111 to 114 of the FETs 101 to 104 are connected with an output terminal. The wiring path lengths of the four multifingered FETs as seen from an input terminal (the drain electrode 110) can be made equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an integrated circuit device. More specifically, the invention relates to a source, a gate,
The present invention relates to an integrated circuit device having a unique layout when providing a plurality of multi-finger type field effect transistors, each of which is an aggregate of unit FET devices each including a drain electrode and a drain electrode.

[0002]

2. Description of the Related Art Wireless LAN (Local Area N)
network and PHS (Personal Hand)
Among various integrated circuit elements for realizing a system such as a y-phone system, a power amplifier of a transmission system and a transmission / reception switch are field-effect transistors (hereinafter referred to as “FETs”) for handling large power signals.
) Often exceeds 1 mm. An FET having a total gate width of 1 mm or more has a gate width of 100 μm.
This is realized by a layout configuration called “multi-finger type” in which unit FETs of m to 200 μm are arranged in parallel.

FIG. 7 is a schematic pattern diagram showing a typical layout of a conventional multi-finger type FET. That is, the FET shown in FIG.
This is a typical example of a multi-finger FET having a total gate width of about 1 mm formed on a substrate such as i) or gallium arsenide (GaAs), and shows a configuration in which ten unit FETs are arranged in parallel. Adjacent unit FETs share a source electrode or a drain electrode disposed therebetween. Each electrode is composed of a finger portion and a connection portion, the gate electrode is a gate finger 411 and a gate connection portion 412, and the source electrode is a source finger 4
21, the source connection portion 422, and the drain electrode
It is constituted by the finger 431 and the drain connection portion 432.

[0004] In this specification, as shown in FIG. 7, a “unit FET” refers to an FET portion constituted by a pair of a source finger, a gate finger, and a drain finger adjacent to each other. It shall be pointed out. As shown in the figure, by arranging a plurality of unit FETs in parallel and wiring them in parallel, the current capacity of the FETs can be increased and a large power signal can be handled.

[0005]

However, when a switching circuit of a plurality of channels is formed by using the conventional multi-finger FET as described above, there is a problem that the signal line length differs for each channel and a deviation occurs in transmission characteristics. there were. In the following, a description will be given of an example in which a multi-finger FET is used as a transfer gate FET of a one-input multi-output port switch.

FIG. 8A is a schematic circuit diagram of a one-input / multi-output port switch. That is, FIG. 1 shows a 1-input, 6-output port switch (hereinafter referred to as “SP6T (Single Port)” used in a wireless LAN adopting a sector configuration.
6 Throw) switch. 2) illustrates the circuit of FIG. The input terminal 310 is connected to output terminals 311 to 311 via transfer gate FETs 301 to 306.
16 is connected. As will be described later, in an actual integrated circuit device, these transfer gates FE
Each of T301 to T-306 is “multi-finger FE
T ".

The power supply voltage terminal 300 has a pull-up resistor 3
It is connected to the input terminal 310 via 40. The gate signal input terminals 331 to 336 are connected to the gate resistors 341 to 341.
46, transfer gate FETs 301-31
6 are connected to the gate electrodes 321-326. These gate resistors 341 to 346 are for preventing leakage of a high-frequency signal at the time of a switching operation, and the gate of each FET requires a high resistance of several KΩ.

Further, the transfer gate FET 30
An inductor 3 that resonates with the off-capacity of the FET is provided between the source electrode and the drain electrode 1 to 306.
51 to 356 have a resonance-type configuration connected in parallel.
The merit of this configuration is that when the transfer gate FET is off, the off-capacitance of the FET and the inductor resonate in a predetermined frequency band and the impedance of the transmission path becomes very large. It can be achieved.

Next, the operation of this switch will be described. When 3 volts are applied to the gate signal input terminal 331 and 0 volts are applied to the other gate signal input terminals 332 to 336, only the transfer gate FET 301 is turned on (O
N) and other transfer gate FETs 302-
306 turns off. When a high frequency signal is input from the input terminal 310 in this state, the transfer gate FET 3
A signal is output to the output terminal 311 via the “01”. At this time, the signal input from the input terminal 310 receives the loss due to the on-resistance of the transfer gate FET 301 and the loss leaking through the off-source capacitance between the source / drain of the transfer gate FETs 302 to 306 on the off side. , The signal from which these losses are subtracted is output from the output terminal 311
Output from In the case of a 1-input multi-output port switch,
The input signal line tends to be longer as the number of output ports increases.

FIG. 8B is a circuit diagram illustrating an actual circuit of the SP6T switch. As shown in the figure, the actual circuit is represented as having transmission lines 371 to 375 arranged between the input terminal 310 and the drain electrodes 361 to 366 of each FET. Then, as can be seen from FIG.
06, the number of transmission lines arranged for each FET differs.

FIG. 9 is a pattern diagram showing an example of the layout of the SP6T switch. The chip size of the switch shown in the figure is, for example, about 2.7 mm × 1.2 mm. The signal line 380 connected to the input terminal 310
It is located in the center of the chip. On each side thereof, three multi-finger FETs 301 to 306 are arranged,
Each of the drains 361 to 366 is connected to the signal line 380.

Looking at the line lengths of the signal lines between the drain terminals 361 to 366 of these six multi-finger FETs and the input terminal 310, it can be seen that there is a difference in the inductance of the signal lines. For example, the line length between the input terminal 310 and the drain terminal 361 is different from the line length between the input terminal 310 and the drain terminal 363 by about 1.2 mm. Due to such a difference in line length, there is a problem that a large deviation occurs in a loss or the like when each switch is turned on.

As described above, in a conventional integrated circuit device using a multi-finger FET, individual multi-finger FETs are arranged along a signal line and connected to each other, so that the difference in signal line length is different. Was large for each channel, causing a characteristic deviation.

The present invention has been made in view of such a problem. That is, the object is to realize an integrated circuit element in which a difference in signal line length is as small as possible in an integrated circuit element in which a plurality of multi-finger FETs are arranged, so that a deviation in characteristics of each channel is small. Aim.

[0015]

That is, an integrated circuit device according to the present invention is an integrated circuit device in which a plurality of multi-finger FETs are provided on a substrate, and includes a plurality of unit FETs arranged substantially in parallel with each other. At least one FET row is formed on the substrate, and the source and the gate of the plurality of unit FETs selected in the FET row;
And each of the drains is commonly connected to form each of the plurality of multi-finger FETs;
The unit FETs adjacent in the column are configured as belonging to different multi-finger FETs, so that the signal line length of each multi-finger FET can be made uniform and the element size can be reduced. .

A plurality of adjacent unit FETs may be connected to form a unit cell, and the unit cells may be commonly connected to form a multi-finger FET.

Here, by configuring the FET row as the unit cells belonging to each of the plurality of multi-finger FETs are arranged periodically, the signal line length can be easily made uniform. .

Further, when each of the unit cells is constituted by an even number of unit FETs, all adjacent unit FETs can share a source or a drain, thereby further reducing the element size.

Alternatively, the integrated circuit device according to the present invention comprises:
An integrated circuit device in which a plurality of multi-finger FETs are provided on a substrate, and a plurality of unit FETs are arranged on the substrate substantially in parallel with each other so that adjacent unit FETs share either a source or a drain. And each of the source, gate, and drain of a unit FET periodically selected from the plurality of unit FETs arranged is connected in common to form the plurality of multi-fingers F.
Each of the ETs is configured, so that the signal line length of each multi-finger FET can be made uniform and the element size can be reduced.

Here, the plurality of multi-fingers FE
A common line commonly connecting at least one of a source, a gate, and a drain of the T;
By further including a common wiring extending substantially parallel to both sides of the T column and connected to each of the unit cells, the signal line length for each multi-finger FET can be made uniform, and the element layout can be improved. The degree of freedom is further improved.

The same multi-finger FET
A plurality of wirings commonly connecting at least any one of a source, a drain, and a gate of the unit cell belonging to each of the unit cells. By further providing a plurality of wirings connected to the crab, there is an advantage that the element size can be reduced and the degree of freedom of the element layout can be improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

According to the present invention, when laying out a plurality of multi-finger FETs, first, each multi-finger FET is divided into a plurality of "unit cells",
The "unit cells" are arranged alternately.

FIG. 1 is an explanatory view illustrating the order of arrangement of FETs according to the present invention. FIG. 1 illustrates a case where three multi-finger FETs are arranged. Here, each multi-finger FET is denoted by “A”,
"B" and "C". Multi-finger FET
“A” to “C” each have a plurality of unit FETs. According to the present invention, such a multi-finger FE
When laying out T “A” to “C”, first, each multi-finger FET is divided into a plurality of “unit cells”. Here, the “unit cell” may be composed of one unit FET or a plurality of unit FETs. FIG. 1 illustrates a case where the “unit cell” includes two unit FETs. That is, the multi-finger FET “A” is divided into unit cells A1, A2,... Having two unit FETs. Similarly, the multi-finger FET “B” has unit cells B1, B2,.
It is divided into. The same applies to the multi-finger FET “C”.

The respective "unit cells" are periodically laid out in a "nested" manner. That is, A1, B
1, C1, A2, B2, C2, A3, B3, C3, A
4 and so on. In this specification, the array of unit FETs obtained in this manner is referred to as an “FET array”. In the actual layout, the FET rows need not be one row. That is, two or more rows can be appropriately formed according to the number of unit FETs.

In FIG. 1, the "unit cell" is 2
Although the case where there are a plurality of unit FETs has been illustrated, the present invention is not limited to this. Besides this,
The “unit cell” may be composed of one unit FET, or may be composed of three or more unit FETs. However, it is desirable that the number of unit FETs included in the “unit cell” be an even number. If the number of unit FETs included in the “unit cell” is an odd number, the adjacent “unit FE”
This is because either the source or drain wiring cannot be shared between "T" and "unit FET", and it is necessary to increase the number of wirings.

On the other hand, each multi-finger FET
Need not be divided so that all “unit cells” have the same number of unit FETs. For example, the "unit cell" A1 may be divided into two unit FETs, and the "unit cell" A2 may be divided into four unit FETs. However, the method of dividing into “unit cells” needs to be the same between multi-finger FETs. For example, the “unit cell” A1 includes two unit FEs.
T and the "unit cell" A2 is divided into four unit FETs, the "unit cells" B1 and C1
Has two unit FETs each, and a "unit cell" B
2 and C2 must be divided so as to have four unit FETs each.

Next, in the present invention, the wiring for each electrode of each unit FET is laid out evenly above and below this "FET row". That is, the wiring pattern is formed so that the electrode wiring length of each multi-finger FET becomes uniform.

According to the present invention, by dividing the multi-finger FET into unit cells and arranging them alternately and arbitrarily wiring them, the signal lines have the same line length for all the multi-finger FETs. This makes it possible to eliminate the deviation of the characteristics of each multi-finger FET.

Hereinafter, specific examples of the present invention will be described. FIG. 2 is a layout diagram of the FET section of the integrated circuit device according to the present invention. FIG. 3 is an enlarged view of a part of this layout. FIG. 4 is a diagram showing an equivalent circuit of this layout. FIG. 5 is a diagram showing a basic circuit of the FET section of the integrated circuit device. The one illustrated in these drawings is a one-input four-output port (SP4T)
This is the FET portion of the switch. First, the overall circuit configuration will be described with reference to FIG. The integrated circuit element illustrated in FIG. 1 is formed on a substrate such as silicon or gallium arsenide, and includes four multi-finger FETs 1.
01 to 104. Each of the FETs can be configured as, for example, a MOSFET formed on a silicon substrate, a MESFET formed on a gallium arsenide substrate, or the like. The figure shows the FET of the SP4T switch.
It is a circuit diagram that extracts only the part, the actual switch is
It has a gate resistance, an inductor, and the like in addition to the illustrated FET.

The drain electrodes of the multi-finger FETs 101 to 104 are connected to a drain terminal 110 through common wiring. In addition, each of the gate electrodes 121 to 124
Is connected to a gate resistor (not shown), and each source electrode 1
11 to 114 are connected to output terminals (not shown).

Here, a characteristic feature of the present invention is that the multi-finger FETs 101 to 104 are laid out integrally, and the unit cells constituting each multi-finger FET are arranged adjacent to each other in a “nested shape”. Is a point. In the configuration illustrated in FIGS. 2 and 3,
Each of the multi-finger FETs 101 to 104
It is composed of five unit cells. That is, the multi-finger FET 101 includes the unit cells 101a, 101
.., 101e. The multi-finger FET 102 includes unit cells 102a to 102e, the multi-finger FET 103 includes unit cells 103a to 103e, and the multi-finger FET 104 includes
4a to 104e.

Each unit cell has two unit FETs.
Having. That is, each multi-finger FET has ten unit FETs. In the layout shown in FIGS. 2 and 3, the finger length of the unit FET is 1
Since each of the multi-finger FETs is
Has a total gate width of 1 mm.

In the layouts shown in these figures, a total of 20 unit cells, ie, 40 unit FETs are arranged in the same column. The arrangement order of the unit cells is 101a, 102a, 103a, 104a, 10a
1b, 102b, 103b, 104b, 101c ...
It is like 104e. In other words, multi-finger F
The sequence of the unit cells of the ET 101, the unit cell of 102, the unit cell of 103, and the unit cell of 104 is repeated five times.

FETs laid out in a row as described above
Leading wires for each electrode are formed above and below the column, that is, the column of unit FETs. In the example shown in FIG. 2, the drain electrode wiring 110 is laid out so as to surround the periphery of the FET row, and is connected to the drain electrode of the FET row from above and below as appropriate. Also, source electrode wirings 111 to 11
4 and the gate electrode wirings 121 to 124 are also formed separately on the upper side and the lower side of the FET row, and are connected to the respective electrodes of the FET row at substantially equal intervals.

For example, the drain wiring will be described. As is clear from the equivalent circuit diagram of FIG.
01a, 102a, and 103a, respectively, are drain wirings 110a and 110b, respectively.
Drain wirings 110c and 110d laid out so as to extend below the T column and shared between unit cells 103a, 104a and 101b are laid out so as to extend above the FET column, respectively. . Further, the gate electrode wiring will be described. The gate electrode wiring 12 connected to the unit cells 101a and 102a, respectively.
1a and 122a are laid out so as to extend below the FET column, and the gate electrode wirings 123a and 124a of the unit cells 103a and 104a are laid out so as to extend above the FET column. Describing the source electrode wiring, the source electrode wirings 111a and 112a connected to the unit cells 101a and 102a are
The source electrode wirings 113a and 114a laid out so as to extend below the ET column and connected to the unit cells 103a and 104a are laid out so as to extend above the FET column.

According to the present invention, it is possible to eliminate the deviation of the line length for each multi-finger FET by the layout described above. That is, the layout of each multi-finger FET becomes redundant as compared with a conventional example in which four multi-finger FETs are separately arranged as shown in FIG.
0), the wiring path lengths of the four multi-finger FETs become equal. That is, four multi-fingers F
Conditions such as wiring resistance, wiring inductance, and coupling capacitance for each channel corresponding to ET can be made uniform, and deviations in characteristics for each channel can be suppressed.

Further, according to the present invention, by laying out the electrode wirings above and below the FET row as described above, restrictions on pad arrangement in chip layout are reduced, and design flexibility is improved. That is, F
Electrode pads can be arbitrarily provided not only on the upper side or the lower side of the ET column but also on both the upper side and the lower side, and the pads can be efficiently arranged to reduce the chip area. .

In the specific example shown in FIGS.
Although the case where the unit FETs are collectively arranged as one unit cell has been described, in addition to this, one unit FET may be arranged as one unit cell.
The unit FETs may be arranged as one unit cell, or three or more unit FETs may be arranged together as one unit cell. However, as described above, it is desirable that the unit cell is configured to have an even number of unit FETs. Explaining the reason in the example shown in FIGS. 2 to 4, the drain can be shared between adjacent “unit FETs”, and the element area can be reduced. Here, if a unit cell is formed by an odd number of unit FETs, a portion where the drain cannot be shared between the unit cells and the unit cell occurs, and the element area increases.

In FIGS. 2 and 3, the "FET
Although the case where the “row” is one row has been exemplified, the present invention is not limited to this. That is, when the integrated circuit element has a large number of multi-finger FETs, or when each multi-finger FET is composed of a large number of unit FETs, the “FET row” may be configured as two or more rows. good. Also in this case, by appropriately laying out the electrode wirings on the upper side and the lower side of each FET row, the wiring path length can be made uniform while suppressing an increase in chip size.

FIG. 6 is an explanatory diagram illustrating a layout of an integrated circuit device according to the present invention. The integrated circuit device shown in the figure has an S composed of six multi-finger FETs.
This is a P6T switch, and its circuit configuration is the same as that of FIG. F including six multi-finger FETs
The ET section 290 is arranged at the center of the chip. Also,
Power supply terminal 200, input terminal 210, output terminals 211-2
16 and the control terminals 231 to 236 are respectively arranged in the peripheral portion of the chip. Further, around the FET section 290, a pull-up resistor 240 and gate resistors 241 to 241 are provided.
246 and inductors 251 to 256 are arranged and connected appropriately.

In the FET unit 290, as described above with reference to FIGS.
Are divided into unit cells each having a predetermined number of unit FETs, and are periodically arranged in a nested manner. The electrode wirings are laid out above and below the FET row so that the electrode wirings are almost equal.

For the FET section 290, the input terminal 21
From 0, the wiring is connected, and the conditions of the wiring path from the input terminal 210 to the drain electrodes of the six multi-finger FETs are equal. In addition, six multi-finger F
Output terminals 211 to 216 respectively connected to ET
The wiring route up to is also equal. Compared with the conventional layout shown in FIG. 8, it is not necessary to distribute signal lines from input terminals to six individually provided multi-finger FETs, so that the chip size is about 1.3 mm × 1.
9 mm, which was reduced to about 76% of the conventional area.

In the conventional example, the deviation for each channel is equal to 0.
While the difference was 5 dB, the deviation of the integrated circuit device of the present invention could be extremely reduced to 0.1 dB.

In the above description, a specific example in which the present invention is applied to a one-input multiple-output port switch, that is, a case where the drain electrode of each multi-finger FET is common has been described. However, the present invention is not limited to this. Not something. In addition, for example, the present invention can also be applied to circuit elements in which the gate electrodes of the multi-finger FETs are connected in common, and the various effects described above can be obtained.

In addition, the present invention can be applied to, for example, a power amplifier circuit having a plurality of multi-finger FETs. In this case, by arranging the unit FETs of each multi-finger FET periodically in a “nested” manner as described above, the unit F
An effect of dispersing ET and suppressing an increase in element temperature can also be obtained. That is, in the case of a specific multi-finger FET, when individually laid out as in the related art, unit FETs serving as heat sources are densely arranged. Therefore, when a large electric power is applied to the multi-finger FET, the temperature tends to rise locally. On the contrary,
According to the present invention, since unit FETs belonging to the same multi-finger FET are scattered, heat sources are dispersed, and a local rise in temperature is suppressed.

Further, the present invention is not limited to high frequency integrated circuit devices. In addition, the present invention is applicable to all integrated circuit elements in which it is desirable to arrange a plurality of multi-finger FETs under uniform wiring path conditions.
The same effects can be applied, and the various effects described above can be obtained in the same manner. For example, the present invention is similarly effective when applied to all applications in which it is desired to suppress deviation for each channel such as wiring resistance, inductance, or coupling capacitance.

[0048]

The present invention is embodied by the above-described embodiment, and has the following effects. First, according to the present invention, the wiring path length for each multi-finger FET can be equalized. That is, conditions such as wiring resistance, wiring inductance, and coupling capacitance for each channel corresponding to each multi-finger FET can be made uniform, and a deviation in characteristics for each channel can be suppressed.

Further, according to the present invention, by forming the electrode wiring of the FET above and below the FET row,
Restrictions on pad arrangement during chip layout are reduced, and design flexibility is improved. That is, the electrode pads can be arbitrarily provided not only on the upper and lower sides of the FET row but also on both the upper and lower sides, and the chip area can be reduced by the efficient arrangement of the pads.

Further, according to the present invention, by arranging the unit FETs of the multi-finger FET in a nested manner, an effect of suppressing an increase in element temperature can be obtained. That is, in the case of a specific multi-finger FET, when individually laid out as in the related art, unit FETs serving as heat sources are densely arranged. Therefore, when a large electric power is applied to the multi-finger FET, the temperature tends to rise locally. On the contrary,
According to the present invention, since unit FETs belonging to the same multi-finger FET are scattered, heat sources are dispersed and a local rise in temperature can be suppressed.

As described above, the present invention is applicable to all integrated circuit elements, in which it is desirable to arrange a plurality of multi-finger FETs under uniform wiring path conditions, including high-frequency integrated circuit elements. The invention can be similarly applied, and the above-described various effects can be similarly obtained. For example, the present invention is equally effective when applied to all applications in which it is desired to suppress deviation for each channel such as wiring resistance, inductance, or coupling capacitance, and has a great industrial merit.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating the order of arrangement of FETs according to the present invention.

FIG. 2 is a layout diagram of an FET section of an integrated circuit device according to the present invention.

FIG. 3 is an enlarged view of a part of the layout of the integrated circuit device according to the present invention.

FIG. 4 is a diagram illustrating an equivalent circuit of the layout shown in FIG.

FIG. 5 is a diagram illustrating a basic circuit of the FET unit illustrated in FIG. 2;

FIG. 6 is an explanatory diagram illustrating a layout of an integrated circuit device according to the present invention.

FIG. 7 is a schematic pattern diagram showing a typical layout of a conventional multi-finger type FET.

FIG. 8A is a schematic circuit diagram of a one-input multiple-output port switch. (B) is a circuit diagram illustrating an actual circuit of the SP6T switch.

FIG. 9 is a pattern diagram illustrating an example of a layout of an SP6T switch.

[Explanation of symbols]

 101-104 Multi-finger FETs 101a, 102a,... Unit cell 110 Drain electrode wiring 111-114 Source electrode wiring 121-124 Gate electrode wiring 161-164 Drain electrode 200, 300 Power supply terminal 210, 310 Input terminal 211-216, 311 to 316 Output terminals 231 to 236, 331 to 336 Control terminals 240, 340 Pull-up resistors 241 to 246, 341 to 346 Gate resistors 251 to 256, 351 to 356 Inductors 290 FET units 371 to 375 Transmission lines 380 Input signal lines 411 Gate finger 412 Gate connection 421 Source finger 422 Source connection 431 Drain finger 432 Drain connection

Claims (7)

[Claims] 1. An integrated circuit device having a plurality of multi-finger FETs provided on a substrate, wherein at least one FET row composed of a plurality of unit FETs arranged substantially in parallel with each other is formed on the substrate. A plurality of the unit FETs selected in the FET row
Each of the plurality of multi-finger FETs are connected in common to form each of the plurality of multi-finger FETs, and the unit FETs adjacent in the FET row are configured as belonging to different multi-finger FETs. An integrated circuit element characterized by the above-mentioned. 2. An integrated circuit device in which a plurality of multi-finger FETs are provided on a substrate, wherein at least one FET row including a plurality of unit FETs arranged substantially in parallel with each other is formed on the substrate. A plurality of unit FETs adjacent to each other in the FET row
A source cell, a gate, and a drain are commonly connected to each other to form a unit cell; and a plurality of the unit cells selected in the FET row are commonly connected to a source, a gate, and a drain of the plurality of unit cells. An integrated circuit device comprising: each of the finger FETs, wherein the unit cells adjacent in the FET row belong to different ones of the multi-finger FETs. 3. The integrated circuit device according to claim 2, wherein said FET row is configured such that said unit cells belonging to each of said plurality of multi-finger FETs are periodically arranged. 4. The integrated circuit device according to claim 2, wherein each of said unit cells is constituted by an even number of unit FETs. 5. An integrated circuit device in which a plurality of multi-finger FETs are provided on a substrate, wherein a plurality of unit FETs are substantially parallel to each other such that adjacent unit FETs share either a source or a drain. The source, the gate, and the drain of a unit FET that is arranged on the substrate and periodically selected from the arranged unit FETs are commonly connected, and each of the plurality of multi-finger FETs is An integrated circuit device, comprising: 6. A common line commonly connecting at least one of a source, a gate, and a drain of the plurality of multi-finger FETs, and extends substantially in parallel on both sides of the FET row. The integrated circuit device according to any one of claims 1 to 5, further comprising a common wiring connected to each of the unit cells. 7. A plurality of wirings commonly connecting at least one of a source, a drain, and a gate of the unit cell belonging to the same multi-finger FET, wherein the wirings are substantially parallel on both sides of the FET row. Extends to
7. The integrated circuit device according to claim 1, further comprising a plurality of wirings connected to any one of said unit cells.