JPH11167442A - Device for activating system operating at 'sleep' mode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system for receiving the supply of power from a power source and operating at a 'sleep' mode. SOLUTION: A system clock 12, a vibration detection means 13 monitoring the operation of a system clock and a means 16 activating the system when the system is at the 'sleep' mode are provided. When the reactivating means of the system is in the system and the system is switched to the 'sleep' mode, an autonomous time base is immediately formed. When a prescribed time interval terminates, the system is activated again. When the system is not at the 'sleep' mode, it functions differently from the time base and reactivation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the field of electronic circuits and, more particularly, to means for reactivating a system operating in "sleep" mode.

[0002]

BACKGROUND OF THE INVENTION In the context of the present invention, an "electronic circuit" is a central processing unit which can be connected to at least one peripheral device, and which supplies a clock signal to all logic means of the system, in particular to the central processing unit. And a system clock. All components of the system are powered by the power supply.

[0003] Generally, such systems are referred to as "runs".
Mode or "active" mode, "standby"
It operates in one of two modes: a “halt” mode and a “sleep” mode.

When the system is in "run" mode, all components operate. "stand-by"
In the mode, only the peripheral device operates, and the central processing unit is usually in a stopped state. That is, the central processing unit is not operated by the clock signal. Also, when the system is in “sleep” mode, all components are shut down, including the system clock, and the power supply only continues to power the system. Thus, the system often operates in a "sleep" mode, which significantly reduces the power consumption of the system.

When designing a system of the type described above, the system is reactivated or "sleeped".
Switching from run mode to "run" mode or "standby" mode is problematic.

[0006] Prior solutions to this problem have provided a reset signal that reactivates the entire system by means external to the system. For example, the external means was formed by a key provided with means for supplying a reset signal to the system and was activated by user action.

[0007] The problem with such a solution is that additional means must be used to reactivate the system, which goes against the usual industry standards of cost and space requirements.

Another problem with the above solution is that it requires the use of means outside the system to reactivate the system, and thus does not allow autonomous reactivation of the system.

Another conventional solution to the above problem is
This is a method of creating a time base different from the time base provided by the system clock. The system clock is inactive in "sleep" mode. If the system switches to "sleep" mode, the new time base must be able to measure time intervals immediately.

By way of example, European Patent Specification EP
No. 586,256 discloses a system in the field of mobile phones comprising a first clock operating at a high frequency, a system clock, and a second clock operating at a low frequency. The system clock can enter a “sleep” mode, ie, be inactive for a predetermined time. The sleep time can be measured by counting low-frequency pulses generated by the second clock.

The problem with such a solution is that the low frequency clock must be calibrated against the system clock.

There are other solutions in the prior art to the problem of generating an alarm of a system of the type described above.

Referring to FIG. 1 herein, US Pat.
No. 98748 will be described. Disclosed is a system 1 including a central processing unit 2, a counter 3, a pulse generator 4, a first 25 MHz clock 5, and a second 50 KHz clock 6. These components have a counter 3 of 20 m when the central processing unit 2 is operating normally.
The counter 3 is reset to 0 every s, and when the central processing unit is not operating normally, the counter 3 is configured to continue counting up to 40 ms. At that time, the central processing unit 2
Power switches. As a result, the central processing unit 2
Power is supplied from the capacitor, the + 5V supply voltage source is disconnected, and the system 1 enters the << Sleep >> mode.

As disclosed in the aforementioned US Pat. No. 4,698,748, the << Sleep >> mode of the central processing unit 2 is continuously controlled by the central processing unit controlling the two multiplexers 7 and 8. Note that this corresponds to the operating state that is active at the moment.

[0015]

SUMMARY OF THE INVENTION Applicants have found that prior solutions such as those described above require dedicated means of operating the system in a "sleep" mode, and that such a solution is not available. The method has been found to require a large amount of power consumption. Typically, such an operation generally requires a current equal to several hundredths of a nanoamp (1 nA = 10 ⁻⁹ A) to several microamps (1 μA = 10 ⁻⁶ A).

For example, see the aforementioned US Pat. No. 4,698,748.
Although also disclosed in FIG. 1, when the system 1 is in the << Sleep >> mode in connection with FIG. 1 herein, the system consumes 10 mA.

It is an object of the present invention to provide a system which includes reactivation means and which solves the above problems when the system is in "sleep" mode.

Another object of the present invention is to provide a "sleep"
An object is to provide a system that consumes less power in a mode.

It is another object of the present invention to provide such a system that meets conventional industry standards in terms of cost and complexity.

[0020]

These and other objects are achieved by a system according to claim 1. That is,
The present invention provides a clock system configured to provide a clock signal at a first frequency, a central processing unit configured not to receive a clock signal in a "sleep" mode, and monitoring system clock activity. Vibration detection means and when the system is in "sleep" mode,
Means for re-activating it, wherein the means for re-activating is internal to the system, and as soon as the system switches to "sleep" mode, the autonomous time
Forming a base, reactivating the system at the end of a predetermined time interval, and performing a function different from time base formation and reactivation when the system is not in a “sleep” mode.

Such an arrangement allows the system to be reactivated autonomously and eliminates the need for dedicated means of operating the system in "sleep" mode, thereby reducing system space requirements and costs. There are advantages.

Another advantage of the reactivation means of the system according to the invention is that the reactivation means is internal to the system, so that the system can be reactivated without using external means, whereby The system is to be simplified.

Yet another advantage of the reactivation means of the system according to the invention is that it uses the vibration detection means in a "sleep" mode, forming an autonomous time base at the same time that the current flows from the power supply. This vibration detection means consumes little power when operating in "sleep" mode.

An advantage of the storage means of the system according to the invention is that it stores a plurality of predetermined number of pulses and outputs one of said predetermined number, indicating a predetermined time interval of the autonomous time base, and thus "sleep". The operation time of the system in the "mode" can be changed.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become apparent upon reading the detailed description of a preferred embodiment of the invention, given by way of example, with reference to the accompanying drawings, in which: FIG. FIG. 2 is a diagram illustrating a system 10 according to the present invention. The system 10 includes a central processing unit 11, a system
It includes a clock 12 and a vibration detecting means 13. System 10 may include at least one peripheral device 14.

It will be appreciated that system 10 also includes a power supply (not shown) configured to supply a supply voltage Vdd with respect to ground voltage Vss. Each component of system 10 includes a supply terminal (not shown) configured to receive supply voltage Vdd and a ground terminal (not shown) configured to receive ground voltage Vss.
Thus, the various voltages present in the system 10 are between the supply voltage Vdd and the ground voltage Vss. System 1
0 also operates in one of the "run", "standby", or "sleep" modes as described above.

The central processing unit 11 has a reference numeral 1
A first input terminal and a second input terminal denoted by 11 and 112,
And an output terminal 113. Peripheral device 14 includes first and second input terminals 141 and 142. It goes without saying that the peripheral device can further include at least one output terminal (not shown).

The system clock 12 is connected to the input terminal 12
1 and first, second, and third output terminals indicated by reference numerals 122, 123, and 124, respectively. The system clock 12 is configured to generate a clock signal CK at terminals 122, 123, and 124. Terminal 12
2 is connected to the central processing unit 11 via a terminal 111 so as to receive the clock signal CK. The terminal 123 is connected to the peripheral device 14 so as to receive the clock signal CK. By way of example only, the frequency of the clock signal CK supplied by the terminals 122 and 123 is usually about 600 KHz.

Each of the vibration detecting means 13 has a reference numeral 1
It includes a first input terminal, a second input terminal, a third input terminal, and an output terminal 134 indicated by 31, 132, and 133.
The vibration detecting means 13 is configured to monitor the operation of the system clock 12. For that purpose, terminal 13
1 is connected to the terminal 124 so as to receive the clock signal CK of the first frequency. That is, the vibration detecting means 13 receives the clock signal CK.

It should be noted that the first frequency may be lower than the frequency of the clock signal CK supplied to the central processing unit 11 and the peripheral device 14. By way of example, the first frequency is typically on the order of 500 Hz. System clock 12 includes a frequency division chain (not shown) configured to receive an input signal at a frequency of 600 KHz and generate an output signal between 600 KHz and several Hz. It goes without saying that the various frequencies are only given as examples for explanation.

The system 10 further includes a voltage conversion means 15 having an output terminal 151. The voltage conversion means 15
It is configured to receive the above-described supply voltage Vdd and generate a current Idd via the terminal 151 in response thereto. The voltage conversion means 15 preferably comprises a current mirror configured to supply a current Idd, so that this current has a predetermined value. By way of example only, the current Idd is approximately 1
equal to nA. Therefore, the terminal 151 is connected to the terminal 132 such that the vibration detecting means 13 receives the current Idd which is usually equal to 1 nA, for example.

The structure of the vibration detecting means 13 of the system shown in FIG. 2 will be briefly described. FIG. 3 is a simplified schematic diagram of the means. As described above in connection with FIG. 2, the vibration detecting means 13 includes terminals 131, 132, 133, and 134.
As shown in FIG. 3, the vibration detecting means 13 is
3, a reset means 24 and a threshold detecting means 25 are included. Preferably, a capacitor is used for the storage means 23, and a Schmitt trigger circuit is used for the threshold value detection means 25.

One of the two plates of terminal 132 and capacitor 23 is connected to node 26 so that the capacitor
dd. The other plate of the capacitor 23 is connected to the ground.

The reset means 24 includes first and second input terminals 241 and 242, respectively, and an output terminal 243. The reset unit 24 is configured to receive the reset control signal and set the voltage Vi at the terminal of the capacitor 23 to 0. This control signal
Usually, it corresponds to the rising edge of the clock signal CK. To that end, terminal 241 is connected to terminal 131 so that reset means 24 receives clock signal CK, and terminal 243 is connected to node 26 so that voltage Vi can be reset to zero.

The Schmitt trigger circuit 25 has an input terminal 251 and an output terminal 252. Schmidt
The trigger circuit 25 receives the voltage Vi, detects whether this voltage is higher than the threshold voltage Vth,
When i is higher than the voltage threshold voltage Vth, the voltage V0 corresponding to the pulse can be supplied. Therefore, the terminal 251 is connected to the node 26 so that the Schmitt trigger circuit 25 can receive the voltage Vi, and the terminal 252 is connected such that the voltage V0 is supplied as the output voltage of the vibration detecting means 13. 134
It is connected to the. It should be noted that in a preferred example where the threshold detecting means 25 is constituted by a Schmitt trigger circuit, the threshold voltage Vth corresponds to a switching point of this circuit.

Vibration detection means 1 when system 10 is in "standby" mode or "run" mode
Operation 3 will be briefly described. Regardless of the mode of operation of system 10, all components of the system remain at voltage Vdd. Thus, current Idd flows continuously through terminal 132 and capacitor 23 is charged such that voltage Vi is a linear function as a function of time t.

FIG. 4 is three timing charts showing the voltage Vi, the voltage V0, and the waveforms 31, 32 and 33 of the clock signal CK. As shown in the timing chart 32, the voltage Vi
Is initially 0 at t0 and thereafter increases linearly with time t. Further, when the system 10 is in the “run” mode or the “standby” mode, the state of the clock signal CK changes periodically as shown in the timing diagram 31. The frequency of the clock signal CK is usually
Equal to 500 Hz. Therefore, as shown at the timing 31, at the instant t0, the clock signal CK is low, for example, as the voltage Vss, and at the instant t1, the state changes, and is high, for example, as the voltage Vdd. Moment t1
After receiving the rising edge of the clock signal CK, the reset means 24 resets the voltage Vi, and Vi returns to the initial value as shown in a timing 32. The situation is the same as at the instant t0, and this situation is repeated.

It should be noted that the example shown in FIG. 4 illustrates the normal operation of system 10 in "run" or "standby" mode. Since the clock signal CK is periodically supplied to the vibration detecting means 13, the state of the voltage V0 does not change as shown in the timing 33.

By way of example only, consider the following abnormal situation. That is, for some reason,
The frequency of the clock signal CK decreases continuously. As a result, the capacitor 23 is reset at the end of the time that has increased with decreasing frequency. Therefore, the voltage Vi continuously increases linearly with time, and reaches the threshold voltage Vth. As a result, the Schmitt trigger circuit 25 switches. In this case, the state of the voltage V0 changes. That is, Schmitt trigger circuit 25 provides a reset command for system 10 as described below.

When the system is in the “sleep” mode, since the clock system 12 has been deactivated, the vibration detecting means 13 uses the clock system 1.
Note that we do not monitor the operation of the second. As shown in FIG. 2, the system 10 is configured such that the system 10 is in a "sleep"
Means 16 for reactivating the system 10 when operating in the mode.

The reactivation means 16 is provided by the system 1
0, forms an autonomous time base as soon as the system 10 switches to a "sleep" mode, reactivates the system at the end of a predetermined time interval, and places the system 10 in a "sleep" mode. If not, it performs a different function than the time base formation and reactivation functions.

In the preferred embodiment shown in FIG. 2, as described above in connection with FIG.
Includes a vibration detection means 13 used to monitor the operation of the clock system 12 in a "run" or "standby" mode, while forming an autonomous time base in a "sleep" mode.

The operation of the vibration detecting means 13 when the system 10 is in the "sleep" mode will be briefly described. FIG. 5 shows the clock signal CK, the voltage Vi, and the voltage V when the system 10 is in the “sleep” mode.
It is three timing diagrams which respectively show the waveform 41,42,43 of 0.

The instant t0 shown in FIG. 5 is the same as the instant t0 described in connection with FIG. As shown at the timing 41, at the instant t1, the state of the clock signal CK does not change, so that the voltage Vi is not reset. Therefore, as shown at timing 42, this voltage continues to increase linearly. At the instant t3 which comes 10 ms after t0, the voltage Vi changes to the threshold voltage Vt which is the switching point of the circuit 25.
h. As a result, as shown in timing 43,
Circuit 25 supplies an output pulse of voltage V0. This pulse can be used to provide a reset signal for system 10. Thus, the system 10 forms an autonomous time base as soon as it switches to the “sleep” mode, and can reactivate the system 10 after a time interval, typically 10 ms.

In order to further improve the performance, as shown in FIG.
7, storage means 18, comparison means 19, and control means 20
Can be included.

Each of the counting means 17 has a reference number 1
It includes first and second input terminals 71 and 172, and an output terminal 173. The counting means 17 is configured to receive the voltage V0, that is, to receive the pulse supplied by the vibration detecting means 13 at the instant t3. Further, the counting means 17 is configured so as to be able to count the supplied pulses and supply the counting result to the comparing means 19. Because of this, terminal 17
1 means that the counting means 17 detects the voltage V from the vibration detecting means 13
It is connected to the terminal 134 so that it can receive 0.

The storage means 18 includes an input terminal 181 and an output terminal 182. The storage unit 18 is configured to store a plurality of predetermined pulse numbers and supply one of the predetermined pulse numbers to the comparison unit 19. To this end, the terminal 181 is connected to the terminal 113 so that the value stored in the storage means 18 can be changed via the central processing unit 11. Preferably, the storage means 18 comprises an optional register with a plurality of bits. An optional register is a register whose contents are not reset when the system containing the register is reactivated. That is, within the scope of the preferred embodiment shown in FIG. 2, the value stored in such a register may be changed by rewriting via the central processing unit 11 of the system 10, or the initialization of the system 10, i.e. Changed only when the power supply is connected to.

As an example, three bits B0, B1, B2
Consider an optional register with Bit B
The value represented by 0, B1, B2 is equal to any of a predetermined number of pulses and is supplied in the unit of time, ie, the "sleep" mode by the vibration detection means 13.
The time interval between two consecutive pulses is equal to 10 ms. Table 1 below shows an example of the correspondence between the bits B2, B1, and B0 and the predetermined number of pulses N.

To improve performance, an optional 4-bit register may be provided, the fourth bit being the autonomous time that the vibration detector 13 satisfies when the system 10 is in "sleep" mode. Used to enable or disable a function. Again, for improved performance, an optional register with a large number of bits could be used to store a larger number of predetermined pulses.

The comparing means 19 has a reference numeral 19 respectively.
1 and 192, and an output terminal 193. The comparing means 19 receives the pulse count and one of the predetermined number of pulses and compares these numbers or, if the numbers are equal, supplies a reset command signal to the control means 20. Is configured. For this purpose, the terminal 191 is connected to the terminal 1 so that the comparing means 19 can receive the number of pulses counted since the last time the counting means 17 was reset.
73. The terminal 192 is connected to the terminal 182 so that the comparing unit 19 can receive one of the predetermined number of pulses stored in the storage unit 18.

The control means 20 includes an input terminal 201 and first and second input terminals 202 and 203, respectively.
Output terminal. The control means 20 includes the system 1
It is configured to control a set of zero reset signals and provide reset control signals to most of the components of the system 10. Therefore, the terminal 201 is connected to the terminal 193 so that the control unit 20 can receive the reset command signal supplied from the comparison unit 19. Terminal 202 is connected to terminals 112 and 142 so that control means 20 can control central processing unit 11 and peripheral device 14, respectively. Terminal 203 is connected to control means 2
0 is connected to the terminals 121, 133, 172 so that 0 can control the reset of the clock system 12, the vibration detecting means 13 and the counting means 17, respectively.

To illustrate the control of such a reset signal, consider the case where the system 10 is in a "run" mode or a "standby" mode and an abnormal situation as described above has occurred. in this case,
When the vibration detection means 13 supplies a pulse, the control means 20
Supplies a reset control signal for the system 10.

Consider the case where the system 10 is in the "sleep" mode and uses the vibration detection means 13 as a time base for a predetermined time interval corresponding to a number N greater than one. As shown in FIG. 5, at the instant t3, a pulse is supplied as the voltage V0. The counting means 17
Assuming that it has been initialized at the instant t0, the counting means 1
7 supplies a pulse count equal to 1 which is different from the predetermined number N. As a result, the comparing means 19 does not supply the reset command signal, and the voltage Vi becomes 0. This situation is the same as the situation at the moment t0, and this situation is repeated.

Thus, in conjunction with the logic means 17 to 20, the vibration detection means 13 supplies a pulse in a "sleep" mode, usually every 10 ms, thereby providing a time
A base is formed. The supplied clock signal is 10
It has a second frequency of about 0 Hz. This frequency is 5
Note that 00 Hz, which is significantly lower than the first frequency defined above. It goes without saying that the values of the various frequencies have been given only as examples for explanation. Those skilled in the art will note that the frequency of the vibration detecting means 13 is determined by the capacitance of the capacitor 23 and the strength of the current Idd, as described in connection with FIG.

Since the autonomous time-based embodiment as described above requires very little power,
Note that this system is particularly advantageous. In fact, the operation depends mainly on the outflow of the current Idd which charges the capacitor 23. It should be noted that such a system is particularly advantageous since the area required to perform this configuration is limited to the area of the logic means 17 to 20. In fact, vibration detection means 13 are generally present in such systems.

The operation of the system 10 when the system 10 switches from the "run" mode or the "standby" mode to the "sleep" mode, or vice versa, will be described below with reference to FIGS. . FIG.
Are three timing diagrams 51 showing waveforms of the clock signal CK, the voltage V0, and the reset signal RST, respectively.
52 and 53.

The system 10 is in a "run" mode or a "standby" mode for a time interval leading to the instant T0 and a time interval starting from the instant T1. At these time intervals, the clock system 12 is activated and the state of the clock signal CK changes periodically, as shown at timing 51. As shown at timings 52 and 53, the voltage V0 supplied by the vibration detecting means 13 at the same time interval is 0 as in the case of the reset signal RST. As already mentioned above, it goes without saying that such a situation corresponds to a normal situation.

After the instant T0, the system 10 goes into a “sleep” mode. Therefore, clock system 1
2 is deactivated, and there is no periodic state change of the clock signal CK, as shown at timing 51. As shown in a timing 52, at the same time interval, the vibration detecting means 13 supplies a pulse every 10 ms. Assuming that 4 is selected as the predetermined pulse number N, the reset signal RST is 0 unless the pulse count is equal to 4 as shown in the timing chart 53. At instant T2, the pulse count is equal to four. Therefore,
As indicated by the timing 53, the comparing means 19 supplies a pulse. The time from instant T1 to T2 corresponds to the reaction time of system 10 and the stabilization time of such a system, following the reset signal provided at instant T2. Therefore, the situation at the moment T1 is similar to the initial situation before the moment T0.

It will be apparent to those skilled in the art that various modifications can be made to the above detailed description without departing from the scope of the invention. In another embodiment,
The vibration detecting means can be replaced by a means inside the system. Such a measure can cause the system to "sleep"
As soon as it switches to the mode, it forms an autonomous time base, reactivates this system at the end of a predetermined time interval, and if the system is not in "sleep" mode, what is time base formation and reactivation Different functions can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system according to the related art.

FIG. 2 shows a system according to the invention.

FIG. 3 is a schematic diagram of the vibration detecting means of FIG. 2;

4 is three timing diagrams showing waveforms of three signals related to the vibration detecting means of FIG. 3 when the system of FIG. 2 is in a “run” mode or a “standby” mode.

FIG. 5 is three timing diagrams showing waveforms of three signals related to the vibration detecting means of FIG. 3 when the system of FIG. 2 is in a “sleep” mode.

FIG. 6 is a three timing diagram showing the waveforms of three signals in the system of FIG. 2 when the system is in a “run” mode, a “standby” mode, or a “sleep” mode, respectively. is there.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 System 11 Central processing unit 12 System clock 13 Vibration detection means 14 Peripheral equipment 15 Voltage conversion means 111 1st input terminal 112 2nd input terminal 113 Output terminal

Claims (7)

[Claims] A system (10) receiving power from a power supply and operable in a "sleep" mode, the clock system (12) being configured to provide a clock signal at a first frequency. A central processing unit (11) configured to receive no clock signal in a "sleep"mode; and a vibration detection means (1) for monitoring operation of a system clock.
3) and means (16) for reactivating the system when it is in "sleep" mode, wherein the reactivation means is internal to the system and autonomous as soon as the system switches to "sleep" mode. Form a dynamic time base, reactivate the system at the end of a predetermined time interval, and perform different functions than time base formation and reactivation if the system is not in "sleep" mode. System (10) to do. 2. A reactivation means (16) for forming an autonomous time base in a "sleep" mode and for monitoring the operation of a system clock in a "run" mode or a "standby" mode. 2. The system (1) according to claim 1, further comprising a vibration detecting means.
0). 3. A pulse (V0) having a second frequency lower than the first frequency in the "sleep" mode in the vibration detection means.
3. The apparatus of claim 2, wherein
(10). 4. The reactivation means (16) stores a plurality of predetermined pulse numbers and supplies one of the pulse numbers representing a predetermined time interval of the autonomous time-based operation to the comparison means. And a counting means (17) configured to receive a pulse from the storage means (18) and the vibration detecting means, count the received pulses, and supply the count to the comparing means. The system (10) according to claim 3, wherein: 5. A reactivating means (16) for receiving a pulse count and one of a predetermined number of pulses, comparing these numbers and, if equal, resetting the system. The system (10) according to claim 4, further comprising comparison means (19) configured to provide (RST). 6. The system (10) according to claim 5, wherein the storage means (18) includes an optional register containing a plurality of bits. 7. An optional register containing at least two bits for providing an autonomous time base function that the vibration detection means can perform when the system is in a “sleep” mode. 7. The system (10) of claim 6, wherein one of the two is enabled or disabled.