JPH1116361A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To assure high speed data reading operation by shortening the read cycle to realize low power consumption of a sense amplifier. SOLUTION: This device determines simultaneously addresses of a plurality of sections and gives, based on the quick clock CLK 2 generated by a clock generator 4, the data of output line of the sections 1 to 4 by the forward switches 10A, 10B, 10C, 10D which are sequentially controlled through the first burst counter 1 to the main sense amplifiers 3A, 3B, 3C, 3D which are given different driving capability depending on the respective output timing. Moreover, output signals of the main sense amplifiers 3A, 3B, 3C, 3D for determining the data at the different times sequentially guides depending on the respective capability by the forward switches 13A, 13B, 13C, 13D which are sequentially controlled by the second burst counter 2 for controlling the read cycle on the basis of the external clock CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a circuit configuration suitable for a burst mode in data reading in a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 5 is a timing chart for explaining data reading in a burst mode in a conventional semiconductor memory device, particularly showing a pipeline burst function. In the figure, (A) is an external clock CLK, (B) is an externally applied address AD,
(C) is a data output Dout, (D) is an address set signal / ADS, and (E) is an address inside the device. In the figure, an external clock CLK supplied from outside is provided.
5 shows the relationship between the signals from cycle 1 to cycle 6.

Now, the cycle Cyc of the external clock CLK is
In le1, when A0 is given as the address AD and the address set signal / ADS is given at the same time, the address A0 is set inside the device.

A data output D0 of the semiconductor memory corresponding to the address A0 is provided in a cycle Cycle3.
It is output as a data output Dout.

[0005] In a semiconductor memory device,
With the setting of the address A0, the cycle Cycle2,
In addresses 3 and 4, addresses A1, A2, A3
Is generated. As a result, these addresses A1, A
D, which is the data output of the semiconductor memory corresponding to A3
1, D2 and D3 are cycles Cycle4,
5 and 6 are sequentially output.

The above-mentioned data reading is called a pipeline burst function, and data for four addresses are continuously output as a data output Dout.

[0007]

In the conventional semiconductor memory device, the semiconductor memory is controlled in the pipeline burst mode as described above.
The cycle time of the LK had to be secured longer than the time from when the address was determined to when the data was stored in the output register. For this reason, there is a problem that it is difficult to increase the speed of the operation and it is difficult to reduce the power consumption of the sense amplifier used for reading data.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a plurality of addresses to a semiconductor memory at the same time, and to provide a sense amplifier having a difference in capability according to a data output order. An object of the present invention is to provide a semiconductor memory device capable of realizing high-speed reading and low power consumption by performing data reading through the semiconductor memory device.

[0009]

In order to achieve the above object, according to the present invention, there is provided a semiconductor memory device, comprising: means for simultaneously determining an address of a memory cell in each of a plurality of sections; In order to determine the data read to the output line of each memory cell, each of the sense amplifiers is arranged based on a plurality of sense amplifiers arranged corresponding to each section of the memory cell and a clock faster than a read cycle. First switch means for sequentially applying data read from each memory cell to each output line to the amplifier; and, from each of the sense amplifiers, an order based on a read cycle.
And a second switch for outputting data.

In order to achieve the above object, the present invention provides a semiconductor memory device according to claim 4, wherein means for simultaneously determining addresses of memory cells in each of a plurality of sections, and an output line from each of the memory cells. And a plurality of sense amplifiers of variable driving capability arranged corresponding to each section of the memory cell, and sequentially output from the sense amplifiers in accordance with a read cycle in order to determine the data read out. A semiconductor memory device comprising: a plurality of registers for storing the output data thus obtained; and control means for providing different drive capabilities to the sense amplifiers in accordance with the data read order of the plurality of sense amplifiers. To provide.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention. As shown in the figure, the memory cell array MCA has four sections Section1,
It has 2, 3, and 4. Each section has, for example, eight columns, and in each column, a plurality of memory cells are arranged in the column direction. Each memory cell outputs complementary data. This memory cell array MCA has a row decoder RD.
And a column decoder CD. These decoders RD and CD select one destination memory cell in each section based on the added address AD,
Data from the selected four memory cells are output to a bit line group BLG including four sets of complementary bit lines BL and / BL. In the above operation, regarding the decode output from the column decoder CD, the outputs from the four memory cells in the memory cell array MCA are simultaneously determined by the decode output, and the bit line group BLG having four sets of bit lines is determined. It is output at the same time and applied to the column switch 6.

External clock CLK input from outside
Is supplied to the clock generator 4, where a clock CLK2 having a period of 1/2 of that of the external clock CLK is formed. This clock CLK2 is provided to the first burst counter 1.

An externally applied address AD has a first
Is input to the burst counter 1. The first burst counter 1 is supplied with an address set signal / ADS for setting the address AD.

The first burst counter 1 outputs a burst count signal in binary from the set address AD based on the clock CLK2 from the clock generator 4.

A read signal read from the memory cell array MCA to the non-inverting side bit line BL and the inverting side bit line / BL is supplied to the main sense via the column switch 6 and the forward switches 10A, 10B, 10C, and 10D. It is sensed by the amplifiers 3A, 3B, 3C and 3D.

The output of the main sense amplifier 3A is latched by a non-inverting latch 11A and an inverting latch 12A, and is output via a forward switch 13A to an output latch 14A.
0, transferred to the output latch 141, and the data output Dout
Is output as

The output of the main sense amplifier 3B is latched by a non-inverting latch 11B and an inverting latch 12B, and is output via a forward switch 13B to an output latch 14B.
0, transferred to the output latch 141, and the data output Dout
Is output as

The output of the main sense amplifier 3C is latched by a non-inverting latch 11C and an inverting latch 12C.
0, transferred to the output latch 141, and the data output Dout
Is output as

The output of the main sense amplifier 3D is latched by the non-inverting latch 11D and the inverting latch 12D, and is output via the forward switch 13D to the output latch 14D.
0, transferred to the output latch 141, and the data output Dout
Is output as

Note that a burst signal from the first burst counter 1 is applied to the column switch 6, whereby four sets of outputs from the memory cell array MCA are sequentially output.

The binary count output from the first burst counter 1 is output to NOR circuits 7A, 7B, 7C, 7
D and knot circuits 91, 92, 93, and 94, and are provided to forward switches 10A, 10B, 10C, 1 based on predetermined decoding logic.
It is sequentially converted into a selection signal for 0D.

The binary count output from the second burst counter 2 is output from the NOR circuits 8A, 8B, 8C, 8
D and knot circuits 95, 96, 97 and 98, and are provided to forward switches 13A, 13B, 13C, 1C based on predetermined decode logic.
It is sequentially converted into a selection signal for 3D.

Next, the operation of the above-described configuration will be described with reference to the timing chart of FIG. 2A shows an external clock CLK, FIG. 2B shows a clock CLK2 formed by a clock generator 4, FIG.
FIG. 3C shows an externally applied address AD, FIG. 4D shows internal addresses A0, A1, A2, and A3 specified inside the memory cell array MCA, and FIG. 4E shows a main sense amplifier 3A. FIG. 11F is an operation of the main sense amplifier 3B, FIG. 10G is an operation of the main sense amplifier 3C, and FIG.
FIG. 3I shows the operation of the main sense amplifier 3D, FIG. 3I shows the data output Dout, and FIG. 3J shows the address set signal / ADS.

Now, in the cycle Cycle 1, FIG.
As shown in (C), when A0 is given to the first burst counter 1 as the address AD, and when the address set signal / ADS is given as shown in (J) in the same figure, the first burst counter 1 1, the address A0 is set, and based on this, a burst signal to the column switch 6 is given in the first half of the cycle Cycle2.
That is, the output of the non-inverted bit line BL from each section corresponding to the four addresses shown in FIG.
The output of the inverted bit line / BL is output in synchronization with the selection order of the forward switches 10A to 10D described later.

On the other hand, from the first burst counter 1,
A binary signal synchronized with the clock CLK2 is output,
NOR circuits 7A, 7B, 7C, 7D and knot circuit 9
1, 92, 93, and 94, and these signals are decoded by the forward switches 10A, 10A,
B, 10C and 10D. As a result, FIG.
2E, the forward switch 10A is selected in the first half of the cycle Cycle2, and as shown in FIG. 2F, the forward switch 10A is selected in the second half of the cycle Cycle2.
B is selected, and as shown in FIG.
The forward switch 10C is selected in the first half of the cycle 3, and as shown in FIG. 2H, the forward switch 10D is selected in the second half of the cycle Cycle3. In other words, the forward switches 10A, 10A are sequentially synchronized with the clock CLK2.
B, 10C, and 10D will be selected.

As a result, the main sense amplifiers 3A, 3B, 3C and 3D are respectively shown in FIG.
At the timings shown in (F), (G), and (H), each output is taken from sections 1 to 4 and sensed.

The main sense amplifiers 3A, 3A
The memory outputs sensed by B, 3C, and 3D respectively have non-inverted latches 11A, 11B, 11C, and 1C.
1D, and the inversion side is the inversion side latch 12
A, 12B, 12C, and 12D are latched, and the high level or the low level of these latch signals is determined after a lapse of time according to the capability of the main sense amplifiers 3A, 3B, 3C, and 3D.

On the other hand, from the second burst counter 2,
A binary signal synchronized with the external clock CLK is output and decoded through a logic circuit including NOR circuits 8A, 8B, 8C, 8D and NOT circuits 95, 96, 97, 98, and these signals are forward-switched 13A, 13A.
B, 13C and 13D. As a result, the forward switch 13A is selected in cycle Cycle3, the forward switch 13B is selected in cycle Cycle4,
The forward switch 10C is selected in cycle Cycle5, and the forward switch 13D is selected in cycle Cycle6. That is, the forward switches 13A, 13B, 13C, and 13D are sequentially selected in synchronization with the external clock CLK.

As a result, the output signal D0 from the section 1 determined in the non-inverting side latch 11A and the inverting side latch 12A is supplied to the cycle Cycle 3 through the forward switch 13A as shown in FIG. The data is latched by the output latches 140 and 141, and the data output Dou
Output as t. The output signal D1 from the section 2 determined by the non-inverting side latch 11B and the inverting side latch 12B is transmitted through the forward switch 13B in cycle 4 as shown in FIG.
Latched by the output latches 140 and 141, and the data output D
Output as out. Further, the non-inverting side latch 11
C, the output signal D2 from the section 3 determined by the inverting-side latch 12C is latched by the output latches 140 and 141 through the forward switch 13C in cycle Cycle 5, as shown in FIG. It is output as an output Dout. The output signal D3 from the section 4 determined in the non-inverting side latch 11D and the inverting side latch 12D is supplied to the forward switch 13 in cycle Cycle6 as shown in FIG.
D, the output is latched by the output latches 140 and 141,
It is output as a data output Dout.

Now, each main sense amplifier 3
A, 3B, 3C, 3D forward switches 10A, 10
B, 10C, and 10D, the signal output from the sections 1 to 4 is given, and then the forward switch 13 is actually turned on.
The time allowed until output through A, 13B, 13C and 13D is shown in FIGS. 2 (E), (F), (G),
As shown in (H), they are different from T1, T2, T3, and T4, respectively. That is, the main sense amplifier 3A
Need to be determined by the end of cycle Cycle3, whereas the output of main sense amplifier 3B only needs to be determined by the end of cycle Cycle4, and the output of main sense amplifier 3C The output only needs to be determined by the end of cycle Cycle5.
The output of D may be determined by the end of cycle Cycle6.

That is, the main sense amplifier 3
While the driving capability of A needs to be the highest, the driving capability of each of the main sense amplifiers 3B, 3C, and 3D may be sequentially reduced. And
In the first embodiment, the minimum necessary drive capability is individually provided to the main sense amplifiers 3A, 3B, 3C and 3D in accordance with this situation.

As a result, a drive capability equal to that of the main sense amplifiers 3A, 3B, 3C, and 3D is provided, and signals from the sections 1 to 4 are sequentially read out in synchronization with the external clock CLK. And the internal addresses A0, A1, A2, A3 of the sections 1 to 4
At the same time, the external clock C
LK can be speeded up, and at the same time, there is a margin in the time until data determination, so that the total power consumption of the sense amplifier can be reduced.

In this embodiment, as an example, the clock generator 4 for generating the clock CLK2 from the external clock CLK is used, and the data reading system using the forward switch is exemplified. The address is determined simultaneously, a signal is given to the sense amplifier group at an early timing, and the external clock CLK
Any configuration can be applied as long as the configuration is such that the data is sequentially output to the data output Dout in synchronization with. Embodiment 2 FIG. 3 is a block diagram of a semiconductor memory device according to the second embodiment of the present invention. 3, the same reference numerals are given to the same circuit elements as those in FIG. An external clock CLK input from the outside is applied to the first burst counter 1. Non-inverting side BL from memory cell array MCA
And the read signal of each bit line of the inverting side / BL is directly used as the variable capacity sense amplifier 30A,
30B, 30C and 30D.

The variable-capacity sense amplifier 30A,
The outputs of 30B, 30C, 30D are transferred to output latch 140, output latch 141 via output data registers 150, 151, 152, 153, and output data Do.
ut is output.

It should be noted that the variable capacity sense amplifiers 30A, 30B, 30C, 30
D, a sense amplifier capability control signal SC is output, and the corresponding memory cells 50, 51, 5
The data output Dou is actually performed after the addresses of 2, 53 are determined.
It is configured to provide different sensing capabilities depending on the time margin until data is output at t.

An output data register control signal RC is applied from the burst counter 16 to the output data registers 150, 151, 152, 153, and the variable capacity sense amplifiers 30A, 30B, 30C,
Each sense output of 30D is controlled so as to be sequentially output to a data output Dout in synchronization with an external clock CLK.

Next, the operation of the above-described configuration will be described with reference to the timing chart of FIG. 2A shows an external clock CLK, FIG. 2B shows an externally applied address AD, and FIG. 2C shows an internal address A0 specified inside the memory cell array MCA.
A1, A2, A3, FIG. (D) shows the operation of the variable capacity sense amplifier 30A, FIG. (E) shows the operation of the variable capacity sense amplifier 30B, and FIG. (F) shows the operation of the variable capacity sense amplifier 30C. (G) shows the operation of the variable capacity sense amplifier 30D, (H) shows the data output Dout, and (I) shows the address set signal / ADS.

Now, in cycle Cycle1, FIG.
As shown in (A), A0 is given to the burst counter 16 as the address AD, and when the address set signal / ADS is given as shown in FIG. Set.
At the same time, as shown in FIG. 4C, the output of the non-inverted bit line BL and the output of the inverted bit line / BL from the four sections are simultaneously determined and output.

These data are stored in the corresponding variable capacity sense amplifiers 30A, 30B, 30C,
30D, respectively, as shown in FIGS. 4 (D), (E),
At the timings shown in (F) and (G), that is, from the time of cycle Cycle 2, each output of sections 1 to 4 is captured and sensed.

The variable capacity sense amplifier 30A,
The memory outputs sensed at 30B, 30C, 30D are:
The high level or the low level is determined after a lapse of time according to the sense ability controlled by the sense amplifier ability control signal SC from the burst counter 16, respectively.

The variable capacity sense amplifier 3
The memory outputs sensed by 0A, 30B, 30C, 30D are output data registers 150, 151, 152, 1
The output timing is output to the output latches 140 and 141 through 53. The output timing is controlled by an output data register control signal RC supplied from the burst counter 16 to the output data registers 150, 151, 152 and 153.

As a result, as shown in FIG. 4I, the output signal D0 from the section 1 has a cycle Cyc.
The signal is latched in the output latches 140 and 141 through the output data register 151 at le3, and is output as the data output Dout. The output signal D1 from the section 2 has a cycle Cyc as shown in FIG.
The signal is latched by the output latches 140 and 141 via the output data register 152 at le4, and output as the data output Dout. Further, as shown in FIG. 4 (I), the output signal D2 from the section 3 is the cycle Cyc.
The signal is latched by the output latches 140 and 141 through the output data register 152 at le5, and is output as the data output Dout. Then, the output signal D3 from the section 4 is equal to the cycle Cy as shown in FIG.
Cle6 is latched by the output latches 140 and 141 via the output data register 153, and the data output Dout
Is output as

Each of the variable capacity sense amplifiers 30A, 30B, 30C and 30D has sections 1-4.
4D, 4E, and 4E, the permissible time from when the signal output is given to when the signal is actually output through the output data registers 150, 151, 152, and 153 is as shown in FIG.
As shown in (F) and (G), T1, T2, T3, T4
And each is different. That is, the output of the variable-capacity sense amplifier 30A needs to be determined before the end of cycle Cycle3, whereas the output of the variable-capacity sense amplifier 30B is determined by the cycle Cyc.
It is sufficient that the output is determined by the end of le4, and the output of the variable capacity sense amplifier 30C is the cycle Cyc
It is sufficient that the output is determined by the end of le5, and the output of the variable capacity sense amplifier 30D is the cycle Cyc
What is necessary is just to settle by the end of le6.

That is, while the driving capability of the variable-capacity sense amplifier 30A needs to be the highest, the variable-capacity sense amplifiers 30B, 30C, 30D
Can be sequentially reduced. In this embodiment 2, according to this situation,
The required minimum drive capability of each capability variable sense amplifier 30A, 30B, 30C, 30D is individually controlled by the sense amplifier capability control signal SC from the burst counter 16.

As a result, a drive capability equal to that of main sense amplifiers 3A, 3B, 3C, and 3D is provided, and memory cells 50, 51, and 5 are synchronized with external clock CLK.
The internal addresses A0 and A of the sections 1 to 4 are compared with the conventional method in which the signals 2 and 53 are sequentially read.
Since 1, A2 and A3 are determined at the same time,
The speed of the external clock CLK can be increased, and at the same time, there is a margin for the time until the data is determined, so that the total power consumption of the sense amplifier can be reduced.

Incidentally, the control of the driving capability of the variable-capacity sense amplifiers 30A, 30B, 30C, 30D is performed by switching the number of internal amplification stages, the combination of amplifiers, and the transistor size. Of course, various other methods are conceivable for this capability changing method. The number of switching stages may be set to any number of stages corresponding to the number of addresses to be read at the same time.

[0047]

As described above, according to the present invention, the addresses of the memory cells in the different sections are simultaneously determined, and only the read operation is performed in the burst mode.
Since the time required to determine the data of the sense amplifier for reading data from the memory cell differs for each address, it is not necessary to control the address for each read cycle and drive each sense amplifier. In addition, the cycle time can be shortened, the speed of the device can be increased, and the sense amplifier, which has enough time until the data is determined, can reduce the driving capacity as appropriate, which can reduce power consumption. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

FIG. 5 is a timing chart for explaining data reading in a burst mode in a conventional semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st burst counter 2 2nd burst counter 3A, 3B, 3C, 3D Main sense amplifier 4 Clock generator 6 Column switch 7A, 7B, 7C, 7D, 8A, 8B, 8C, 8D NOR circuit 10A, 10B , 10C, 10D, 13A, 13B, 1
3C, 13D Forward switch 11A, 11B, 11C, 11D Non-inverted latch 12A, 12B, 12C, 12D Inverted latch 16 Burst counter 30A, 30B, 30C, 30D Variable-capacity sense amplifiers 91, 92, 93, 94, 95, 96, 97, 98 knot circuit 140, 141 output latch 150, 151, 152, 153 output data register

Claims (5)

[Claims] A means for simultaneously determining the address of a memory cell in each of a plurality of sections; and a method for determining data read to an output line of each of the memory cells in correspondence with each section of the memory cell. A plurality of sense amplifiers arranged, first switch means for sequentially applying data read from each memory cell to each output line to each sense amplifier based on a clock earlier than a read cycle; And a second switch for outputting data from each of the sense amplifiers in an order based on a read cycle. 2. The driving capability of each of the sense amplifiers is set differently, and the driving capability is set higher as the speed is earlier and lower as the speed is slower in a data output read cycle. Item 1. The semiconductor memory device according to Item 1. 3. The semiconductor memory device according to claim 1, wherein said first switch means is controlled by a clock having a half cycle of a clock giving a read cycle. 4. A means for simultaneously determining addresses of memory cells in each of a plurality of sections, and a means for determining data read out from each of the memory cells to an output line corresponding to each section of the memory cells. A plurality of sense amplifiers having variable driving capabilities, a plurality of registers for storing output data sequentially output from each of the sense amplifiers in accordance with a read cycle, and a plurality of data of the plurality of sense amplifiers. Control means for giving different drive capabilities to each of the sense amplifiers in accordance with the reading order. 5. The data control circuit according to claim 4, wherein said control means controls the driving capability of each sense amplifier in a data output read cycle, the higher the earlier, and the lower the lower the speed.
Semiconductor storage device.