JPH11163531A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPH11163531A
JPH11163531A JP9338243A JP33824397A JPH11163531A JP H11163531 A JPH11163531 A JP H11163531A JP 9338243 A JP9338243 A JP 9338243A JP 33824397 A JP33824397 A JP 33824397A JP H11163531 A JPH11163531 A JP H11163531A
Authority
JP
Japan
Prior art keywords
wiring
main
wirings
wiring board
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9338243A
Other languages
Japanese (ja)
Inventor
Katsuhiko Okazaki
勝彦 岡崎
Nobuaki Sugiura
伸明 杉浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9338243A priority Critical patent/JPH11163531A/en
Publication of JPH11163531A publication Critical patent/JPH11163531A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To minimize the effect of multiple reflection in a branch wiring for high speed signal transmission by forming the main wiring of a wiring pattern for bus connecting an electric signal from a transmission element to one or more receiving element of parallel wirings having same number of bending times. SOLUTION: A multilayer wiring board is provided with a main wiring 11 and a transmission element 20 is connected with a plurality of receiving elements 30 through a plurality of wirings having equal length and meandering in parallel. Connection between the receiving element 30 and the main wiring 11 comprises the connection lead 31 of the receiving element 30, the pad 12 of the multilayer wiring board, and a connection via 13. Since a branch wiring is not required, the number of layers of the branch wiring can be decreased. When the number of bending times of the main wiring is minimized, the length of a plurality of main wirings 11 is equalized and since the number of bending times thereof is also equalized, delay time of signal propagation due to a bend is not required to be taken into account resulting in wiring where propagation delay of signal is equalized. According to the arrangement, multiplex reflection of signal waveform is reduced between the main wiring 11 and the elements 20, 30.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多数の集積回路を
搭載してバス接続の技術により電気信号をそれらの集積
回路に分配する多層配線板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board on which a large number of integrated circuits are mounted and an electric signal is distributed to the integrated circuits by a bus connection technique.

【0002】[0002]

【従来の技術】近時では、多層配線板に多数の集積回路
を搭載し、それらを相互に接続して1つの電子装置を構
成することが行われている。その接続方法のひとつとし
て、バス接続がある。一般に、集積回路において高速な
信号伝送を行う場合は、バス接続を利用して並列展開し
た信号を、複数のバス配線を用いて伝送し、配線1本当
りの物理速度を下げる手段が採用されている。
2. Description of the Related Art In recent years, a large number of integrated circuits are mounted on a multilayer wiring board and connected to each other to form one electronic device. One of the connection methods is a bus connection. In general, when high-speed signal transmission is performed in an integrated circuit, a signal that is developed in parallel using a bus connection is transmitted using a plurality of bus lines to reduce a physical speed per line. I have.

【0003】このバス接続の従来例を図4〜図6を参照
して説明する。図4は従来のバス配線を有する多層配線
板の配線構成を示す図であり、20は送信用素子、30
は受信用素子、41は多層配線板40の主幹配線であ
る。図5はその主幹配線41から受信用素子30に至る
接続構造を表した図であり、31は受信用素子30の接
続リード、42は多層配線板40のパッド、43,44
は多層配線板40の接続ビア、45は多層配線板40の
分岐配線である。図6は図5の構造の断面を示す図であ
る。
A conventional example of this bus connection will be described with reference to FIGS. FIG. 4 is a diagram showing a wiring configuration of a conventional multilayer wiring board having bus wirings.
Denotes a receiving element, and 41 denotes a main wiring of the multilayer wiring board 40. FIG. 5 is a diagram showing a connection structure from the main wiring 41 to the receiving element 30. Reference numeral 31 denotes a connection lead of the receiving element 30, reference numeral 42 denotes a pad of the multilayer wiring board 40, and reference numerals 43 and 44.
Is a connection via of the multilayer wiring board 40, and 45 is a branch wiring of the multilayer wiring board 40. FIG. 6 shows a cross section of the structure of FIG.

【0004】以上のように、従来のバス配線では、複数
の平行に並んだ主幹配線41から各素子20,30に分
岐配線45を用いて電気的に接続している。このとき、
分岐配線45が主幹配線41と交差しないよう、異なる
配線層を設けて、その分岐配線45を布線している。
As described above, in the conventional bus wiring, a plurality of parallel main wirings 41 are electrically connected to the respective elements 20 and 30 using the branch wirings 45. At this time,
Different wiring layers are provided so that the branch wiring 45 does not cross the main wiring 41, and the branch wiring 45 is laid.

【0005】図7は上記した従来の配線技術を用いた等
長配線の例を示す図である。46は蛇行配線部である。
主幹配線41と分岐配線45を含めた等長化を行おうと
すると、図7に示すように、最も長い配線に合わせて蛇
行配線部46を設ける必要がある。さらに、この蛇行配
線による曲げ回数がそれぞれの主幹配線41で異なるの
で、曲げた部分で生じる伝播遅延を考慮した設計が必要
となる。すなわち、曲げ部では反射と誘導によって、直
線配線部に比べて遅延時間が短いことが知られているた
め、この曲げ部での遅延時間を考慮して配線長を適宜調
整する必要がある。しかし、分岐配線45による反射の
影響は取り除けない。
FIG. 7 is a diagram showing an example of equal-length wiring using the above-described conventional wiring technique. Reference numeral 46 denotes a meandering wiring section.
In order to make the length equal to that of the main wiring 41 and the branch wiring 45, it is necessary to provide the meandering wiring section 46 in accordance with the longest wiring as shown in FIG. Further, since the number of times of bending due to the meandering wiring differs for each main wiring 41, it is necessary to design in consideration of a propagation delay generated at a bent portion. That is, it is known that the delay time in the bent portion is shorter than that in the straight wiring portion due to reflection and guidance. Therefore, it is necessary to appropriately adjust the wiring length in consideration of the delay time in the bent portion. However, the influence of reflection by the branch wiring 45 cannot be removed.

【0006】[0006]

【発明が解決しようとする課題】一般に、バス配線を有
する装置においては、その処理能力を上げようとするに
は、バス幅を増やしかつ信号伝送速度を上げることが必
要である。しかし、従来の構造では、バス幅を増やせ
ば、構造的な要因から分岐配線45が長くなり、その分
岐配線45の長さが信号波形の立ち上がり立ち下がり時
間に進む距離に比べて無視できない高速信号伝送におい
ては、多重反射の影響が顕著となる。逆に、バス幅を抑
えて信号伝送速度を上げても、最も長い分岐配線45に
制限され、信号速度を最大限に向上させることはできな
かった。また、従来の構造では、分岐配線45のための
配線層を余分に設ける必要があった。さらに、分岐配線
長差による信号の伝播遅延時間差を吸収するには、蛇行
配線部46を、曲げ部分の遅延時間を考慮に入れて挿入
しなければならなかった。
Generally, in a device having a bus wiring, it is necessary to increase the bus width and the signal transmission speed in order to increase the processing capability. However, in the conventional structure, if the bus width is increased, the branch wiring 45 becomes longer due to a structural factor. In transmission, the effects of multiple reflections are significant. Conversely, even if the signal transmission speed is increased by suppressing the bus width, the length is limited to the longest branch wiring 45, and the signal speed cannot be maximized. Further, in the conventional structure, it is necessary to provide an extra wiring layer for the branch wiring 45. Furthermore, in order to absorb the signal propagation delay time difference due to the branch wiring length difference, the meandering wiring portion 46 has to be inserted in consideration of the delay time of the bent portion.

【0007】本発明は以上のような点に鑑みてなされた
ものであり、その目的は、高速信号伝送における分岐配
線による多重反射の影響とバスライン毎のタイミングの
バラツキの影響を無くした多層配線板を提供することで
ある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to provide a multi-layer wiring which eliminates the effects of multiple reflections caused by branch wirings in high-speed signal transmission and the effects of timing variations among bus lines. Is to provide a board.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
の第1の発明は、1又は2以上の受信用素子と該受信用
素子に電気信号を発信する送信用素子とを電気的に接続
する複数の配線パターンを具備する多層配線板におい
て、前記配線パターンが、複数の主幹配線と、該主幹配
線と前記受信用素子や送信用素子を接続する接続部とを
含み、前記主幹配線を、平行且つ曲げ回数の等しい等長
化された配線で形成した。第2の発明は、第1の発明に
おいて、前記曲げ配線部が、直角の曲げ部、45度の曲
げ部、又は90度円弧の曲げ部であるように構成した。
第3の発明は、第1の発明において、前記接続部が、前
記受信用素子又は前記送信用素子の接続リードが接続さ
れるパッドと、該パッドと前記主幹配線を接続する接続
ビアを含むよう構成した。
According to a first aspect of the present invention to achieve the above object, one or more receiving elements are electrically connected to a transmitting element for transmitting an electric signal to the receiving elements. In a multilayer wiring board having a plurality of wiring patterns, the wiring pattern includes a plurality of main wirings, and a connecting portion that connects the main wiring and the receiving element or the transmitting element, and the main wiring is The wirings were formed of equal-length wirings which were parallel and had the same number of bendings. In a second aspect based on the first aspect, the bent wiring portion is a right-angled bent portion, a 45-degree bent portion, or a 90-degree arc-shaped bent portion.
In a third aspect based on the first aspect, the connection portion includes a pad to which a connection lead of the reception element or the transmission element is connected, and a connection via connecting the pad and the main wiring. Configured.

【0009】[0009]

【発明の実施の形態】図1〜図3は本発明の第1の実施
の形態の説明図である。図4〜図6で説明したものと同
じものには同じ符号を付した。10は多層配線板であ
り、そこには主幹配線11が設けられている。ここで
は、送信用素子20と複数の受信用素子30との間を、
平行に蛇行した複数の主幹配線11によって接続し、各
素子間の配線は等長化されている。
1 to 3 are explanatory views of a first embodiment of the present invention. The same components as those described in FIGS. 4 to 6 are denoted by the same reference numerals. Reference numeral 10 denotes a multilayer wiring board, on which a main wiring 11 is provided. Here, between the transmitting element 20 and the plurality of receiving elements 30
The wires are connected by a plurality of main wires 11 meandering in parallel, and wires between the elements are made equal in length.

【0010】受信用素子30から主幹配線11に至る接
続構造は、図2、図3に示すように、受信用素子30の
接続リード31、多層配線板10のパッド12、多層配
線板10の接続ビア13によって構成されている。この
ように本実施の形態では、分岐配線が不要となってお
り、その分岐配線分の層数を削減できる。
As shown in FIG. 2 and FIG. 3, the connection structure from the receiving element 30 to the main wiring 11 includes connection leads 31 of the receiving element 30, pads 12 of the multilayer wiring board 10, and connections of the multilayer wiring board 10. It is constituted by a via 13. As described above, in the present embodiment, the branch wiring is unnecessary, and the number of layers for the branch wiring can be reduced.

【0011】図8に主幹配線11の第1の具体例を示
す。ピッチpで並んだ4個のパッド12に対して、45
度の角度をなすよう斜めに配線された4本の配線部11
A(主幹配線11の方向の長さは4p)と、長さsで4
本の配線が平行な直線配線部11Bとを組み合わせて、
隣の4個のパッド12との間を接続する。
FIG. 8 shows a first specific example of the main wiring 11. For the four pads 12 arranged at the pitch p, 45
Four wiring parts 11 wired obliquely to form an angle of degree
A (the length in the direction of the main wiring 11 is 4p) and the length s is 4
Combining with the straight wiring part 11B where the wiring is parallel,
Connection is made between four adjacent pads 12.

【0012】このとき、曲げ回数は4回がその曲げ回数
を最も少なくする配線である。このように配線すると、
4本の主幹配線11は等長化され、さらに各主幹配線1
1の曲げ回数が等しくなるため、曲げ部による信号伝播
遅延時間を考慮する必要がなく、信号の伝播遅延が完全
に等しい配線が実現できる。
At this time, the number of times of bending is four, which is the wiring that minimizes the number of times of bending. When wired in this way,
The four main wirings 11 are made equal in length, and furthermore, each main wiring 1
Since the number of bends is equal, it is not necessary to consider the signal propagation delay time due to the bent portion, and a wiring with completely equal signal propagation delay can be realized.

【0013】図9は第2の具体例の主幹配線11’を示
す図である。ここでは、ピッチpで並んだ4個のパッド
12に対して、同心円形状で90度の円弧の4本の配線
部11A’(主幹配線11の方向の長さは4p)と、長
さsで4本の配線が平行な直線配線部11B’とを組み
合わせて、隣の4個のパッド12との間を接続する。
FIG. 9 is a diagram showing a main wiring 11 'of the second specific example. Here, with respect to the four pads 12 arranged at the pitch p, four wiring portions 11A 'having a concentric circular arc of 90 degrees (the length in the direction of the main wiring 11 is 4p) and the length s. The four wirings are combined with the parallel linear wiring portion 11B 'to connect between the four adjacent pads 12.

【0014】この例でも、曲げ回数は4回がその曲げ回
数を最も少なくする配線である。このように配線する
と、4本の主幹配線11は等長化される。また、円弧を
用いていることにより、角度を付けて曲げる場合に比べ
て、曲げ部分による反射の影響が少なくなる。さらに、
円弧の長さの和が各配線で等しいので、円弧状の配線部
11A’と直線配線部11B’の信号伝播遅延時間差を
考慮せずに、信号の伝播遅延が完全に等しい配線を実現
できる。
Also in this example, the number of bending times is four, which is the wiring that minimizes the number of bending times. With such wiring, the four main wires 11 are made equal in length. Further, the use of the arc reduces the influence of the reflection by the bent portion as compared with the case where the bending is performed at an angle. further,
Since the sum of the lengths of the arcs is the same for each wiring, it is possible to realize wirings in which signal propagation delays are completely equal without considering the signal propagation delay time difference between the arc-shaped wiring portion 11A 'and the linear wiring portion 11B'.

【0015】図10は第3の具体例の主幹配線11”を
示す図である。ここでは、ピッチpで並んだ4個のパッ
ド12に対して、90度で曲げた4本の配線部11A”
(主幹配線11の方向の長さは4p)と、長さsで4本
の配線が平行な直線配線部11B”とを組み合わせて、
隣の4個のパッド12との間を接続する。この例でも、
図8に示した第1の具体例の主幹配線11とほぼ同様な
作用効果がある。
FIG. 10 is a diagram showing a main wiring 11 "of a third specific example. Here, four wiring portions 11A bent at 90 degrees with respect to four pads 12 arranged at a pitch p. "
(The length of the main wiring 11 in the direction of 4p) is combined with a straight wiring portion 11B "having a length s and four wirings parallel to each other.
Connection is made between four adjacent pads 12. In this example,
The operation and effect are almost the same as those of the main wiring 11 of the first specific example shown in FIG.

【0016】図11に図7に示した従来の主幹配線41
のパッド42a−42b間の配線長と、図8に示した本
発明の第1の具体例の主幹配線11のパッド12a−1
2b間の配線長と、図9に示した本発明の第2の具体例
の主幹配線11’のパッド間12a’−12b’の配線
長と、図10に示した本発明の第3の具体例の主幹配線
11’のパッド間12a”−12b”の配線長の比較を
示す。なお、ピッチpはp=0.5mm、長さsはs=10mm
である。
FIG. 11 shows a conventional main wiring 41 shown in FIG.
The wiring length between the pads 42a-42b and the pad 12a-1 of the main wiring 11 of the first specific example of the present invention shown in FIG.
The wiring length between 2b, the wiring length between the pads 12a'-12b 'of the main wiring 11' of the second specific example of the present invention shown in FIG. 9, and the third specific example of the present invention shown in FIG. A comparison of the wiring length between the pads 12a "-12b" of the main wiring 11 'of the example is shown. The pitch p is p = 0.5 mm and the length s is s = 10 mm
It is.

【0017】これによれば、従来の主幹配線41の場合
は29.0mm、第1の具体例の主幹配線11の場合は27.07m
m、第2の具体例の主幹配線11’の場合は27.85mm、第
3の具体例の主幹配線11”場合は30.00mmの配線長で
ある。第1の具体例の主幹配線11の場合が最も短い。
第3の具体例の主幹配線11”は最も長くなっている
が、分岐配線が必要ないこと、同一曲げ回数で等長化で
きること等により、従来例より優れている。
According to this, the conventional main wiring 41 is 29.0 mm, and the main wiring 11 of the first specific example is 27.07 m.
m, the length of the main wiring 11 'of the second specific example is 27.85 mm, and the length of the main wiring 11 "of the third specific example is 30.00 mm. The case of the main wiring 11 of the first specific example is Shortest.
Although the main wiring 11 "of the third specific example is the longest, it is superior to the conventional example because the branch wiring is not required and the length can be made equal with the same number of bendings.

【0018】[0018]

【発明の効果】以上から本発明によれば、送信用素子か
ら1又は2以上の受信用素子に信号をバス接続する装置
において、主幹配線から受信用素子に至る分岐配線をな
くすことができるので、主幹配線と素子間の信号波形の
多重反射の影響を最小に抑えることができる。また、分
岐配線のための余分な配線層を設ける必要が無くなり、
配線層数を削減できる。さらに、曲げ回数の等しい蛇行
配線により曲げ配線部と直線配線部の信号伝播遅延時間
差を考慮せずに、主幹配線間伝送信号のタイミングのバ
ラツキを完全にゼロにすることができる。したがって、
従来の配線に比べて、バス幅に依存せず、高速な信号伝
送が可能になる。
As described above, according to the present invention, in a device for connecting a signal from a transmitting element to one or more receiving elements by bus, the branch wiring from the main wiring to the receiving element can be eliminated. In addition, the influence of the multiple reflection of the signal waveform between the main wiring and the element can be minimized. Also, there is no need to provide an extra wiring layer for branch wiring,
The number of wiring layers can be reduced. Furthermore, the meandering wiring having the same number of bends can completely eliminate the timing variation of the transmission signal between the main wirings without considering the signal propagation delay time difference between the bent wiring part and the straight wiring part. Therefore,
Compared to conventional wiring, high-speed signal transmission can be performed without depending on the bus width.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施の形態の多層配線板の主幹配
線を用いて送信用素子と受信用素子を接続した配線の説
明図である。
FIG. 1 is an explanatory diagram of wiring in which a transmitting element and a receiving element are connected using a main wiring of a multilayer wiring board according to an embodiment of the present invention.

【図2】 同実施の形態の主幹配線と受信用素子との間
の接続構造を示す説明図である。
FIG. 2 is an explanatory diagram showing a connection structure between a main wiring and a receiving element according to the embodiment;

【図3】 同実施の形態の主幹配線と受信用素子との間
の接続構造を示す断面図である。
FIG. 3 is a cross-sectional view showing a connection structure between a main wiring and a receiving element according to the embodiment.

【図4】 従来の多層配線の主幹配線と分岐配線を用い
て送信用素子と受信用素子を接続した配線の説明図であ
る。
FIG. 4 is an explanatory diagram of wiring in which a transmitting element and a receiving element are connected using a main wiring and a branch wiring of a conventional multilayer wiring.

【図5】 同従来例の主幹配線と受信用素子との間の接
続構造を示す説明図である。
FIG. 5 is an explanatory diagram showing a connection structure between a main wiring and a receiving element of the conventional example.

【図6】 同従来例の主幹配線と受信用素子との間の接
続構造を示す断面図である。
FIG. 6 is a cross-sectional view showing a connection structure between a main wiring and a receiving element of the conventional example.

【図7】 従来の多層配線板の主幹配線と分岐配線によ
る配線の等長化を図った配線説明図である。
FIG. 7 is an explanatory diagram of wiring in which a main wiring and a branch wiring of a conventional multilayer wiring board are made equal in length.

【図8】 本発明の第1の具体例の主幹配線による配線
の等長化を図った配線説明図である。
FIG. 8 is an explanatory diagram of wiring in which the length of the wiring by the main wiring of the first specific example of the present invention is made equal.

【図9】 本発明の第2の具体例の主幹配線による配線
の等長化を図った配線説明図である。
FIG. 9 is a wiring explanatory diagram for equalizing the length of a main wiring according to a second specific example of the present invention.

【図10】 本発明の第3の具体例の主幹配線による配
線の等長化を図った配線説明図である。
FIG. 10 is a wiring explanatory diagram for equalizing the length of a main wiring according to a third specific example of the present invention.

【図11】 本発明と従来例のバス配線の配線長の比較
説明図である。
FIG. 11 is an explanatory diagram for comparing the wiring lengths of the bus wiring of the present invention and the conventional example.

【符号の説明】[Explanation of symbols]

10:本実施の形態の多層配線板、11,11’,1
1”:主幹配線、12,12a,12b,12a’,1
2b’,12a”,12b”:パッド、13:接続ビ
ア、20:送信用素子、30:受信用素子、31:接続
リード、40:従来の多層配線板、41:主幹配線、4
2:パッド、43,44:接続ビア、45:分岐配線。
10: multilayer wiring board of the present embodiment, 11, 11 ', 1
1 ″: main wiring, 12, 12a, 12b, 12a ′, 1
2b ', 12a ", 12b": pad, 13: connection via, 20: transmission element, 30: reception element, 31: connection lead, 40: conventional multilayer wiring board, 41: main wiring, 4
2: pad, 43, 44: connection via, 45: branch wiring.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】1又は2以上の受信用素子と該受信用素子
に電気信号を発信する送信用素子とを電気的に接続する
複数の配線パターンを具備する多層配線板において、 前記複数の配線パターンが、複数の主幹配線と、該複数
の主幹配線と前記受信用素子や送信用素子を接続する接
続部とを含み、 前記主幹配線を、平行且つ曲げ回数の等しい等長化され
た配線で形成したことを特徴とする多層配線板。
1. A multilayer wiring board comprising a plurality of wiring patterns for electrically connecting one or more receiving elements and a transmitting element for transmitting an electric signal to the receiving element, wherein the plurality of wirings are provided. The pattern includes a plurality of main wirings, and a connecting portion that connects the plurality of main wirings and the receiving element or the transmitting element, wherein the main wirings are parallel, equal-length wirings having the same number of bending times. A multilayer wiring board characterized by being formed.
【請求項2】前記主幹配線の曲げ部は、直角の曲げ部、
45度の曲げ部、又は90度円弧の曲げ部であることを
特徴とする請求項1に記載の多層配線板。
2. The bent portion of the main wiring, wherein the bent portion has a right angle,
2. The multilayer wiring board according to claim 1, wherein the multilayer wiring board is a 45-degree bent portion or a 90-degree arc bent portion.
【請求項3】前記接続部は、前記受信用素子又は前記送
信用素子の接続リードが接続されるパッドと、該パッド
と前記主幹配線を接続する接続ビアを含むことを特徴と
する請求項1に記載の多層配線板。
3. The device according to claim 1, wherein the connection portion includes a pad to which a connection lead of the reception element or the transmission element is connected, and a connection via connecting the pad and the main wiring. 2. The multilayer wiring board according to item 1.
JP9338243A 1997-11-25 1997-11-25 Multilayer wiring board Pending JPH11163531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9338243A JPH11163531A (en) 1997-11-25 1997-11-25 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9338243A JPH11163531A (en) 1997-11-25 1997-11-25 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH11163531A true JPH11163531A (en) 1999-06-18

Family

ID=18316283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9338243A Pending JPH11163531A (en) 1997-11-25 1997-11-25 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH11163531A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7055123B1 (en) 2001-12-31 2006-05-30 Richard S. Norman High-performance interconnect arrangement for an array of discrete functional modules
JP2008166428A (en) * 2006-12-27 2008-07-17 Sanyo Electric Co Ltd Circuit equipment and digital broadcasting receiver
JP2009182163A (en) * 2008-01-31 2009-08-13 Elpida Memory Inc Semiconductor module, board, and wiring method
JP2013118298A (en) * 2011-12-05 2013-06-13 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7055123B1 (en) 2001-12-31 2006-05-30 Richard S. Norman High-performance interconnect arrangement for an array of discrete functional modules
JP2008166428A (en) * 2006-12-27 2008-07-17 Sanyo Electric Co Ltd Circuit equipment and digital broadcasting receiver
JP2009182163A (en) * 2008-01-31 2009-08-13 Elpida Memory Inc Semiconductor module, board, and wiring method
US8054643B2 (en) 2008-01-31 2011-11-08 Elpida Memory, Inc. Semiconductor module, wiring board, and wiring method
JP2013118298A (en) * 2011-12-05 2013-06-13 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the same

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