JPH11163283A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent breaking based in the manufacturing process of a lower electrode for the capacitive element for DRAM information storage. SOLUTION: In a DRAM with memory cells formed of MISFETs Qs for selecting the memory cells formed onto the main surface of a semiconductor substrate 1 and capacitive elements C for storing information being formed to the upper section of the MISFETs Qs and consisting of lower electrodes 21, capacitive insulating films 22 and plate electrodes 23, reinforcing members 24 are formed on the outer circumferential walls of the columnar sections of the lower electrodes 21. The reinforcing members 24 are constituted of a material (such as a silicon oxide film through CVD method) having an etching rate slower than that of the material (such as an SOG film) of a core member for forming erecting sections 21c of the lower electrodes 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
(c) Random Access Memory).

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memory)
The ry) memory cells are arranged at intersections of a plurality of word lines and a plurality of bit lines arranged in a matrix on the main surface of the semiconductor substrate, and one memory cell selecting MISFET (M
etal Insulator SemiconductorField Effect Transisto
r) and one information storage capacitance element (capacitor) connected in series to this. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. Have been. The bit line is arranged above the memory cell selecting MISFET,
Two memory cell selecting MISs adjacent in the extending direction
It is electrically connected to one of the source and drain shared by the FET. The information storage capacitance element is similarly disposed above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

Japanese Patent Application Laid-Open No. 9-55479 discloses a capacitor having an information storage capacitor disposed above a bit line.
A DRAM having a Capacitor Over Bitline structure is disclosed. DR described in this publication
In order to compensate for the decrease in the amount of charge (Cs) stored in the information storage capacitor due to the miniaturization of the memory cell, AM uses a cylindrical lower electrode (storage electrode) of the information storage capacitor arranged above the bit line. The surface area is increased by processing into a shape, and a capacitor insulating film and an upper electrode (plate electrode)
And form.

The lower electrode is composed of a cylindrical portion having an opening upward and a cylindrical portion for supporting the cylindrical portion, and a portion of the cylindrical portion is exposed to expose not only the inner surface and the side surface of the cylindrical portion but also the cylindrical portion. A capacitance insulating film and an upper electrode are also formed on the bottom surface of the portion and the side surface of the columnar portion, so as to increase the amount of accumulated charges.

[0005]

However, in the above structure, the cylindrical portion supporting the cylindrical portion is formed by a part of the polycrystalline silicon film constituting the lower electrode formed in the connection hole. Yes, it is formed with a considerably smaller diameter than the cylindrical portion, resulting in an unstable structure. Further, as the degree of integration increases, the side wall of the cylindrical portion tends to increase due to the necessity of securing a necessary amount of accumulated charge, and the instability of the structure tends to further increase.

Therefore, when the lower electrode is exposed in the process of manufacturing the semiconductor integrated circuit device, the cylindrical portion formed on the upper portion cannot be supported by the cylindrical portion, and the cylindrical portion is mechanically broken, and the semiconductor integrated circuit is broken. This may cause a failure in the device.

An object of the present invention is to reduce product defects due to breakage in the manufacturing process of the lower electrode and improve the product yield.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention comprises an information storage capacitor having a cylindrical portion having an opening above and a lower electrode comprising a columnar portion supporting the cylindrical portion; A semiconductor integrated circuit device including a DRAM in which a memory element is formed by a memory cell selection MISFET and a memory cell selection MISFET in which a capacitance element is connected in series, and wherein an information storage capacitance element is formed above the memory cell selection MISFET,
The reinforcing member is provided on the outer wall of the columnar portion.

According to such a semiconductor integrated circuit device,
Since the reinforcing member is provided on the outer wall of the columnar portion, breakage at the columnar portion can be prevented. As a result, it is possible to stably form the lower electrode, suppress occurrence of defects, and improve the product yield.

The reinforcing member is formed by a first insulating film (for example, SOG) formed therein when forming the cylindrical portion.
The second insulating film (for example, a silicon oxide film formed by a CVD method) having a lower etching rate than that of the second insulating film. Thereby, the reinforcing member can be formed without particularly increasing or changing the manufacturing process as described later.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized in that an information storage capacitive element having a cylindrical portion having an opening above and a lower electrode comprising a columnar portion supporting the cylindrical portion; A memory cell is formed by a memory cell selecting MISFET in which an information storage capacitor is connected in series,
A method of manufacturing a semiconductor integrated circuit device including a DRAM in which an information storage capacitor is formed above a memory cell selecting MISFET, comprising: (a) forming a memory cell selecting MISFET formed on a main surface of a semiconductor substrate; After sequentially depositing a first insulating film (eg, a silicon nitride film) and a second insulating film (eg, a silicon oxide film formed by a CVD method) having an etching selectivity with respect to the first insulating film, the second insulating film Forming a connection hole by opening the first insulation film; (b) depositing a first conductive film constituting a part of the lower electrode on the second insulation film including the inside of the connection hole; A step of depositing a third insulating film (for example, an SOG film) having an etching rate higher than that of the second insulating film, and (c) patterning the third insulating film and the first conductive film to be a core when forming a cylindrical portion Core member Forming a part of the fine lower electrode,
(D) A second conductive film is deposited on the entire surface of the semiconductor substrate, and the second conductive film is etched by anisotropic etching to form side walls made of the second conductive film on some side surfaces of the core member and the lower electrode. (E) performing wet etching on the semiconductor substrate, removing a part of the third insulating film and the second insulating film using the first insulating film as an etching stopper, exposing a cylindrical portion of the lower electrode, and forming a columnar shape. Forming a reinforcing member made of the second insulating film on the outer wall of the portion.

According to such a method of manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device described in (1) can be manufactured.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a diagram showing a DR according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating an example of an AM for a memory cell array region.

A field insulating film 2 for element isolation is formed on the main surface of a semiconductor substrate 1 made of p-type single crystal silicon. The field insulating film 2 is made of LOCOS (Local
Oxidation of Silicon) can be used as a thick silicon oxide film. This field insulating film 2
The active region 3 is formed on the main surface of the semiconductor substrate 1 as a region surrounded by
Is formed.

The active region 3 is a semiconductor region 4 located at the center of the active region 3, a semiconductor region 5 located at both ends of the active region 3, and a semiconductor region 4 between the semiconductor region 4 and the semiconductor region 5 for selecting a memory cell. It can be divided into two channel regions 6 located below the gate electrode of the MISFET.

The semiconductor region 4 and the bit line BL are connected through a contact hole 7 opened to connect to the semiconductor region 4. A plug 9 connected to the semiconductor region 5 and the information storage capacitor C is connected through a contact hole 8 formed on the semiconductor region 5.

The bit line BL is arranged so as to be orthogonal to the word line WL. The linear portion of the bit line BL is formed so as to be shifted from the center of the contact hole 7 so as not to overlap with the contact hole 8, and has a protruding portion BLDB for completely surrounding the contact hole 7. Projection BLD
The formation of the linear portions of B and the bit lines BL can be performed by two-stage exposure as described later.

In the active region 3 of the semiconductor substrate 1, a p-type well 10 is formed. An n-type deep well 11 is formed so as to surround the p-type well 10. Note that a threshold voltage adjustment layer may be formed in the p-type well 10.

MISFETs Qs for selecting a DRAM memory cell are formed on the main surface of the p-type well 10.

The memory cell selection MISFET Qs is p
A gate electrode 13 formed on the main surface of the p-type well 10 via the gate insulating film 12 and a main surface of the p-type well 10 on both sides of the gate electrode 13 and doped with an n-type impurity such as phosphorus or arsenic Semiconductor regions 4 and 5.

Gate insulating film 12 is made of, for example, a silicon oxide film formed by thermal oxidation.
Can be, for example, a laminated film of a polycrystalline silicon film 13a and a silicide film 13b. Silicide film 1
Examples of 3b include metal silicides such as tungsten and titanium.

A cap insulating film 14 made of a silicon nitride film and a sidewall spacer 15 are formed on the upper layer and the side wall of the gate electrode 13 of the memory cell selecting MISFET Qs, respectively. Note that the memory cell selection MI
The gate electrode 13 of the SFET Qs is connected to the word line W of the DRAM.
Part of L.

The memory cell selecting MISFET Qs is covered with an interlayer insulating film 17. The interlayer insulating film 17 includes, for example, a silicon oxide film 17a formed by a thermal CVD (Chemical Vapor Deposition) method and a BPSG (Boron-Ph
(osporaus-Silicate Glass) film 17b, and a silicon oxide film 17c formed by a thermal CVD method.

The bit line BL is formed on the interlayer insulating film 17. Bit line BL can be, for example, a laminated film of polycrystalline silicon film 18a and silicide film 18b. The silicide film 18b can be, for example, a metal silicide film of tungsten, titanium, or the like.
Further, a silicon oxide film 18c formed by, for example, a thermal CVD method is formed at a portion of the projecting portion BLDB of the bit line BL.

The bit line BL is connected via a contact hole 7 to a semiconductor region 4 shared by a pair of memory cell selecting MISFETs Qs. A plug 9 is formed in a contact hole 8 opened on each semiconductor region 5 of the pair of memory cell selecting MISFETs Qs. Plug 9 may be, for example, polycrystalline silicon doped with an n-type impurity.

The bit line BL is covered with an interlayer insulating film 19. The interlayer insulating film 19 can be a laminated film of a silicon oxide film 19a and a silicon nitride film 19b.

An information storage capacitor C is formed on the interlayer insulating film 19.

The information storage capacitive element C is composed of a lower electrode 21 connected to the plug 9 through a contact hole 20, a capacitive insulating film 22, and a plate electrode 23. The lower electrode 21 can be a polycrystalline silicon film doped with an impurity, and the capacitance insulating film 22 can be a stacked film of a silicon nitride film and a silicon oxide film, for example. Further, the plate electrode 23 can be a polycrystalline silicon film doped with impurities.

The lower electrode 21 has a mask portion 21a and a side wall spacer 2a used as a hard mask when forming the contact hole 20 as described later.
1b, a standing portion 21c for increasing the storage capacity by increasing the surface area of the lower electrode 21, and a contact portion 21d formed in the contact hole 20 for connection to the plug 9.

The lower electrode 21 has a cylindrical portion and a columnar portion. That is, the cylindrical portion is a cylindrical portion having an opening upward, and the upright portion 21c, the mask portion 21a, the side wall spacer 21b, and the contact portion 21d.
Portion 21a and sidewall spacer 2
1b. On the other hand, the columnar portion is a portion of the contact portion 21d that does not contact the mask portion 21a and the sidewall spacer 21b, and is a portion that supports the cylindrical portion.

As described above, by forming the lower electrode 21 with the cylindrical portion and the columnar portion, in addition to the inner surface of the cylindrical portion and the outer wall of the standing portion 21c, the bottom surface of the cylindrical portion, that is, the mask portion 21a and the side wall are formed. The bottom surface of the spacer 21b can also be used as the surface of the lower electrode 21, and its surface area can be increased to increase the amount of accumulated charges.

On the outer wall of the columnar portion of the lower electrode 21, a reinforcing member 24 made of, for example, a silicon oxide film formed by a CVD method is formed. Thus, the reinforcing member 2
4 to form a columnar portion, that is, a contact portion 2.
The mechanical strength of 1d can be improved, and as will be described later, breakage at the columnar portion of the lower electrode 21 in the manufacturing process can be prevented and the manufacturing yield of the DRAM can be improved. Further, by using the silicon oxide film formed by the CVD method as the reinforcing member 24, the manufacturing of the reinforcing member 24 can be easily performed as described later.

An interlayer insulating film, wiring, and the like can be further formed on the upper layer of the information storage capacitive element C, but the description is omitted.

Next, a method of manufacturing the memory cell of the DRAM will be described with reference to FIGS. 2 to 15 are sectional views showing an example of a method of manufacturing the DRAM of the present embodiment in the order of steps.

First, as shown in FIG. 2, a semiconductor substrate 1 made of p ^- type silicon single crystal is prepared, and a known LOCO
A thick field insulating film 2 is formed on the surface by using the S method. By forming the field insulating film 2, an active region 3 is formed as a region surrounded by the field insulating film 2. The thickness of the field insulating film 2 is, for example, about 400 nm.

Next, as shown in FIG. 3, using a photoresist as a mask, an n-type impurity (for example, phosphorus (P)) and a p-type impurity (for example, boron (B)) are ion-implanted into the memory of the semiconductor substrate 1. The semiconductor substrate 1 is introduced into a cell array formation region and then the photoresist is removed, and then a p-type well 10 and a deep well 11 are formed by subjecting the semiconductor substrate 1 to a thermal diffusion process. Next, in order to optimize the impurity concentration in the channel region 6 and obtain a desired threshold voltage of the memory cell selecting MISFET, a p-type impurity (for example, fluoride) is added to the main surface of the active region of the p-type well 10. Boron (BF2)) is ion-implanted.

Next, as shown in FIG. 4, the surface of the semiconductor substrate 1 is etched with a hydrofluoric acid solution to remove the silicon oxide film.
The gate insulating film 12 of the ISFET is formed. This gate insulating film 12 is formed by a thermal oxidation method, and its thickness is, for example, about 9 nm. Thereafter, a gate electrode 13 integrally formed as a word line WL is formed on the gate insulating film 12.

The gate electrode 13 is formed by sequentially depositing a P-doped polycrystalline silicon film, a silicide (for example, WSi ₂ ) film, a silicon oxide film, and a silicon nitride film on the entire surface of the semiconductor substrate 1. Are sequentially etched to form a polysilicon film 13a and a silicide film 13a.
This is performed by forming b. A silicon oxide film 25a and a cap insulating film 14 are formed on silicide film 13b. The polycrystalline silicon film 13a and the silicide film 13b are formed by a CVD method, and their thicknesses are, for example, 70 nm and 150 nm, respectively.
Further, the silicon oxide film 25a and the cap insulating film 14
Are formed by a CVD method, and their film thicknesses are, for example, 10 nm and 200 nm, respectively.

Thereafter, the semiconductor substrate 1 is subjected to a thermal oxidation process to form a thin silicon oxide film 25b on the side walls of the polycrystalline silicon film 13a and the silicide film 13b forming the gate electrode 13.

Further, an n-type impurity (for example, P) is ion-implanted into the main surface of the p-type well 10 by using the laminated film as a mask, and the n-type impurity is stretched and diffused, thereby forming the memory cell selecting MISFET. Semiconductor regions 4 and 5 functioning as a source region and a drain region are formed.

Next, as shown in FIG. 5, a silicon nitride film (not shown) deposited on the semiconductor substrate 1 by the CVD method is etched by anisotropic etching such as RIE (Reactive Ion Etching). MISF for memory cell selection
A side wall spacer 15 is formed on the side wall of the gate electrode 13 of ET.

Next, as shown in FIG. 6, a silicon oxide film 17a and a BPSG film 17b are deposited on the semiconductor substrate 1 by thermal CVD using, for example, TEOS as a source gas, and then a contact hole 8 is opened. The contact hole 8 can be formed by a known dry etching method. Further, the BPSG film 17b can be planarized by reflow.

Next, after ion implantation of an n-type impurity into the contact hole 8, a plug 9 is formed as shown in FIG. 7, and a silicon oxide film 17c is formed by thermal CVD using TEOS as a source gas, for example. accumulate. Plug 9
It can be formed by depositing a polycrystalline silicon film in which an n-type impurity is doped at a high concentration, and etching back the film.

Next, as shown in FIG. 8, a contact hole 7 is formed. The contact hole 7 can be formed by a known dry etching method.

Next, as shown in FIG. 9, a polycrystalline silicon film into which P is introduced, a silicide film and a silicon oxide film are sequentially deposited on the semiconductor substrate 1 by the CVD method, and formed by the first exposure. The silicon oxide film is etched using the photoresist as a mask to form a silicon oxide film 18.
Form c. The silicon oxide film 18c is formed as a discrete pattern and is a pattern for forming the protruding portion BLDB of the bit line BL. In addition, since the distance between the patterns is sufficiently large, the exposure for forming the silicon oxide film 18c does not cause a reduction in resolution due to light interference.

Next, as shown in FIG. 10, the silicide film and the polycrystalline silicon film are etched using the linear photoresist formed by the second exposure and the silicon oxide film 18c as a mask, and Bit line BL composed of film 18a and silicide film 18b
To form The bit line BL is connected to one semiconductor region 4 of the memory cell selecting MISFET through a contact hole 7.

This bit line BL is formed of a linear photoresist and a silicon oxide film 18 forming a protrusion BLDB.
c. Since a linear photoresist is formed by exposing a photoresist to a linear pattern, the interaction of exposure light between adjacent patterns is unlikely to occur. The resolution does not decrease and the pattern does not swell or constrict. As a result, defects due to disconnection or short circuit of the bit line BL can be reduced, and the yield of the DRAM can be improved. In addition, since the second exposure is performed independently of the first exposure,
Even if there is a protrusion BLDB, it is not affected by the second exposure. As a result, the distance between the adjacent linear patterns of the bit lines BL formed in the second exposure can be made close to the vicinity of the limit of the exposure resolution, and the integration degree of the DRAM can be improved.

In this embodiment, an example is shown in which the contact hole 7 is opened after the plug 9 is formed to form the bit line BL. However, the contact hole 8 and the contact hole 7 are simultaneously opened. A plug 9 may be formed in the contact holes 7 and 8. In this case, the projecting portion BLDB of the bit line BL is not necessary, and the bit line BL
Is formed and connected to the plug in an out-of-sight condition.

Next, as shown in FIG. 11, after a silicon oxide film 19a and a silicon nitride film 19b (first insulating film) are deposited by, for example, a CVD method, the silicon oxide film 19a and the silicon nitride film 19b are formed by, for example, a CVD method using TEOS. A film 26 is deposited. The silicon oxide film 26 can be planarized by an etch-back method or a CMP (Chemical Mechanical Polishing) method. Thereafter, after depositing a polycrystalline silicon film into which P is introduced, an opening is formed at a position where a contact hole 20 for connecting the information storage capacitor C and the plug 9 is opened, and a mask portion of the lower electrode 21 is formed. 21a
To form Further, a polycrystalline silicon film into which P is introduced is deposited on the entire surface of the semiconductor substrate 1 and is etched by anisotropic etching to form a sidewall spacer 21b. By forming the side wall spacers 21b in this manner, it is possible to open the contact hole 20 with a size smaller than the exposure limit.

Next, as shown in FIG. 12, the mask portion 21a
A contact hole 20 is opened using the sidewall spacer 21b as a mask (hard mask), and a polycrystalline silicon film with P introduced therein and an SOG film are sequentially deposited on the entire surface of the semiconductor substrate 1. Thereafter, using the photoresist as a mask, the silicon oxide film is etched, and then the polycrystalline silicon film and the mask portion 21a are sequentially etched to form a cap insulating film 27, a contact portion 21d,
The mask part 21a is formed. The cap insulating film 27 is made of the SOG film as described above, and
This is a core member for forming c.

Next, after removing the photoresist,
As shown in FIG. 13, a polycrystalline silicon film is
Then, the polycrystalline silicon film is
E by anisotropic etching such as E
1c is formed, and the lower electrode 21 including the mask portion 21a, the sidewall spacer 21b, the standing portion 21c, and the contact portion 21d is completed.

Next, as shown in FIG. 14, the cap insulating film 27 and the silicon oxide film 26 are removed. The cap insulating film 27 and the silicon oxide film 26 can be removed by, for example, wet etching using a hydrofluoric acid solution. As the hydrofluoric acid solution, HF: H ₂ O ₂ : H
A mixed solution of ₂ O = 1: 8: 400 can be exemplified.

At this time, part of the silicon oxide film 26 located on the side wall of the columnar portion of the lower electrode 21 is
4 is left. By forming the reinforcing member 24 in this manner, breakage of the lower electrode 21 can be prevented, and the production yield of the DRAM can be improved.

As described above, a part of the silicon oxide film 26 can be left as the reinforcing member 24 because the cap insulating film 27 has a lower etching rate than the silicon oxide film 26, that is, the silicon oxide film formed by the CVD method. This is because a fast SOG film is used. That is, CVD
While the etching rate of the silicon oxide film formed by the method is 210 nm / min, the etching rate of the SOG film is as high as 2680 nm / min, which is about 13 times as high. Therefore, the cap insulating film 27, which is an SOG film, and the CVD
When the etching with the silicon oxide film 26 as the silicon oxide film is started at the same time, the cap insulating film 27 as the SOG film is etched first, and then the silicon oxide film 26 is gradually etched. Therefore, the etching time is adjusted so that a part of the silicon oxide film 26 remains as the reinforcing member 24, and the reinforcing member 24
Can be formed. As described above, in the present embodiment, the etching is stopped halfway without etching the entire silicon oxide film 26 without adding a special process for forming the reinforcing member 24, and the reinforcing member 2
4 can be formed, and the conventional process can be used as it is. This makes it possible to easily form the reinforcing member 24 without adding a special step, prevent the lower electrode 21 from being broken, and improve the production yield of the DRAM.

Next, as shown in FIG. 15, a silicon nitride film (not shown) is deposited on the semiconductor substrate 1 by the CVD method.
Subsequently, by performing an oxidation process, a silicon oxide film is formed on the surface of the silicon nitride film, and a capacitance insulating film 22 including the silicon oxide film and the silicon nitride film is formed.
Thereafter, a polycrystalline silicon film (not shown) is deposited on the semiconductor substrate 1 by a CVD method, and the polycrystalline silicon film is etched by using a photoresist as a mask.
By forming the plate electrode 23, the DRAM shown in FIG. 1 is almost completed.

According to the DRAM of the present embodiment, since the reinforcing member 24 is formed on the outer peripheral wall of the columnar portion of the lower electrode 21, breakage of the lower electrode 21 can be prevented, and the DRA
The production yield of M can be improved.

The reinforcing member 24 is formed by the lower electrode 2
By forming the cap insulating film (core member of the cylindrical portion) 27 for forming the first standing portion 21c as the SOG film and the silicon oxide film 26 as the reinforcing member 24 as the silicon oxide film formed by the CVD method. By using the difference in the etching rate, it is possible to easily form the semiconductor device, and it is possible to use the conventional process as it is without requiring a special process.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, the silicon oxide film 26 and the SOG film formed by the CVD method have been exemplified as the silicon oxide film 26 and the cap insulating film 27, but the materials are not limited to these. That is, as the silicon oxide film 26, C
When a silicon oxide film formed by the VD method is used, the cap insulating film 27 is not limited to an SOG film as long as the material has a higher etching rate than a silicon oxide film formed by the CVD method. For example, a BPSG film, a PSG film, BSG
It may be a film or the like. When an SOG film is used as the cap insulating film 27, the silicon oxide film 26
Any material having an etching rate lower than that of the OG film may be used.
For example, it may be a BPSG film, a PSG film, a BSG film, or the like.

The polycrystalline silicon film doped with impurities has been exemplified as the material of the lower electrode 21.
It may be a metal film such as a titanium nitride film, a tungsten film, or a stacked film thereof. Further, an oxide of a metal such as iridium or ruthenium, which is a conductor, may be used.

[0064]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to prevent breakage in the manufacturing process of the lower electrode, reduce product defects due to the breakage, and improve the product yield.

Further, the production of a reinforcing member for preventing breakage can be easily carried out using the conventional steps as they are.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an example of a DRAM according to an embodiment of the present invention with respect to a memory cell array region.

FIG. 2 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 12 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 13 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 14 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field insulating film 3 active region 4 semiconductor region 5 semiconductor region 6 channel region 7 contact hole 8 contact hole 9 plug 10 p-type well 11 deep well 12 gate insulating film 13 gate electrode 13a polycrystalline silicon film 13b silicide film 14 Cap insulating film 15 Sidewall spacer 17 Interlayer insulating film 17a Silicon oxide film 17b BPSG film 17c Silicon oxide film 18a Polycrystalline silicon film 18b Silicide film 18c Silicon oxide film 19 Interlayer insulating film 19a Silicon oxide film 19b Silicon nitride film 20 Contact hole 21 Lower electrode 21a Mask part 21b Sidewall spacer 21c Erect part 21d Contact part 22 Capacitive insulating film 23 Plate electrode 24 Reinforcing member 25a Silicon oxide film 25b silicon oxide film 26 silicon oxide film 27 cap insulating film BL bit line BLDB protrusion C information storage capacitor Qs memory cell selection MISFET WL word line

Claims (5)

[Claims] 1. An information storage capacitor comprising a cylindrical portion having an opening above and a lower electrode comprising a columnar portion supporting the cylindrical portion, and the information storage capacitor are connected in series. A semiconductor integrated circuit device including a DRAM formed above the memory cell selecting MISFET, wherein the information storage capacitive element comprises a DRAM formed above the memory cell selecting MISFET; A semiconductor integrated circuit device comprising a member. 2. The semiconductor integrated circuit device according to claim 1, wherein the reinforcing member has a lower etching rate than a first insulating film formed therein when forming the cylindrical portion. 2. A semiconductor integrated circuit device comprising two insulating films. 3. The semiconductor integrated circuit device according to claim 2, wherein said first insulating film is an SOG film, and said second insulating film is a silicon oxide film formed by a CVD method. A semiconductor integrated circuit device characterized by the above-mentioned. 4. An information storage capacitor having a cylindrical portion having an opening above and a lower electrode comprising a columnar portion supporting the cylindrical portion, and the information storage capacitor are connected in series. A method for manufacturing a semiconductor integrated circuit device including a DRAM in which a memory cell is constituted by a memory cell selection MISFET and the information storage capacitor element is formed above the memory cell selection MISFET, comprising: The memory cell selecting MISF formed on the main surface of the substrate
After sequentially depositing a first insulating film and a second insulating film having an etching selectivity with respect to the first insulating film on the ET, the second insulating film and the first insulating film are opened to form a connection hole. (B) depositing a first conductive film constituting a part of the lower electrode on the second insulating film including the inside of the connection hole, and further having an etching rate lower than that of the second insulating film; Depositing a fast third insulating film; and (c) depositing the third insulating film.
Patterning an insulating film and a first conductive film to form a core member serving as a core when forming the cylindrical portion and a part of the lower electrode, and (d) forming a second layer on the entire surface of the semiconductor substrate.
Depositing a conductive film and etching the second conductive film by anisotropic etching to form a side wall portion made of the second conductive film on a side surface of a part of the core member and the lower electrode; (e) The semiconductor substrate is subjected to wet etching, the third insulating film and a part of the second insulating film are removed using the first insulating film as an etching stopper, and a cylindrical portion of the lower electrode is exposed, and the columnar shape is formed. Forming a reinforcing member made of the second insulating film on an outer wall of the portion. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said first insulating film is a silicon nitride film, and said second insulating film is a silicon oxide film formed by a CVD method. ,
The method for manufacturing a semiconductor integrated circuit device, wherein the third insulating film is an SOG film.