JPH11162180A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the maximum number of rewrites and holding time. SOLUTION: The memory reads identical data stored in three or more memory cell arrays 200, 201, 202 at once, compares the level of a voltage corresponding to the sum of three or more read currents with that of a reference voltage 204 and outputs the level comparison result as read data of the three or more memory cell arrays 200, 201, 202.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can reliably read a cell current even if the number of rewritable times increases or the holding time becomes long.

[0002]

2. Description of the Related Art In recent years, FeRAM (Ferro-electric Ran)
dom Access Memory), EPROM (Erasable and Pro
Grammable Read Only Memory), EEPROM (Electr
ical Erasable and Programmable Read Only Memory)
Non-volatile semiconductor memories such as these have attracted attention. EPR
In OM and EEPROM, electric charge is stored in the floating gate,
Data is stored by detecting a change in threshold voltage due to the presence or absence of electric charges by the control gate. The EEPROM includes a flash EEPROM that erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells constituting a flash EEPROM are roughly classified into a split gate type and a stacked gate type. Split gate type flash EE
A PROM is disclosed in WO 92/18980 (G11C 13/00). FIG. 4 shows the publication (WO92 / 1898).
0) Split gate type memory cell 1
01 shows a cross-sectional structure.

An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. Source S
A floating gate FG is formed on a channel CH sandwiched between the gate and the drain D via a first insulating film 103. The control gate CG is formed over the floating gate FG with the second insulating film 104 interposed. Part of the control gate CG is arranged on the channel CH via the first insulating film 103,
The selection gate 105 is configured. Second insulating film 104
The data is stored by storing electrons in the floating gate FG surrounded by.

[0005]

In the case where electrons are stored in the floating gate FG, the cell current flowing through the memory cell decreases as the number of times of rewriting increases, so that stable writing and reading of data cannot be performed. This is because the second insulating film 1
04 is deteriorated, making it difficult for electrons to escape from the floating gate FG.
And then return to the floating gate FG again, the potential of the floating gate FG decreases, and the floating gate F
This is probably because a channel is formed under G, which makes it difficult.

[0006] This deterioration differs from cell to cell and has variations. If it is extremely bad, reading cannot be performed. This problem is remarkable in a nonvolatile semiconductor memory device, but cell information may not be read due to a defect of a memory cell even in a normal semiconductor memory device. A problem arises when important data is stored in such a memory cell.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and simultaneously reads out three or more memory cell arrays storing the same data and reads out three or more memory cell arrays. Of the reference current and a voltage corresponding to the sum of the read currents of
The data is output as read data of one or more memory cell arrays.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described using a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device of the present invention, the same data is stored in three (three or more) memory cell arrays.
The three memory cell arrays are read simultaneously, a level corresponding to the sum of the three read currents is compared with a reference voltage, and the level comparison result is output as read data of the three memory cell arrays.

Thus, if electrons are not injected into the floating gates of the three memory cells, the cell current at the time of reading flows three times in total. So, 3
The level comparison between the voltage corresponding to the doubled current and the reference voltage corresponding to the intermediate 1.5 times the current is performed. The level comparison result is derived as a read output. This gives 3
Even if one of the read cell currents does not flow, it is possible to determine the total with a sufficient margin with respect to the reference voltage.

Conversely, assume that electrons are injected into the floating gates of the three memory cells, and no cell current flows. In this state, even if only one cell current flows for some reason, it does not reach 1.5 with only one cell current, and it is determined that no current flows. Accordingly, the detection accuracy of reading is increased, and the number of rewritable times and the holding time of the semiconductor memory device can be increased.

Assuming that 3I (I is a current flowing according to one memory cell) flows when three memory cell arrays are used, for example, a current of 1.5I is used for generating a reference voltage. Thereby, even if one of the three memory cell arrays stops operating and the current becomes zero, it can be determined. The magnitude of the reference voltage can be freely changed according to the design concept. For example, it may be 1.2I or 1.7I.

Further, the number of the memory cell arrays of the parameter can be increased to three or more. For example, when 5 memory cell arrays are used, 2.5I may be used as the reference voltage. In this case, it can be determined if up to three are operating. FIG. 1 is an overall view of a semiconductor memory device according to the present invention. In FIG. 1, three independent memory cell arrays 200, 201, 2
02, and the row decoders 200A, 201
A, 202A and column decoders 200B, 201B,
202B and the sense amplifiers 200C, 201C, 202
C is independently owned.

The basic operation of the memory cell array shown in FIG. 1 will be described. FIG. 2 shows a split gate type memory cell 10.
1 shows an overall configuration of a flash EEPROM 121 using the same. The memory cell array 122 includes a plurality of memory cells 1
01 are arranged in a matrix. The control gates CG of the memory cells 101 arranged in the row direction are connected to common word lines WLa to WLz. Each memory cell 1 arranged in a column direction
01 is connected to the common bit lines BLa to BLz. The sources S of all the memory cells 101 are connected to a common source line SL.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and column address applied from the outside are applied to the address pin 1
25. The row address and the column address are sent from the address pin 125 to the address buffer 12.
6 to the address latch 127. Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124.

The row decoder 123 includes an address latch 1
Word line W corresponding to the row address latched at 27
La to WLZ are selected, and the selected word line is connected to the gate voltage control circuit 134. Column decoder 12
4 selects the bit lines BLa to BLz corresponding to the column addresses latched by the address latch 127 and connects the selected bit lines to the drain voltage control circuit 133.

The gate voltage control circuit 134 controls the potential of the word line connected via the row decoder 123 according to each operation mode shown in FIG. The drain voltage control circuit 133 controls the potential of the bit line connected via the column decoder 124 according to each operation mode shown in FIG. The common source line SL is connected to the source voltage control circuit 132. Source voltage control circuit 132
Controls the potential of the common source line SL in accordance with each operation mode shown in FIG.

Data specified externally is input to the data pin 128. The data is stored on data pin 128
Through the input buffer 129 and the column decoder 124
Transferred to The column decoder 124 controls the potential of the bit line selected as described above according to the data. Data read from any memory cell 101 is transmitted from bit lines BLa to BLz to column decoder 124.
Is transferred to the sense amplifier group 130 via the. The sense amplifier group 130 includes several sense amplifiers (not shown). The column decoder 124 connects the selected bit line to each sense amplifier.

The data determined by the sense amplifier group 130 is output from the output buffer 131 to the outside via the data pin 128. Each of the above circuits (123 to 13)
The operation of 4) is controlled by the control core circuit 140.
As described above, the erasing, writing, and reading of the memory cell array 122 are performed by the peripheral circuit as shown in FIG.

In the present invention, the configuration shown in FIG. 1 is used to store the same data in a plurality of memory cell arrays. In FIG. 1, address data from the address latch 127 is applied to the row decoder 200A and the column decoder 200B. Then, an address is specified by the row decoder 200A and the column decoder 200B, and data of the specified cell is read from the column decoder 200B. The read signal is amplified and output by the sense amplifier 200C.

On the other hand, the address data from the address latch 127 is also applied to the row decoders 201A and 202A and the column decoders 201B and 202B. Since the same data is stored in the same address in the memory cell arrays 200, 201, and 202, the memory cell array 2
01 and 202 generate the same data, and the sense amplifier 2
Generated from 01C and 202C. The sum of the three sense amplifiers 200C, 201C and 202C is compared with a reference voltage of a reference power supply 204 by a comparator 203.

FIG. 5 shows a specific circuit configuration of the comparator 203. The terminals 301 to 303 in FIG.
Output signals of 00C, 201C and 202C are applied. Now, the signal to be read is at "L" level,
Assuming that signals of “H” level are all applied to the terminals 301 to 303, the transistors 304, 305, 306
Turns on.

When reading data from the memory, the terminal 307,
An “H” level signal is applied to 308, 309, and 310, and the circuit is set to read enable (READ ENABLE). Since the transistors 304, 305, and 306 have the same transistor size, the on-resistance is the same,
Equal current Io flows and 3Io flows through transistor 314. Therefore, the current 3 is applied to the gate of the transistor 315.
A low voltage determined by Io and the ON resistance of the transistor 314 is generated.

On the other hand, transistors 311, 312, 31
3 has the same transistor size as the transistors 304, 305, and 306. Therefore, the current Io flows through the transistor 311 and the transistors 312 and 31
3, a current Io / 2 flows. Therefore, a current 1.5Io flows through the transistor 316. And the transistor 31
7, an intermediate voltage determined by the current 1.5Io and the on-resistance of the transistor 316 is generated.

The transistors 315 and 317 constitute a differential amplifier and compare the levels of two input voltages. In the above state, the gate of the transistor 317 is higher,
The transistor 317 turns on and the transistor 315 turns off. The transistors 318 and 319 are off,
Current mirror circuit 3 including transistors 320 and 321
22 operates. That is, the source of the transistor 317
The same current as the current flowing between the drains
15 supplied between the source and the drain of the transistor 3
The drain voltage at 15 increases. Therefore, output terminal 3
An output signal of "L" level is obtained at 23.

In this case, even if one of the cell currents from the three memory cell arrays does not flow and the magnitude of the signal applied to the terminals 301 to 303 decreases, the determination is made using the sum of the three. Of certainty increases.
Also, due to defective word lines, bit lines, decoders, etc.
If one of the three cell currents does not flow completely,
Current 2Io flows through transistor 314. For this reason,
A voltage determined by the current 2Io and the on-resistance of the transistor 314 is generated at the gate of the transistor 315. Even in this case, the current of 1.5 Io is applied to the gate of the transistor 317.
And a voltage determined by the on-resistance of the transistor 316, the gate voltage of the transistor 317 becomes higher.

Next, assuming that the signal to be read is at the "H" level and all the signals at the "L" level are applied to the terminals 301 to 303, the voltage VDD is applied to the gate of the transistor 315. Then, transistor 3
15 is turned on, and an “H” level output signal is obtained at the output terminal 323. Also in this case, the transistors 304 to 3
Even if any one of 06 is turned on, an output signal of "H" level can be obtained.

As shown in FIG. 1, three memory cell arrays 2
00, 201, and 201 are arranged independently, and row decoders 200A, 200B, and 200C, column decoders 200B, 201B, and 202B, and a sense amplifier 2 are provided.
Since 00C, 201C, and 202C are independently held, even if a defect such as a word line, a bit line, or a decoder occurs, the effect affects only one memory cell array, so that the operation is stabilized.

[0028]

According to the present invention, the read detection sensitivity is increased, and the number of rewritable times and the holding time of the semiconductor memory device can be increased. Further, according to the present invention, since a memory cell array, a row decoder, a column decoder, and a sense amplifier are independently held, even if a defect such as a word line, a bit line, or a decoder occurs, the influence is exerted on one memory cell array. The operation is stable because it only has an effect.

The semiconductor memory device of the present invention is particularly suitable for use in a nonvolatile semiconductor memory device in which data retention time is important.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device of the present invention.

FIG. 2 is a block diagram showing an overall view of a semiconductor memory device of the present invention.

FIG. 3 is a diagram illustrating operation modes applied to memory cells of the semiconductor memory device according to the present invention.

FIG. 4 is a sectional view of a memory cell of the semiconductor memory device of the present invention.

FIG. 5 is a specific circuit example of a comparator 203 of the semiconductor memory device of the present invention.

[Explanation of symbols]

 Reference Signs List 200 memory cell array 201 memory cell array 202 memory cell array 203 comparator 204 reference power supply 323 output terminal

Claims (2)

[Claims] 1. A method for simultaneously reading out three or more memory cell arrays storing the same data, comparing a level corresponding to the sum of the three or more read currents with a reference voltage, and comparing the levels. Is output as read data of the three or more memory cell arrays. 2. A voltage generating means for generating a voltage corresponding to the sum of read currents from three or more memory cell arrays storing the same data, and a reference for generating a reference voltage corresponding to the sum of the read currents Voltage generating means, and a level comparing means for comparing the output voltage of the voltage generating means with the output voltage of the reference voltage generating means,
A semiconductor memory device wherein a level comparison result of said level comparison means is output as read data of said three or more memory cell arrays.