JPH11154388A - Magnetoresistive memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetoresistive memory element which can take out a large output signal and in which power consumption can be reduced by mak ing the element such structure that element resistance is high and a resistance variation rate can be improved. SOLUTION: This element is provided with a gate insulation film 8 and a gate electrode 10 formed on a silicon substrate 1, a drain region 11 formed being adjacent a lower part channel region, a magnetoresistive element including magnetic particles 4, a tunnel oxide film, and a ferroelectric layer 6, and a source electrode 7 injecting carriers in the magnetoresistive element. And the direction of magnetization of the magnetoresistive element is controlled by the direction of a gate current made to flow in the gate electrode 10, further, carriers injected from the source electrode 7 are made flow in the silicon substrate 1 through tone magnetoresistive element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a magnetoresistive memory element using a magnetoresistive element.

[0002]

2. Description of the Related Art In recent years, a memory element (MRAM) utilizing a giant magnetoresistance effect (GMR) has been proposed (for example, JL Brown et al .: IEEE).
transaction of component
s, PART A, VOL17, p373 (199
4)). FIG. 24 shows the structure of this memory element. FIG.
, The first magnetic layer 101, the non-magnetic layer 102, the second
The magnetic layer 103, the insulating layer 104, and the electrode 105 are laminated. The first magnetic layer 101, the nonmagnetic layer 102, and the second magnetic layer 103 are so-called spin valve GMR films. The first magnetic layer 101 is a free layer (free layer) made of a soft magnetic material having a small coercive force, and the direction of magnetization changes freely according to external magnetization. The second magnetic layer 103 is a pinned layer (pin layer) made of a hard magnetic material having a large coercive force, and the direction of magnetization is pinned. The nonmagnetic layer 102 is made of a conductor such as Cu. The electrode 105 and the GMR film extend in directions orthogonal to each other, and are used as a word line and a bit line, respectively.

[0003] The operating principle of this memory element is as follows. Writing is performed by applying a relatively large current to the electrode (word line) 105 to generate a large magnetic field.
This is performed by fixing the magnetization direction of the second magnetic layer (pin layer) 103 in a predetermined direction. At this time, for example, in FIG. 24, when the magnetization direction of the second magnetic layer (pinned layer) 103 is rightward, it is “0”, and when it is leftward, it is “1”. Reading is performed by changing the resistance of the GMR film, that is, the first and second resistances.
When the magnetization directions of the magnetic layers 101 and 103 are parallel, the resistance is low, and when the magnetization directions are antiparallel, the resistance is high due to spin-dependent scattering. Specifically, GM
A pulse current that changes from plus to minus flows through the electrode 5 while a current of several tens mA smaller than that at the time of writing flows through the R film to change the direction of magnetization of the first magnetic layer (free layer) 101 from left to right. Flip in the direction. At this time, the second
If the data of the magnetic layer (pin layer) 103 is “1”, the resistance changes from the minimum to the maximum, and if the data is “0”, the resistance changes from the maximum to the minimum. This resistance change is output as a voltage change of the read electrode connected to the GMR film.

[0004] This magnetoresistive memory element has a simple structure, can be formed on an inexpensive substrate such as glass, can repeat writing / reading 10 ¹⁵ times or more, and is non-volatile. Have been.

However, in the magnetoresistive memory element shown in FIG. 24, there is a limit to an increase in the rate of change in resistance, and since the resistance itself of the element portion is low, it is difficult to detect a change in magnetoresistance with respect to wiring resistance. Therefore, a complicated peripheral circuit such as an amplifier circuit is required to extract a large output signal. Furthermore, since current always flows through the bit line and the word line during reading, there is a problem that power consumption is large.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to increase the degree of integration by eliminating the need for a complicated peripheral circuit by obtaining a large output signal by a structure having a high element resistance and capable of increasing the resistance change rate. An object of the present invention is to provide a magnetoresistive memory element that can reduce power consumption.

[0007]

A magnetoresistive memory element according to the present invention comprises a gate insulating film and a gate electrode formed on a semiconductor substrate, and a diffusion layer (drain) formed adjacent to a channel region below the gate electrode. ), A magnetoresistive element including a first magnetic layer, a nonmagnetic layer, and a second magnetic layer; and an electrode (source electrode) for injecting carriers into the magnetoresistive element, and a gate current flowing through the gate electrode. The direction of magnetization of the magnetic layer constituting the magnetoresistive element is controlled by the direction of the magnetoresistive element, and the magnetoresistive element is arranged such that carriers injected from the electrode flow to the semiconductor substrate through the magnetoresistive element. It is characterized by the following.

[0008]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, a silicon substrate, an insulating substrate (SOI) having a silicon layer formed thereon, or a compound semiconductor such as GaAs, AlAs, or GaN is used as a semiconductor substrate. Since the magnetoresistive memory element of the present invention basically has a structure in which a magnetoresistive element is incorporated in a MOS transistor, it can be manufactured by applying a Si-ULSI manufacturing process other than the magnetoresistive element manufacturing process. Therefore, it is not necessary to increase the number of masks so much in an actual production line such as when combining with a CMOS, and the production cost can be suppressed.

The magnetoresistive element has a structure in which a first magnetic layer, a nonmagnetic layer, and a second magnetic layer are stacked. One magnetic layer is a free layer (free layer) made of a soft magnetic material having a small coercive force.
And the direction of the magnetization changes freely according to the external magnetization. The other magnetic layer is a magnetization fixed layer (pin layer) made of a hard magnetic material having a large coercive force, and the direction of magnetization is fixed. As the material of the magnetic layer, Co, CoFe, Fe,
Ni, NiFeCo, CoPt, or the like can be used. One of the magnetic layers constituting the magnetoresistive element (for example, the first magnetic layer formed on the semiconductor substrate side) is preferably made of magnetic fine particles. In order to form such magnetic fine particles, for example, a method of controlling the vapor deposition time when depositing a magnetic material and stopping the vapor deposition before a continuous film of the magnetic material is formed can be mentioned.

The magnetoresistive element may be a so-called spin valve film (hereinafter, sometimes referred to as an SV film) in which the nonmagnetic layer is a conductor layer. As the material of the nonmagnetic conductor layer, Cu,
Ag, Au, or the like can be used. In this case, the magnetoresistance change is detected using spin-dependent scattering. The magnetoresistive element may be a so-called tunnel junction type MR film (hereinafter sometimes referred to as a JMR film) in which the nonmagnetic layer is a tunnel insulating layer. The material of the tunnel insulating layer may be SiO 2
₂ , SiN, a semiconductor having a large band gap, or the like can be used. In this case, the magnetoresistance change is detected using spin-dependent tunneling. That is, when the magnetization directions of the first and second magnetic layers are parallel, tunneling easily occurs and the resistance becomes low, and when the magnetization directions are antiparallel, tunneling hardly occurs and the resistance becomes high. . Further, a stacked layer of a tunnel insulating layer and a conductor layer may be used as the nonmagnetic layer of the magnetoresistive element. Note that an artificial lattice film having a structure in which many magnetic layers are stacked via a nonmagnetic layer may be used as the magnetoresistive element.

In the magnetoresistive element, the direction of magnetization of a magnetic layer constituting the magnetoresistive element is controlled by the direction of a gate current flowing to the gate electrode of a MOS transistor, and carriers injected from a source electrode are transferred to the semiconductor through the magnetoresistive element. Substrate (inversion layer formed by application of gate voltage)
, And further flow from the channel region to the drain electrode. For example, a magnetoresistive element and a gate electrode may be arranged adjacent to each other with an insulating layer interposed therebetween on a semiconductor substrate, and a part of the gate electrode may be formed on the magnetoresistive element via an insulating film. In this case, the gate electrode is used as a word line, and the drain electrode is used as a bit line.

In the present invention, a tunnel junction may be formed between the semiconductor substrate and the magnetoresistive element, or a Schottky junction may be formed. Further, an underlayer may be formed on a semiconductor substrate (and a tunnel insulating layer when a tunnel junction is formed), and a magnetoresistive element may be formed on the underlayer. The underlayer may be a nonmagnetic conductor layer, a laminate of a magnetic layer and a tunnel insulating layer, or a laminate of a magnetic layer, a tunnel insulating layer, and a nonmagnetic conductor layer.

The operation of the magnetoresistive memory device of the present invention is as follows. Writing is performed by causing a relatively large current to flow through the gate electrode (word line) to generate a large magnetic field and fix the magnetization direction of the pinned layer in a predetermined direction (set to "0" or "1"). . In reading, a current smaller than that in writing is applied to the gate electrode to change the direction of magnetization of the free layer so that the directions of magnetization of the pinned layer and the free layer are parallel or antiparallel. At the same time, an inversion layer extending from the semiconductor substrate (channel region) immediately below the gate electrode to the semiconductor substrate immediately below the magnetoresistive element is formed according to the potential of the gate electrode. The carriers injected from the source electrode flow through the magnetoresistive element, flow to the inversion layer formed on the surface of the semiconductor substrate via the tunnel junction or Schottky junction, and further flow to the drain (bit line). Since the magnitude of the current read by the bit line depends on whether the magnetization directions of the pinned layer and the free layer are parallel or antiparallel, the information of the pinned layer can be read as a change in magnetoresistance.

As described above, in the magnetoresistive memory device according to the present invention, the carrier injected from the source electrode is a magnetoresistance device, a tunnel junction or a Schottky junction, an inversion layer,
Since the current flows through a path called a drain electrode (bit line), the element resistance is substantially increased as compared with a conventional magnetoresistive memory element. For this reason, it becomes easy to detect the magnetic resistance with respect to the wiring resistance. As a result, peripheral circuits such as an amplifier circuit, which are required in the conventional magnetoresistive memory element, are not required.
At this time, since the ON / OFF of the current for measuring the magnetoresistance is controlled by the gate electrode, the controllability is high, and since the current flows only when the current is ON, the power consumption is lower than that of the conventional magnetoresistance memory element. It can be greatly reduced.

When one of the magnetic layers constituting the magnetoresistive element is made of magnetic fine particles, the contact area between the magnetic fine particles and the non-magnetic layer, that is, the area where carriers are scattered increases, and the direction of magnetization of the fine particles is changed. Because the current is efficiently reflected, the change in magnetoresistance can be increased.

Further, in a memory element using a tunnel junction type MR film (JMR film) having a structure in which magnetic fine particles, a tunnel insulating film (nonmagnetic layer) and a magnetic layer are laminated as a magnetoresistive element, the surface of the magnetic fine particles is When electrons tunnel through the small tunnel junction, a single electron phenomenon appears due to the effect of the capacitance of the tunnel insulating film. In the region where the single electron phenomenon is observed, the change in magnetoresistance greatly increases (several times or more) (see Japanese Patent Application No. 8-259858).
In order to realize this phenomenon at room temperature, the size of the magnetic fine particles is preferably several tens nm or less, more preferably 10 nm or less. The smaller the magnetic fine particles, the greater the single electron effect, which is advantageous for miniaturization of the memory element.

When a nonmagnetic conductor layer is provided between the tunnel insulating film of the JMR film and the magnetic layer, the interface resistance between the nonmagnetic conductor layer and the magnetic layer and between the nonmagnetic conductor layer and the tunnel insulating film is increased. In addition, it becomes easy to detect a change in the magnetoresistance with respect to the wiring resistance.

In a memory element in which a JMR film having a structure in which magnetic fine particles, a tunnel insulating film, and a magnetic layer are laminated on a tunnel insulating layer is formed, the magnetic fine particles are surrounded by the tunnel insulating film. In this case, when the size of the magnetic fine particles is several tens nm or less (preferably 10 nm or less), the capacitance of the tunnel insulating film can be reduced to 10 ^-15 F or less, and single electron can be easily formed at room temperature by Coulomb blockade. Since the effect can be realized, a large magnetoresistance change can be obtained. And the memory element of the present invention is Si-UL
Since it can be manufactured by incorporating it into the manufacturing process of the SI, a highly uniform and reliable thermal oxide film, CVD-SiO ₂ film, or CVD-SiN film can be used as the tunnel insulating film.

Incidentally, in the conventionally known JMR film, Al ₂ O ₃ or the like is used as a tunnel insulating film, and it is difficult to form a uniform film thickness. Since the current flowing through the tunnel insulating film depends exponentially on the film thickness, if the film thickness is non-uniform, the current value greatly changes. Therefore, when a magnetoresistive memory element is manufactured using a conventional JMR film, variation in current value between memory cells becomes a serious problem. On the other hand, in the magnetoresistive memory element of the present invention, a tunnel insulating film having a uniform film thickness can be formed by applying the Si-ULSI technique as described above, and the variation in current value between memory cells can be reduced. Can be suppressed.

In a memory element in which a magnetic layer and a tunnel insulating layer are formed as an underlayer on a semiconductor substrate, and a JMR film having a structure in which magnetic fine particles, a tunnel insulating film and a magnetic layer are laminated on the underlayer is provided. It has a structure in which magnetic fine particles are sandwiched between two magnetic layers via a tunnel oxide film. With such a structure, a very large magnetoresistance change can be obtained.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 shows an example of a magnetoresistive memory element according to the present invention. This magnetoresistive memory element can be manufactured as follows. First, a field oxide film 2 is formed on a p-type silicon substrate 1 to define an element region. After surface treatment of the element region, thermal oxidation is performed to form a tunnel oxide film 3 having a thickness of about 3 nm.
To form By depositing Co while controlling the deposition time, magnetic fine particles (free layer) 4 are formed on the tunnel oxide film 3.
To form A nonmagnetic conductor layer 5 having a thickness of about 5 nm is formed on the magnetic fine particles 4 by vapor deposition of Cu. A ferromagnetic layer (pin layer) 6 having a thickness of about 5 nm is formed on the nonmagnetic conductor layer 5 by depositing CoFe. These are patterned to form a spin valve film (SV film). A source electrode 7 made of Cu is joined to the side surface of the SV film. A gate oxide film 8 is formed on the surface of the silicon substrate 1 by thermal oxidation. Further, an insulating layer 9 is formed on the surfaces of the nonmagnetic layer 5 and the ferromagnetic layer 6.
After depositing polysilicon, patterning is performed to form a gate electrode 10. The n ⁺ -type drain region 11 is formed by implanting phosphorus (P) ions using the gate electrode 10 as a mask. Further, a contact hole is formed on the drain region 11, and a drain electrode (not shown) is formed.

In the above method, the drain region 11 is formed by ion-implanting impurities using the gate electrode 10 as a mask. However, the drain region 11 may be formed in advance, and the gate electrode 10 may be formed later.

As shown in FIG. 23A, a power supply 51 is connected to one end of a word line connecting the gate electrode 10 of each element, and a resistor 52 is connected to the other end. Apply voltage. As a result, each gate electrode 10
Is applied with a voltage having the same potential, and a current corresponding to the applied voltage and the resistance 52 flows. To switch the direction of the current of the gate electrode 10, a circuit as shown in FIG.
That is, a switch 53 is provided at a connection point between a wiring connected to one end of the power supply 51, a wiring connected to both ends of a word line connecting the gate electrode 10 of each element, and a wiring connected to one end of the resistor 52. , The direction of the current of the gate electrode 10 is switched.

The operation of this magnetoresistive memory element will be described. When the SV film and the gate electrode are arranged side by side as shown in the figure, the magnetic layer of the SV film is not magnetized in the horizontal direction, but only the horizontal component of the magnetization is shown in the figure. ing.

Writing to the magnetoresistive memory element is performed as follows.
This is performed by applying a relatively large current to the gate electrode (word line) 10 to generate a large magnetic field and fixing the magnetization direction of the ferromagnetic layer (pin layer) 6. At this time, the direction of the magnetization is changed depending on the direction of the current. For example, in FIG. 1, when the direction of the magnetization of the ferromagnetic layer (pin layer) 6 is rightward, it is set to "0", and when it is leftward, it is set to "1". In FIG. 1, the magnetization direction of the ferromagnetic layer (pin layer) 6 is leftward, and “1” is written.

Reading is performed as follows. By passing a current smaller than that at the time of writing to the gate electrode 10 and changing the direction of the current on the way, the direction of magnetization of the magnetic fine particles (free layer) 4 is reversed, for example, from left to right. At the same time, an inversion layer 12 extending from the silicon substrate immediately below the gate electrode 10 to the silicon substrate immediately below the SV film is formed according to the positive potential (V _G > 0) applied to the gate electrode 10. The state of the inversion layer 12 can be changed by controlling the potential of the gate electrode 10. Then, the carriers injected from the source electrode 7 flow through the SV film and pass through the tunnel oxide film 3 to the inversion layer 12.
To the drain electrode (bit line). At this time, the data of the ferromagnetic layer (pin layer) 6 is "1".
If so, the resistance changes from minimum to maximum, and if "0", the resistance changes from maximum to minimum. This resistance change is output as a voltage change in the bit line.

In this magnetoresistive memory element, electrons injected from the source electrode are applied to the SV film, tunnel junction, inversion layer,
Since the current flows along the path of the drain electrode (bit line) and the area where electrons are scattered by the magnetic fine particles 4 increases, substantial element resistance increases, and it becomes easy to detect a change in magnetoresistance relative to wiring resistance. As a result, peripheral circuits such as an amplifier circuit, which are required in the conventional magnetoresistive memory element, are not required. Further, since the ON / OFF of the current for measuring the magnetic resistance is controlled by the gate electrode, the controllability is high, and the current flows only when the current is ON.
Power consumption can be greatly reduced as compared with a conventional magnetoresistive memory element.

Although the magnetic fine particles are used as the free layer in FIG. 1, a continuous film of a magnetic material may be used. When magnetic fine particles are used as the free layer, the fine particles need not necessarily be in contact with each other, and may be separated from each other. This is because, in FIG. 1, since the change in the magnetic resistance itself is detected, a current may flow to the semiconductor substrate side through the nonmagnetic conductor layer existing between the magnetic fine particles separated from each other. Also, the source electrode 7
A tunnel insulating layer may be provided between the substrate and the SV film.

Embodiment 2 FIG. 2 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element can be manufactured as follows. First, a field oxide film 2 is formed on an n-type silicon substrate 21 to define an element region. Thereafter, magnetic fine particles (free layer) are formed on the element region in the same manner as in Example 1.
4. A nonmagnetic conductor layer 5 and a ferromagnetic layer (pinned layer) 6 are formed. In this case, a Schottky junction is formed between the silicon substrate 21 and the magnetic fine particles 4. These are patterned to form an SV film. A source electrode 7 made of Cu is joined to the side surface of the SV film. A gate oxide film 8 is formed on the surface of the silicon substrate 1 by thermal oxidation. Further, an insulating layer 9 is formed on the surfaces of the nonmagnetic layer 5 and the ferromagnetic layer 6. After depositing polysilicon, patterning is performed to form a gate electrode 10. Boron (B) using gate electrode 10 as a mask
Is implanted to form ap ⁺ -type drain region 22. Further, a contact hole is formed on the drain region 22, and a drain electrode (not shown) is formed.

This magnetoresistive memory element has a gate electrode 1
The same operation as in the first embodiment except that a negative potential (V _G <0) is applied to 0 to form an inversion layer 23 extending from the silicon substrate immediately below the gate electrode 10 to the silicon substrate immediately below the SV film. Can be. Further, since this magnetoresistive memory element has the same structure as that of the first embodiment except that a Schottky junction is formed between the silicon substrate 21 and the SV film, the same effect as that of the first embodiment is obtained. Can be

Embodiment 3 FIG. 3 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a non-magnetic conductor layer 13 made of Cu is formed as a base layer on a tunnel oxide film 3 formed on a p-type silicon substrate 1, and an SV film is formed on the non-magnetic conductor layer 13. It has the same structure as that of the first embodiment except for the above. The nonmagnetic conductor layer 13 has an action of promoting the growth of the magnetic fine particles 4 formed thereon. This magnetoresistive memory element operates in the same manner as that of the first embodiment, and a similar effect is obtained.

Embodiment 4 FIG. 4 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a ferromagnetic layer (pin layer) 14 made of CoFe and a tunnel insulating layer 15 on the surface thereof are formed as an underlayer on a tunnel oxide film 3 formed on a p-type silicon substrate 1. It has the same structure as that of the first embodiment except that an SV film is formed on the insulating layer 15. This magnetoresistive memory element operates in the same manner as that of the first embodiment. Further, the magnetization written as information can be increased by the presence of the ferromagnetic layer (pin layer) 14, and the element resistance can be increased by the presence of the tunnel insulating layer 15.

Embodiment 5 FIG. 5 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has a ferromagnetic layer (pin layer) 14 made of CoFe as a base layer on a tunnel oxide film 3 formed on a p-type silicon substrate 1, and a tunnel insulating layer 1 on the surface thereof.
5, and a nonmagnetic conductor layer 13 made of Cu is formed,
It has the same structure as that of the first embodiment except that an SV film is formed on the nonmagnetic conductor layer 13. This magnetoresistive memory element operates in the same manner as that of the first embodiment. Further, the effects described in the third and fourth embodiments can be obtained together.

Embodiment 6 FIG. 6 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element is the same as the embodiment except that a nonmagnetic conductor layer 13 made of Cu is formed as a base layer on the element region of the n-type silicon substrate 1 and an SV film is formed on the nonmagnetic conductor layer 13. It has a structure similar to the two. The nonmagnetic conductor layer 13 has an action of promoting the growth of the magnetic fine particles 4 formed thereon. This magnetoresistive memory element operates in the same manner as that of the first embodiment, and a similar effect is obtained.

Embodiment 7 FIG. 7 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a ferromagnetic layer (pin layer) 14 made of CoFe and a tunnel insulating layer 15 on the surface thereof are formed as an underlayer on a tunnel oxide film 3 formed on a p-type silicon substrate 1. It has the same structure as that of the second embodiment except that an SV film is formed on the insulating layer 15. This magnetoresistive memory element operates in the same manner as that of the first embodiment. Further, the magnetization written as information can be increased by the presence of the ferromagnetic layer (pin layer) 14, and the element resistance can be increased by the presence of the tunnel insulating layer 15.

Embodiment 8 FIG. 8 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has a ferromagnetic layer (pin layer) 14 made of CoFe as a base layer on a tunnel oxide film 3 formed on a p-type silicon substrate 1, and a tunnel insulating layer 1 on the surface thereof.
5, and a nonmagnetic conductor layer 13 made of Cu is formed,
It has the same structure as that of the first embodiment except that an SV film is formed on the nonmagnetic conductor layer 13. This magnetoresistive memory element operates in the same manner as that of the first embodiment. Further, the effects described in Embodiments 6 and 7 can be obtained together.

Embodiment 9 FIG. 9 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element can be manufactured as follows. First, a field oxide film 2 is formed on a p-type silicon substrate 1 to define an element region. After surface treatment of the element region, thermal oxidation is performed to form a tunnel oxide film 3 having a thickness of about 3 nm. The magnetic fine particles (free layer) 4 are formed on the tunnel oxide film 3 by controlling the deposition time to deposit Co. The size of the magnetic fine particles 4 is preferably 10 nm or less in order to exhibit the single electron effect. CVD-S having a thickness of 3 nm or less on the magnetic fine particles 4
A tunnel oxide film 31 made of an iO ₂ film is formed. Co
A ferromagnetic layer (pin layer) 6 having a thickness of about 5 nm is formed on the tunnel oxide film 31 by depositing Fe. These are patterned to form a tunnel junction type MR film (JMR film).
A source electrode 7 made of Cu is joined to the side surface of the ferromagnetic layer 6 of the JMR film. A gate oxide film 8 is formed on the surface of the silicon substrate 1 by thermal oxidation. Further, an insulating layer 9 is formed on the surface of the ferromagnetic layer 6. After depositing polysilicon, patterning is performed to form a gate electrode 10. Gate electrode 1
The n ⁺ -type drain region 11 is formed by ion-implanting phosphorus (P) using 0 as a mask. Further, a contact hole is formed on the drain region 11, and a drain electrode (not shown) is formed.

Example 1 of this magnetoresistive memory element except that a JMR film was used instead of an SV film as a GMR film.
It has a similar structure and operates similarly. In this magnetoresistive memory element, electrons injected from a source electrode are J
Since the current flows through the path of the MR film, the tunnel junction, the inversion layer, and the drain electrode (bit line), the element resistance substantially increases, and it becomes easy to detect a change in magnetoresistance relative to the wiring resistance.

Although the magnetic fine particles are used as the free layer in FIG. 9, a continuous film of a magnetic material may be used. When magnetic fine particles are used as the free layer, the fine particles do not necessarily need to be in contact with each other, and it is sufficient that the tunnel oxide film formed thereon is continuously formed. This is because if the tunnel oxide film is filled between the fine particles even if the fine particles are separated from each other, the current flowing through this portion sharply decreases. Further, a tunnel insulating layer may be provided between the source electrode 7 and the JMR film.

Embodiment 10 FIG. 10 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a JMR film composed of magnetic fine particles 4, a tunnel oxide film 31, a nonmagnetic conductor layer 32 and a ferromagnetic layer 6 is formed on a tunnel oxide film 3 formed on a p-type silicon substrate 1. It has the same structure as that of FIG. The thickness of the nonmagnetic conductor layer 32 is 5 nm or less,
Further, it is preferably 1 nm or less.

This magnetoresistive memory element differs from that of FIG. 9 in that a nonmagnetic conductor layer 32 is provided between the tunnel oxide film 31 and the ferromagnetic layer 6. In this case, since the interface resistance between the nonmagnetic conductor layer 32 and the tunnel oxide film 31 and the ferromagnetic layer 6 is added, the element resistance becomes larger than that of FIG.

Embodiment 11 FIG. 11 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element can be manufactured as follows. First, a field oxide film 2 is formed on an n-type silicon substrate 21 to define an element region. Hereinafter, Example 9
Magnetic fine particles (free layer) on the element region
4. A tunnel oxide film 31 and a ferromagnetic layer (pin layer) 6 are formed. In this case, a Schottky junction is formed between the silicon substrate 21 and the magnetic fine particles 4. These are patterned to form a JMR film. A source electrode 7 made of Cu is joined to the side surface of the JMR film. A gate oxide film 8 is formed on the surface of the silicon substrate 1 by thermal oxidation. Further, an insulating layer 9 is formed on the surfaces of the nonmagnetic layer 5 and the ferromagnetic layer 6. After depositing polysilicon, patterning is performed to form a gate electrode 10. Using the gate electrode 10 as a mask, boron (B) ions are implanted to form the p ⁺ -type drain region 22. Further, a contact hole is formed on the drain region 22, and a drain electrode (not shown) is formed.

This magnetoresistive memory element has a gate electrode 1
The same operation as in the ninth embodiment except that a negative potential (V _G <0) is applied to 0 to form an inversion layer 23 extending from the silicon substrate immediately below the gate electrode 10 to the silicon substrate immediately below the JMR film. Can be. This magnetoresistive memory element has the same structure as that of the ninth embodiment except that a Schottky junction is formed between the silicon substrate 21 and the JMR film. Can be

Embodiment 12 FIG. 12 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a JMR film composed of magnetic fine particles 4, a tunnel oxide film 31, a nonmagnetic conductor layer 32 and a ferromagnetic layer 6 is formed on a tunnel oxide film 3 formed on a p-type silicon substrate 1. It has the same structure as that of FIG.

This magnetoresistive memory element differs from that of FIG. 11 in that a nonmagnetic conductor layer 32 is provided between tunnel oxide film 31 and ferromagnetic layer 6. In this case, since the interface resistance between the nonmagnetic conductor layer 32 and the tunnel oxide film 31 and the ferromagnetic layer 6 is added, the element resistance becomes larger than that in FIG.

Embodiment 13 FIG. 13 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a nonmagnetic conductor layer 13 made of Cu is formed as a base layer on a tunnel oxide film 3 formed on a p-type silicon substrate 1, and a JM layer is formed on the nonmagnetic conductor layer 13.
It has the same structure as that of the ninth embodiment except that the R film is formed. The nonmagnetic conductor layer 13 has an action of promoting the growth of the magnetic fine particles 4 formed thereon. This magnetoresistive memory element operates in the same manner as that of the ninth embodiment, and the same effects can be obtained.

Embodiment 14 FIG. 14 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a ferromagnetic layer (pin layer) 14 made of CoFe and a tunnel insulating layer 15 on the surface thereof are formed as an underlayer on a tunnel oxide film 3 formed on a p-type silicon substrate 1. It has the same structure as that of the ninth embodiment except that a JMR film is formed on the insulating layer 15. This magnetoresistive memory element operates in the same manner as that of the ninth embodiment. Further, the magnetization written as information can be increased by the presence of the ferromagnetic layer (pin layer) 14, and the element resistance can be increased by the presence of the tunnel insulating layer 15.

Embodiment 15 FIG. 15 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element includes a ferromagnetic layer (pin layer) 14 of CoFe as a base layer on a tunnel oxide film 3 formed on a p-type silicon substrate 1, a tunnel insulating layer 15 on the surface thereof, and Cu. It has the same structure as that of the ninth embodiment except that a nonmagnetic conductor layer 13 is formed and a JMR film is formed on the nonmagnetic conductor layer 13. This magnetoresistive memory element operates in the same manner as that of the ninth embodiment. Further, the effects described in Embodiments 13 and 14 can be obtained together.

Embodiment 16 FIG. 16 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has the same structure as the embodiment except that a nonmagnetic conductor layer 13 made of Cu is formed as a base layer on the element region of the n-type silicon substrate 1 and a JMR film is formed on the nonmagnetic conductor layer 13. It has a structure similar to that of the eleventh embodiment. The nonmagnetic conductor layer 13 has an action of promoting the growth of the magnetic fine particles 4 formed thereon. This magnetoresistive memory element operates in the same manner as that of the eleventh embodiment, and the same effects can be obtained.

Embodiment 17 FIG. 17 shows another magnetoresistive memory element of the present invention. In this magnetoresistive memory element, a ferromagnetic layer (pin layer) 14 made of CoFe and a tunnel insulating layer 15 on the surface thereof are formed as an underlayer on a tunnel oxide film 3 formed on a p-type silicon substrate 1. It has the same structure as that of the eleventh embodiment except that a JMR film is formed on the insulating layer 15. This magnetoresistive memory element operates similarly to that of the eleventh embodiment. Further, the magnetization written as information can be increased by the presence of the ferromagnetic layer (pin layer) 14, and the element resistance can be increased by the presence of the tunnel insulating layer 15.

Embodiment 18 FIG. 18 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element includes a ferromagnetic layer (pin layer) 14 of CoFe as a base layer on a tunnel oxide film 3 formed on a p-type silicon substrate 1, a tunnel insulating layer 15 on the surface thereof, and Cu. It has the same structure as that of the eleventh embodiment except that a nonmagnetic conductor layer 13 is formed and a JMR film is formed on the nonmagnetic conductor layer 13. This magnetoresistive memory element operates similarly to that of the eleventh embodiment. Also,
The effects described in Embodiments 16 and 17 can be obtained together.

Embodiment 19 FIG. 19 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has a structure in which the element structure of the magnetoresistive memory element of Example 9 (FIG. 9) is made vertical. That is, the tunnel oxide film 3, the magnetic fine particles 4, the tunnel oxide film 31, and the ferromagnetic layer 6 are stacked on the p-type silicon substrate 1 and etched to form a mesa structure. A gate oxide film 8 is formed on the surface of the silicon substrate 1 by thermal oxidation.
Further, an insulating layer 9 is formed on the surface of the ferromagnetic layer 6. After a portion of the insulating layer 9 is etched to deposit Cu, patterning is performed to form a drain electrode 11 connected to the ferromagnetic layer 6. After depositing polysilicon, patterning is performed to form gate electrodes 10 on both sides of the mesa portion. Gate electrode 1
The n ⁺ -type source region 7 is formed by ion-implanting phosphorus (P) with 0 as a mask. A contact hole is formed on the source region 7, and a source electrode (not shown) is formed. Further, an insulating layer 41 for insulating the drain electrode 11 from the gate electrode 10 is formed. This magnetoresistive memory element operates in the same manner as that of the ninth embodiment and achieves the same effects.

Embodiment 20 FIG. 20 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has the same structure as that of the magnetoresistive memory element of Example 19, except that the back surface of the substrate 1 is used as a source electrode.

Embodiment 21 FIG. 21 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has the same structure as the magnetoresistive memory element of Example 19 except that an electrode 42 for controlling magnetization is provided on the insulating layer 41. In this memory element, instead of the current flowing through the gate electrode 10 as in the previous embodiments,
The magnetization of the magnetic layer of the magnetoresistive element is controlled by the current flowing through the electrode 42.

Embodiment 22 FIG. 22 shows another magnetoresistive memory element of the present invention. This magnetoresistive memory element has a structure similar to that of the magnetoresistive memory element of Example 20, except that an electrode 42 for controlling magnetization is provided on an insulating layer 41.

[0056]

As described in detail above, according to the present invention, a large output signal can be taken out by a structure having a high element resistance and a high resistance change rate, and a complicated peripheral circuit is not required, thereby increasing the degree of integration. It is possible to provide a magnetoresistive memory element capable of reducing power consumption. Further, the magnetoresistive memory element of the present invention is a Si-ULS
It is easy to bond with I, and a highly uniform and reliable insulating film such as SiO ₂ can be used.

[Brief description of the drawings]

FIG. 1 is a sectional view of a magnetoresistive memory element according to a first embodiment.

FIG. 2 is a sectional view of a magnetoresistive memory element according to a second embodiment.

FIG. 3 is a sectional view of a magnetoresistive memory element according to a third embodiment.

FIG. 4 is a sectional view of a magnetoresistive memory element according to a fourth embodiment.

FIG. 5 is a sectional view of a magnetoresistive memory element according to a fifth embodiment.

FIG. 6 is a sectional view of a magnetoresistive memory element according to a sixth embodiment.

FIG. 7 is a sectional view of a magnetoresistive memory element according to a seventh embodiment.

FIG. 8 is a sectional view of a magnetoresistive memory element according to an eighth embodiment.

FIG. 9 is a sectional view of a magnetoresistive memory element according to a ninth embodiment.

FIG. 10 is a sectional view of a magnetoresistive memory element according to a tenth embodiment.

FIG. 11 is a sectional view of a magnetoresistive memory element according to an eleventh embodiment.

FIG. 12 is a sectional view of a magnetoresistive memory element according to a twelfth embodiment.

FIG. 13 is a sectional view of a magnetoresistive memory element according to a thirteenth embodiment.

FIG. 14 is a sectional view of a magnetoresistive memory element according to a fourteenth embodiment.

FIG. 15 is a sectional view of a magnetoresistive memory element according to Example 15;

FIG. 16 is a sectional view of a magnetoresistive memory element according to a sixteenth embodiment.

FIG. 17 is a sectional view of a magnetoresistive memory element according to a seventeenth embodiment.

FIG. 18 is a sectional view of a magnetoresistive memory element according to an eighteenth embodiment.

FIG. 19 is a sectional view of a magnetoresistive memory element according to a nineteenth embodiment;

FIG. 20 is a sectional view of a magnetoresistive memory element according to a twentieth embodiment;

FIG. 21 is a sectional view of a magnetoresistive memory element according to Example 21.

FIG. 22 is a sectional view of a magnetoresistive memory element according to a twenty-second embodiment.

FIG. 23 is a diagram showing a circuit for supplying a gate current of the magnetoresistive memory element according to the present invention.

FIG. 24 is a sectional view of a conventional magnetoresistive memory element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... field oxide film 3 ... tunnel oxide film 4 ... magnetic fine particle (free layer) 5 ... non-magnetic conductor layer 6 ... ferromagnetic layer (pin layer) 7 ... source electrode 8 ... gate oxide film 9 ... insulating layer 10 ... gate electrode 11 ... n ⁺ drain region 12 ... inversion layer 21 ... n-type silicon substrate 22 ... p ⁺ -type drain region 23 ... inversion layer 31 ... tunnel oxide film 32 ... nonmagnetic conductor layer 41 ... insulation layer 42 ... Electrode 51 ... Power supply 52 ... Resistance 53 ... Switch

Claims (7)

[Claims] A gate insulating film and a gate electrode formed on a semiconductor substrate; a diffusion layer formed adjacent to a channel region below the gate electrode; a first magnetic layer, a non-magnetic layer, and a second A magnetoresistive element including a magnetic layer, and an electrode for injecting carriers into the magnetoresistive element, the direction of magnetization of the magnetic layer constituting the magnetoresistive element is controlled by the direction of a gate current flowing through the gate electrode, A magnetoresistive memory element, wherein the magnetoresistive element is arranged such that carriers injected from the electrode flow to the semiconductor substrate through the magnetoresistive element. 2. The method according to claim 1, wherein one of the magnetic layers constituting the magnetoresistive element is made of magnetic fine particles.
A magnetoresistive memory element according to claim 1. 3. The magnetoresistive memory element according to claim 1, wherein the nonmagnetic layer constituting the magnetoresistive element is made of a conductor. 4. The non-magnetic layer constituting the magneto-resistive element comprises a tunnel insulating layer.
A magnetoresistive memory element according to claim 1. 5. The magnetoresistive memory element according to claim 3, wherein said semiconductor substrate and said magnetoresistive element form a tunnel junction. 6. The magnetoresistive memory element according to claim 3, wherein said semiconductor substrate and said magnetoresistive element form a Schottky junction. 7. The tunnel insulating layer used as a non-magnetic layer constituting the magneto-resistive element is made of CVD-SiO ₂ or CVD-SiN.
A magnetoresistive memory element according to claim 1.