JPH11149791A - Non-volatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the fluctuation of the threshold voltage of each memory cell, and to reduce writing time in a non-volatile semiconductor storage for electrically writing data. SOLUTION: A writing circuit 6 is constituted of an Nch transistor MN whose source is connected to the drain of Y gates MY1-MY3, and its drain is connected to a power supply 11 via a resistor RL, a level shifter circuit 7 where the drain voltage VL of the Nch transistor MN is inputted and a write completion signal is outputted when the drain voltage VL reaches a preset write completion decision level, and a write operation switching circuit 8 where a write control signal and the write completion signal of the level shifter circuit 7 are inputted, the Nch transistor MN is turned on in response to the write control signal for starting write operation, and the Nch transistor MN is turned off in response to the write completion signal 7 of the level shifter circuit for ending write operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an EPROM, an EE
The present invention relates to a nonvolatile semiconductor memory device such as a PROM, a flash EEPROM, and the like, in which data can be electrically written.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for a nonvolatile semiconductor memory device for debugging a program or replacing a magnetic disk.
There is an increasing demand for PROMs, EEPROMs, and flash EEPROMs. Hereinafter, a flash EEPROM will be described as an example of a conventional nonvolatile semiconductor memory device.

FIG. 11 shows a general flash EEPROM.
FIG. 3 is a circuit diagram showing the configuration of FIG. In FIG. 11, 1 is an X decoder for selecting a row of the memory cell array, 2 is a Y decoder for selecting a column of the memory cell array, 3 is a source control circuit, 4 is a sense amplifier circuit, 5 is a write circuit, and M (i ,
j) (i = 1 to 3, j = 1 to 3) are memory cells, MYj
(J = 1 to 3) is a Y gate, WLi (i = 1 to 3) is a word line, BLj (j = 1 to 3) is a bit line, and YGi (i
= 1 to 3) are decode signal lines.

The memory cells M (i, j) are formed of transistors having a double gate structure having a floating gate, and are arranged in a matrix of three rows and three columns. The control gate of each memory cell M (i, j) is connected to a word line WLi, which is the output line of the X decoder 1, and the drain of each memory cell M (i, j) is connected to a bit line BLj. . Each memory cell M (i,
The sources of j) are commonly connected and connected to the source control circuit 3. Each bit line BLj has a Y gate MY
j, and the gate of each Y gate MYj is
The drain of each of the Y gates MYj is connected to a sense amplifier circuit 4 and a write circuit 5 while being connected to a decode signal line YGi which is an output line of the Y decoder 2.

The ROM data of the flash EEPROM is stored in each memory cell M according to "1" and "0".
The threshold voltage of (i, j) (hereinafter referred to as “Vt”)
For example, when the ROM data is "1", 0V <Vt <1
When V and ROM data are “0”, Vt> power supply voltage is set, and when “H” level (power supply voltage) is input to the word line WLi, when the ROM data is “1”, the memory cell M ( i, j) is turned on and the ROM data is "0".
In this case, the memory cell M (i, j) remains off.

[0006] Data write and erase operations of a memory cell in a flash EEPROM will be described with reference to FIG. FIG. 12 shows Vt of the memory cell, where the horizontal axis represents the gate voltage and the vertical axis represents the drain current of the memory cell. When writing data to the memory cell, for example, the source is set to the ground level, and when a voltage is applied to the control gate and the drain, an avalanche phenomenon of electrons occurs in the floating gate, and charges accumulate in the floating gate. As a result, the source and drain can be cut off (write state in FIG. 12). When erasing data, for example, when the control gate is set to the ground level, the drain is opened, and a voltage is applied to the source, the charges accumulated in the floating gate are drained to the source side, and the Vt of the memory cell decreases. Thus, the transistor can be returned to the original state (the erased state in FIG. 12).

In the circuit of FIG.
A specific operation when the operation is performed on the memory cell M (2, 2) will be described. The source of the memory cell is set to the ground level by the source control circuit 3, and the X decoder 1
Thereby, the word line WL2 connected to the gate of the memory cell M (2, 2) is set to “H” and the other word lines WL
1, WL3 is set to "L". Further, the memory cell M
The decode signal connected to the gate of the Y gate MY2 connected to the bit line BL2 by the Y decoder 2 so that only the bit line BL2 connected to the drain of (2, 2) is connected to the sense amplifier circuit 4 and the write circuit 5. Only the line YG2 is set to “H”, and the other decode signal lines YG
1, YG3 is set to "L". With these settings, only the memory cell M (2, 2) can perform the write and verify operations under the control of the sense amplifier circuit 4 and the write circuit 5.

Next, a voltage is applied to the drain of the memory cell M (2, 2) for a predetermined time by the write circuit 5 to perform writing. Thereafter, verification is performed by the sense amplifier circuit 4. If the read data is “1”, the write operation is performed again. If the read data is “0”, the write is completed, and the operation is terminated. As described above, when writing is performed, it is necessary to determine the completion of writing by repeating the operation of writing and verifying. Therefore,
The write time varies depending on the number of repetitions of the write and verify operations.

[0009]

As described above, in a conventional nonvolatile semiconductor memory device such as a flash EEPROM, when writing is performed, the writing and verifying operations are repeated to determine the completion of the writing. Since the operation is repeated, the writing time is prolonged. Further, in order to reduce the number of repetitions of the write and verify operations, the time required for one write may be increased, but in that case, Vt control after the write becomes difficult, and Vt control becomes difficult.
There is a possibility that the variation will increase or a reliability defect due to excessive writing will occur.

It is an object of the present invention to provide a non-volatile semiconductor memory device capable of suppressing variation in threshold voltage (Vt) of each memory cell and shortening a writing time.

[0011]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a nonvolatile memory cell having a drain connected to a bit line; , A memory cell array arranged for a desired capacity, an X decoder for selecting a row of the memory cell array, a Y decoder for selecting a column of the memory cell array, and an output signal of the Y decoder having a source connected to a bit line. What is claimed is: 1. A nonvolatile semiconductor memory device comprising: a column select transistor that is controlled to be turned on and off; and a write circuit that writes data to a nonvolatile memory cell, wherein the write circuit has a source connected to a drain of the column select transistor, Inputs an N-channel transistor connected to a power supply via a resistor, and a drain voltage of the N-channel transistor; A level shifter circuit that outputs a write end signal when the drain voltage of the semiconductor memory reaches a preset write end determination level, a write control signal and a write end signal of the level shifter circuit, and responds to the write control signal. And a write operation switching circuit for turning on the transistor to start the write operation, and turning off the N-channel transistor in response to the write end signal of the level shifter circuit to end the write operation.

With this configuration, the Vt of each memory cell after writing can be made uniform without variation, regardless of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced. 3. A nonvolatile semiconductor memory device according to claim 2, wherein said nonvolatile memory cell comprising a transistor having a drain connected to a bit line and capable of electrically writing data is arranged in a row and column direction by a desired capacity. A cell array, an X decoder for selecting a row of the memory cell array, a Y decoder for selecting a column of the memory cell array, a column selection transistor having a source connected to a bit line and controlled on / off by an output signal of the Y decoder; A write circuit for writing data to the nonvolatile memory cell, wherein the write circuit has a source connected to the drain of the column selection transistor, and a drain connected to the power supply via a resistor. N-channel transistor and the drain voltage of the N-channel transistor are input, and this drain voltage is set in advance. A level shifter circuit that outputs a write end signal when the write end determination level is reached, a write control signal, a write end signal of the level shifter circuit, and a drain signal of a column selection transistor are input, and an N channel is provided in response to the write control signal. A transistor is turned on to start a write operation, and in response to a write end signal of the level shifter circuit, an inverted signal of a drain signal of a column selection transistor is supplied to a gate of the N-channel transistor to reduce a current of the N-channel transistor. And a write operation switching circuit for ending the write operation.

With this configuration, the Vt of each memory cell after writing can be made uniform without variation, regardless of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced. According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the second aspect, at the time of a read operation, the write operation switching circuit supplies an inverted signal of the drain signal of the column select transistor to the gate of the N-channel transistor. By outputting the output signal of the level shifter circuit as read data, the write circuit is used as a sense amplifier circuit.

Thus, it is not necessary to separately provide a sense amplifier circuit, and the size can be reduced. 5. The non-volatile semiconductor memory device according to claim 4, wherein electrically-writable non-volatile memory cells each including a transistor having a drain connected to a bit line and having a desired capacity arranged in a row and column direction. A cell array, an X decoder for selecting a row of the memory cell array, a Y decoder for selecting a column of the memory cell array, a column selection transistor having a source connected to a bit line and controlled on / off by an output signal of the Y decoder; A write circuit for writing data to a non-volatile memory cell, wherein the write circuit has a drain connected to a drain of a column selection transistor, and a source connected to a power supply via a resistor. Input the P-channel transistor and the source voltage of the P-channel transistor, and the source voltage A level shifter circuit that outputs a write end signal when the write end determination level is reached, a write control signal and a write end signal of the level shifter circuit are input, and a P-channel transistor is turned on in response to the write control signal to perform a write operation. And a write operation switching circuit for turning off the P-channel transistor in response to the write end signal of the level shifter circuit to end the write operation.

With this configuration, the Vt of each memory cell after writing can be made uniform without variation, regardless of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In the embodiment of the present invention, a flash EEPROM will be described as an example, as in the conventional example. However, the present invention can be applied to a nonvolatile semiconductor memory device such as an EPROM and an EEPROM, which can electrically write data.

FIG. 1 shows a first embodiment of the present invention.
1 is a configuration diagram of a nonvolatile semiconductor memory device according to an embodiment. In FIG. 1, 6 is a write circuit, 7 is a level shifter circuit, 8 is a write operation switching circuit, 11 is a power supply, RL
Is a resistor, MN is an Nch (N-channel) transistor, and other portions that are the same as those in FIG. FIG. 2 is a circuit configuration diagram of the level shifter circuit 7 according to the embodiment, and FIG. 3 is a circuit configuration diagram of the write operation switching circuit 8.

In the present embodiment, the write circuit 6 connected to the drain of each Y gate (column selection transistor) MYj (j = 1 to 3) together with the sense amplifier circuit 4 is shown in FIG.
Unlike the first write circuit 5, the other configuration is the same as that of FIG. The write circuit 6 of FIG.
RL, a resistor RL, a level shifter circuit 7, and a write operation switching circuit 8. The drains of the Y gates MYj are connected in common and connected to the source of the Nch transistor MN. The drain of the Nch transistor MN is connected to the power supply 11 via the resistor RL.

The level shifter circuit 7 includes a resistor RL and an Nch
The voltage at the connection point with the transistor MN, in other words, Nc
The voltage VL of the drain of the h transistor MN (hereinafter referred to as “write detection level VL”) is input. This level shifter circuit 7 is, for example, as shown in FIG.
This is an inverter circuit composed of a transistor 21 and an Nch transistor 22. In an ordinary inverter circuit, the input voltage inverts the output at half the power supply voltage.
This is a circuit in which the output is inverted at a desired value by adjusting the size of the Pch transistor 21 and the Nch transistor 22.

The write operation switching circuit 8 receives the output signal LO of the level shifter circuit 7 and a write control signal,
The output signal CO is input to the gate of the Nch transistor MN. The write operation switching circuit 8 is realized by, for example, a circuit as shown in FIG. 3. When the write control signal is at the “H” level, the output signal CO is set to the “L” level, and when the write control signal is at the “L” level, This circuit outputs the same level as the output signal LO of the input level shifter circuit 7 as the output signal CO. In FIG. 3,
31 and 32 are latch circuits composed of D flip-flops,
33 is a NOR circuit, 34 and 35 are Nch transistors,
36 and 37 are inverter circuits.

An operation at the time of writing of the nonvolatile semiconductor memory device of the present embodiment configured as described above will be described. For example, a memory cell M (2,
2). First, the source of the memory cell is set to the ground level by the source control circuit 3, and the X decoder 1
Thereby, the word line WL2 connected to the gate of the memory cell M (2, 2) is set to “H” and the other word lines WL
1, WL3 is set to "L". Further, the memory cell M
The decode signal connected to the gate of the Y gate MY2 connected to the bit line BL2 by the Y decoder 2 so that only the bit line BL2 connected to the drain of (2, 2) is connected to the sense amplifier circuit 4 and the write circuit 6. Only the line YG2 is set to “H”, and the other decode signal lines YG
1, YG3 is set to "L". With these settings, only the memory cell M (2, 2) can perform the write and verify operations under the control of the sense amplifier circuit 4 and the write circuit 6.

Next, writing is performed by the writing circuit 6. FIG. 4 shows a timing chart at this time. When writing is performed, the write control signal input to the write circuit 6 is set to “L”. As a result, the output signal CO of the write operation switching circuit 8 becomes “H”, and the Nch transistor MN is turned on. At this time, the level of the power supply 11 and the value of the resistor RL are adjusted so that a voltage of a level necessary for writing is applied to the drain of the memory cell M (2, 2). With the above settings, writing is performed on the memory cell M (2, 2). And Nc
When the h-transistor MN is turned on, the write detection level VL at the beginning of writing becomes lower than the write end determination level VLs of the level shifter circuit 7, and the output signal LO of the level shifter circuit 7 becomes "H". Note that the write end determination level VLs of the level shifter circuit 7 is determined when the writing of the memory cell is completed, that is, when the memory cell
write detection level VL at the time when data is written up to t
Set as the scheduled level for.

Then, as writing proceeds, Vt of the memory cell M (2, 2) increases, and the resistance component increases. Therefore, the write detection level VL is higher than at the beginning of the write. As the writing proceeds, the write detection level V
L is the write end determination level VLs of the level shifter circuit 7
, The output signal LO of the level shifter circuit 7 changes from “H” to “L”. The "L" output signal LO at this time is a write end signal. The write operation switching circuit 8 receives the write end signal, that is, when the input signal LO from the level shifter circuit 7 becomes “L”,
The output signal CO becomes "L" level. That is, as writing to the memory cell M (2, 2) proceeds, the write detection level VL increases. When the data is written to the predetermined Vt, the output signal LO of the level shifter circuit 7 is inverted, and the output signal CO of the write operation switching circuit 8 becomes "L" level. When the output signal CO goes to "L" level, the Nch transistor MN is turned off, and writing is not performed, and the writing operation is completed.

As described above, according to the first embodiment,
By configuring the writing circuit 6 as described above, the Vt after writing can be made uniform without variation regardless of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced. [Second Embodiment] FIG. 5 is a configuration diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. In FIG. 5, reference numeral 9 denotes a write circuit serving also as a sense amplifier, and reference numeral 10 denotes a write operation switching circuit. In addition, the same parts as those in FIG. FIG. 6 is a circuit diagram of the write operation switching circuit 10 according to the embodiment.

In the present embodiment, instead of the sense amplifier circuit 4 and the write circuit 6 in FIG. 1, a sense amplifier / write circuit 9 is provided for each Y gate (column select transistor) MYj.
(J = 1 to 3) are connected to the drains, and the other configuration is the same as that of FIG. 5 includes an Nch transistor MN, a resistor RL, a level shifter circuit 7, and a write operation switching circuit 10. The drains of the Y gates MYj are connected in common and connected to the source of the Nch transistor MN. The drain of the Nch transistor MN is connected to the power supply 11 via the resistor RL.

The level shifter circuit 7 includes a resistor RL and an Nch
The voltage at the connection point with the transistor MN, in other words, Nc
The configuration is the same as that of FIG. 2 with the input of the voltage VL of the drain of the h transistor MN (hereinafter referred to as “write detection level VL”). The write operation switching circuit 10 inputs the output signal LO of the level shifter circuit 7, the write control signal, and the drain voltage of the Y gate MYj (j = 1 to 3), and the output signal CO is input to the gate of the Nch transistor MN. Is done. The write operation switching circuit 10 is realized by, for example, a circuit as shown in FIG. 6, and when a write control signal is at "H" level, a Y gate M
This circuit outputs an inverted signal of the input signal from the drain of Yj, and outputs the same level as the output signal LO of the input level shifter circuit 7 as the output signal CO when the write control signal is at the “L” level. In FIG. 6, 39,
40 is an inverter circuit, 41, 44 and 45 are Pch transistors, 42, 43 and 46 are Nch transistors, and other parts corresponding to those in FIG.
Description is omitted.

The operation of the nonvolatile semiconductor memory device according to the present embodiment configured as described above will be described. First,
The operation at the time of writing will be described. The cell on which the writing is performed is, for example, a memory cell M (2, 2). First, the source of the memory cell is set to the ground level by the source control circuit 3, and the memory cell M is set by the X decoder 1.
The word line WL2 connected to the gate of (2, 2) is set to “H”.
And the other word lines WL1 and WL3 are set to “L”. Further, the Y decoder 2 is connected to the gate of the Y gate MY2 connected to the bit line BL2 so that only the bit line BL2 connected to the drain of the memory cell M (2, 2) is connected to the sense amplifier / write circuit 9. Only the decoded signal line YG2 is set to “H”, and the other decoded signal lines YG1 and YG3 are set to “L”. With these settings, only the memory cell M (2, 2) can perform the write and verify operations under the control of the write circuit 9 also serving as the sense amplifier.

Next, writing is performed by the sense amplifier / write circuit 9. FIG. 7 shows a timing chart at this time. When writing is performed, the write control signal input to the sense amplifier / write circuit 9 is set to “L”.
To As a result, the output signal CO of the write operation switching circuit 10 becomes "H", and the Nch transistor MN is turned on. At this time, the level of the power supply 11 and the value of the resistor RL are adjusted so that a voltage of a level necessary for writing is applied to the drain of the memory cell M (2, 2). With the above settings, writing is performed on the memory cell M (2, 2). Then, the Nch transistor MN is turned on.
As a result, the write detection level VL at the beginning of writing becomes lower than the write end determination level VLs of the level shifter circuit 7, and the output signal LO of the level shifter circuit 7 becomes "H".
become. Note that the write end determination level VLs of the level shifter circuit 7 is set as a scheduled level of the write detection level VL at the time when the writing of the memory cell is completed, that is, at the time when the memory cell is written to the scheduled Vt.

Then, as writing proceeds, Vt of the memory cell M (2, 2) increases, and the resistance component increases. Therefore, the write detection level VL is higher than at the beginning of the write. As the writing proceeds, the write detection level V
L is the write end determination level VLs of the level shifter circuit 7
, The output signal LO of the level shifter circuit 7 changes from “H” to “L”. The "L" output signal LO at this time is a write end signal. The write operation switching circuit 10 receives the write end signal, that is, when the input signal LO from the level shifter circuit 7 becomes “L”, the output signal CO becomes an inverted signal of the input signal from the drain of the Y gate MYj. . That is, the memory cell M
As writing to (2, 2) proceeds, the write detection level VL increases. When the data is written to the predetermined Vt, the output signal LO of the level shifter circuit 7 is inverted, and the output signal CO of the write operation switching circuit 10 becomes an inverted signal of the input signal from the drain of the Y gate MYj, and the level becomes low.
When the level of the output signal CO decreases, the Nch transistor MN controls the current, the drain voltage of the memory cell (2, 2) decreases, and writing is not performed, and the writing operation is completed.

Next, the operation at the time of reading will be described. In the read operation, by setting the write control signal to “H”, the write operation switching circuit 10 inverts the input signal from the drain of the Y gate MYj (j = 1 to 3) and outputs the inverted signal to the gate of the Nch transistor MN. The read / write circuit 9 operates as a sense amplifier circuit by outputting the output signal LO of the level shifter circuit 7 as read data to the outside. As described above, when used as a sense amplifier circuit, it is necessary to control the drain voltage of the memory cell usually in the vicinity of 0 to 1V. Also during the read operation, the source control circuit 3 sets the source of the memory cell to the ground level. The gate level of the memory cell is set higher during writing than during reading.

As described above, according to the second embodiment,
By configuring the sense amplifier / write circuit 9 as described above, the Vt after writing can be made uniform without variation irrespective of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced. Further, since the sense amplifier / write circuit 9 is used for the read operation, a separate sense amplifier circuit is not required, and the size can be reduced. Note that a separate sense amplifier circuit can be provided, and the sense amplifier / write circuit 9 can be used exclusively for the write circuit.

[Third Embodiment] FIG. 8 shows a third embodiment of the present invention.
1 is a configuration diagram of a nonvolatile semiconductor memory device according to an embodiment. 8, reference numeral 6 'denotes a write circuit, reference numeral 12 denotes a write operation switching circuit, reference numeral MP denotes a Pch (P-channel) transistor, and other parts that are the same as those in FIG. FIG. 9 is a circuit diagram of a write operation switching circuit 12 according to the same embodiment.

In this embodiment, a write circuit 6 'connected to the drain of each Y gate (column select transistor) MYj (j = 1 to 3) together with the sense amplifier circuit 4 is different from the write circuit 6 in FIG. The other configuration is the same as that of FIG. That is, in the present embodiment, the Pch transistor MP is used instead of the Nch transistor MN of FIG. 1, and the write operation switching circuit 8 (see FIG. 3) of FIG. Circuit 12 is used. The drains of the Y gates MYj are connected in common and connected to the drain of the Pch transistor MP. The source of the Pch transistor MP is connected to the power supply 11 via the resistor RL.

The level shifter circuit 7 includes a resistor RL and a Pch
The voltage at the connection point with the transistor MP, in other words, Pc
The source voltage VL of the h transistor MP (hereinafter referred to as “write detection level VL”) is input. This level shifter circuit 7 is shown, for example, in FIG. The write operation switching circuit 12 receives the output signal LO of the level shifter circuit 7 and the write control signal, and outputs the output signal CO
Is input to the gate of the Pch transistor MP. The write operation switching circuit 12 is realized, for example, by a circuit as shown in FIG. 9. When the write control signal is at "H" level, the output signal CO is set to "H" level, and when the write control signal is at "L" level, This circuit outputs an inverted signal of the output signal LO of the input level shifter circuit 7 as the output signal CO. In FIG. 9, reference numeral 38 denotes an inverter circuit, and other portions corresponding to those in FIG. 3 are denoted by the same reference numerals and description thereof is omitted.

The write operation of the nonvolatile semiconductor memory device according to the present embodiment configured as described above will be described. For example, a memory cell M (2,
2). First, the source of the memory cell is set to the ground level by the source control circuit 3, and the X decoder 1
Thereby, the word line WL2 connected to the gate of the memory cell M (2, 2) is set to “H” and the other word lines WL
1, WL3 is set to "L". Further, the memory cell M
The decoder connected to the gate of the Y gate MY2 connected to the bit line BL2 by the Y decoder 2 so that only the bit line BL2 connected to the drain of (2, 2) is connected to the sense amplifier circuit 4 and the write circuit 6 '. Only the signal line YG2 is set to “H”, and the other decode signal lines Y
G1 and YG3 are set to “L”. With these settings, only the memory cell M (2, 2) can perform the write and verify operations under the control of the sense amplifier circuit 4 and the write circuit 6 '.

Next, writing is performed by the writing circuit 6 '. FIG. 10 shows a timing chart at this time. When writing is performed, the write control signal input to the write circuit 6 'is set to "L". As a result, the output signal CO of the write operation switching circuit 12 becomes "L", and the Pch transistor MP is turned on. At this time, the level of the power supply 11 and the value of the resistor RL are adjusted so that a voltage of a level necessary for writing is applied to the drain of the memory cell M (2, 2). With the above settings, writing is performed on the memory cell M (2, 2). Then, when the Pch transistor MP is turned on, the write detection level VL at the beginning of writing is changed to the level shifter circuit 7.
, The output signal LO of the level shifter circuit 7 becomes “H”.

Then, as writing proceeds, Vt of the memory cell M (2, 2) increases, and the resistance component increases. Therefore, the write detection level VL is higher than at the beginning of the write. As the writing proceeds, the write detection level V
L is the write end determination level VLs of the level shifter circuit 7
, The output signal LO of the level shifter circuit 7 changes from “H” to “L”. At this time, the output signal LO of “L” is a write end signal, and the write operation switching circuit 12 receives the write end signal, that is, when the input signal LO from the level shifter circuit 7 becomes “L”, the output signal CO Becomes "H" level. That is, the memory cell M
As writing to (2, 2) proceeds, the write detection level VL increases. When the data is written to the predetermined Vt, the output signal LO of the level shifter circuit 7 is inverted, and the output signal CO of the write operation switching circuit 12 becomes “H” level. When the output signal CO goes to "H" level, the Pch transistor MP is turned off, writing is not performed, and the writing operation is completed.

As described above, according to the third embodiment,
By configuring the writing circuit 6 'as described above, the Vt after writing can be made uniform without variation irrespective of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced. Note that the first and second
In the third and third embodiments, the memory cell array is 3
The row and the column are described as three, but it is needless to say that the present invention is not limited to this.

[0039]

As described above, according to the present invention, the write circuit
N-channel (or P-channel) connected between the drain of the column selection transistor and the power supply via a resistor on the power supply side
A transistor; a level shifter circuit for outputting a write end signal when a drain voltage of the N-channel transistor (or a source voltage of the P-channel transistor) reaches a preset write end determination level; A write operation switching circuit for turning on the (or P-channel) transistor to start the write operation and controlling the N-channel (or P-channel) transistor to end the write operation in response to a write end signal of the level shifter circuit. By doing so, the Vt of each memory cell after writing can be made uniform without variation, regardless of the writing characteristics of each memory cell. Further, since the verify operation does not need to be performed separately from the write operation, the write time can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a level shifter circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a write operation switching circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a write operation switching circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a write operation switching circuit according to a third embodiment of the present invention.

FIG. 10 is a timing chart according to the third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

FIG. 12 is a diagram showing a state of a memory cell in a writing and erasing state of a flash EEPROM which is a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 X decoder 2 Y decoder 3 Source control circuit 4 Sense amplifier circuit 5 Write circuit 6 Write circuit 6 'Write circuit 7 Level shifter circuit 8 Write operation switching circuit 9 Sense amplifier combined write circuit 10 Write operation switch circuit 11 Power supply 12 Write operation switch circuit RL resistance MN N-channel transistor MY1-MY3 Y gate (column selection transistor) BL1-BL3 Bit line MP P-channel transistor

Claims (4)

[Claims] 1. A memory cell array in which electrically-writable nonvolatile memory cells each including a transistor having a drain connected to a bit line and having a desired capacity arranged in a row and column direction, and the memory cell An X decoder for selecting a row of the array, a Y decoder for selecting a column of the memory cell array, a column selection transistor having a source connected to the bit line and being on / off controlled by an output signal of the Y decoder; A write circuit for writing data to a memory cell, wherein the write circuit has a source connected to a drain of the column selection transistor, and a drain connected to a power supply via a resistor. An N-channel transistor, and a drain voltage of the N-channel transistor,
A level shifter circuit that outputs a write end signal when the drain voltage reaches a preset write end determination level; a write control signal and a write end signal of the level shifter circuit; and a response to the write control signal Turning on the N-channel transistor to start a write operation;
A non-volatile semiconductor memory device comprising: a write operation switching circuit for turning off the N-channel transistor in response to a write end signal of the level shifter circuit to end the write operation. 2. A memory cell array in which electrically-writable nonvolatile memory cells each including a transistor having a drain connected to a bit line and having a desired capacity arranged in a row and column direction, and the memory cell An X decoder for selecting a row of the array, a Y decoder for selecting a column of the memory cell array, a column selection transistor having a source connected to the bit line and being on / off controlled by an output signal of the Y decoder; A write circuit for writing data to a memory cell, wherein the write circuit has a source connected to a drain of the column selection transistor, and a drain connected to a power supply via a resistor. An N-channel transistor, and a drain voltage of the N-channel transistor,
A level shifter circuit that outputs a write end signal when the drain voltage reaches a preset write end determination level; a write control signal, a write end signal of the level shifter circuit, and a drain signal of the column selection transistor; In response to the write control signal, the N-channel transistor is turned on to start a write operation, and in response to a write end signal of the level shifter circuit, an inverted signal of a drain signal of the column selection transistor is applied to the gate of the N-channel transistor. And a write operation switching circuit for terminating the write operation by reducing the current of the N-channel transistor by supplying the current. 3. A write operation switching circuit supplies an inverted signal of a drain signal of a column selection transistor to a gate of an N-channel transistor during a read operation, and outputs an output signal of a level shifter circuit as read data, thereby enabling a write circuit to operate. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said nonvolatile semiconductor memory device is used as a sense amplifier circuit. 4. A memory cell array in which electrically-writable non-volatile memory cells each including a transistor having a drain connected to a bit line and having a desired capacity arranged in a row and column direction, and the memory cell An X decoder for selecting a row of the array, a Y decoder for selecting a column of the memory cell array, a column selection transistor having a source connected to the bit line and being on / off controlled by an output signal of the Y decoder; A write circuit for writing data to a memory cell, wherein the write circuit has a drain connected to a drain of the column select transistor, and a source connected to a power supply via a resistor. And a source voltage of the P-channel transistor, and the source voltage is set in advance. A level shifter circuit that outputs a write end signal when the write end determination level is reached, a write control signal and a write end signal of the level shifter circuit, and turns on the P-channel transistor in response to the write control signal. To start the write operation,
And a write operation switching circuit for turning off the P-channel transistor in response to a write end signal of the level shifter circuit to end the write operation.