JPH11149671A - Exposing device for optical master disk - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an exposing device for an optical master disk which can perform exposure in a MCAV format, a CAV format, or the like with a simple means and at high speed. SOLUTION: A spindle motor drive pulse generator 22 outputs a pulse signal Tf for spindle motor drive command to a spindle motor driver 3, also generates a track pulse signal TP/deciding a reference position of a track of an optical disk, and outputs it to a pulse generator 24 for formatter. Programmable oscillators 25, 26 generate each pulse signals f1 , f2 , and output them to the pulse generator 24 for formatter. The pulse generator 24 for formatter generates clock pulse signals Fclk for formatter of the prescribed numbers for each track of the optical disk synchronizing with the track pulse signal TP/based on the pulse signals f1 , f2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an exposure apparatus for an optical disk master suitable for exposing a photoresist master of an optical disk, particularly a medium of MCAV format.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open Nos. 4-146540 and 6-188726 disclose a conventional exposure apparatus for a master optical disc. FIG. 10 illustrates this conventional optical disk master exposure apparatus. As shown in FIG. 1, a conventional apparatus includes a spindle motor drive pulse generator 101 that generates a pulse signal Tf for driving a spindle motor that rotates a turntable (not shown) that rotates on a photoresist master of an optical disk.
And a pulse signal S for driving a traverse motor for moving the turntable in the direction of the surface of the photoresist master.
traverse motor drive pulse generator 10 for generating f
2, a formatter pulse generator 103 for generating a cutting clock Fclk to be supplied to a formatter (not shown) for encoding a signal of information to be written on the photoresist master, a spindle motor drive pulse generator 101, a transverse motor drive pulse generator And a crystal oscillator 104 for supplying a single basic clock f0 to the pulse generator 102 and the formatter pulse generator 103.

[0003] Each of the pulse generators 101, 1
In 02 and 103, delay pulses of the basic clock f0 are arranged at equal time positions within one cycle of the basic clock f0 with reference to one rotation of the turntable, and the output from these pulse trains is adjusted to the frequency designated. It is trying to select and output pulses and obtain a low jitter pulse train with high resolution frequency setting.

[0004]

Recently, DVD-ROMs, DVD-Rs, and DVs have been used as large-capacity optical disk media.
Attention has been paid to D-RAMs and the like. In the DVD standard, track pitch: 0.74 μm, minimum pit length:
It is 0.4 μm, and a preformat having a microstructure of about half of that of the track pitch of 1.6 μm and the minimum pit length of 0.87 μm in the case of the current CD standard must be formed on the master optical disc. Therefore, there is a need for a technique for exposing the photoresist master of an optical disc with higher accuracy. Also, since the pitch is about half that of the current CD standard, the exposure time is increased at the same exposure speed as the conventional one, which leads to an increase in trouble due to the attachment of dust. There is also a need for a technique for exposing the photoresist master.

As a DVD-RAM disk format, an MCAV format is being studied (Nikkei Electronics No. 95.11.6, 163).
Pp. 170). In this method, the optical disc is divided into zones in the radial direction, and the cutting clock is increased as the zone is closer to the outer periphery. The synchronization of the command pulse to the spindle motor that drives the turntable that rotates the photoresist master disc is synchronized. There is a need for a technique for improving the accuracy and jitter specifications.

[0006] Assuming exposure at the current double speed and triple speed, the cutting clock frequency is 100 MHz.
It is necessary to achieve about z and a jitter of 0.8 nsec or less.

However, the upper limit of the cutting clock frequency and the jitter specification that can be realized by using the above-mentioned prior art disclosed in Japanese Patent Application Laid-Open Nos. 4-146540 and 6-188726 are such that the basic clock is 40 MHz.
When 5 stages of delay of 5 nsec ± 2 nsec are used, the output frequency is several MHz and the maximum jitter is about 12 nsec. In order to achieve the above cutting clock frequency and jitter specifications, the basic clock is 1 GHz.
As described above, the delay element is 0.4 nsec ± 0.1 ns.
ec or less is required, and it is extremely difficult to specifically configure a circuit including peripheral circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide an exposure apparatus for an optical disk master capable of performing exposure in an MCAV format or a CAV format by a simple means at a higher speed than conventionally.

Another object of the present invention is to correct a change in frequency due to a temperature drift, a change with time, or the like, so that an actual pulse signal can be brought closer to the arrangement of a clock pulse signal for a true formatter. .

[0010]

According to the first aspect of the present invention, there is provided a turntable for rotating a photoresist master of an optical disk placed thereon, a spindle motor for rotating the turntable, and connecting the turntable to the photoresist. A transverse feed motor moving in the direction of the master surface, a light source for emitting a laser beam for exposing the photoresist master, a formatter for encoding a signal of information to be written on the photoresist master, and the laser beam according to the encoded signal. ON and OFF to generate an optical modulator that converts the laser light into an optical signal whose pulse width is adjusted, a pulse signal for commanding the drive of the spindle motor, and a reference position of a track on the optical disk. Motor pulse generator that generates a track pulse signal that determines the A horizontal feed motor drive pulse generator for generating a pulse signal for a drive command of the horizontal feed motor; a programmable oscillator; and an output pulse of the programmable oscillator as the formatter clock pulse signal for the track pulse signal. A formatter pulse generator that outputs a predetermined number in synchronization.

Therefore, the high-precision oscillator output of the programmable oscillator can be used as a formatter clock pulse signal in synchronization with the track pulse signal.

According to a second aspect of the present invention, in the first aspect of the invention, after outputting a predetermined number of formatter clock pulse signals for one track of the optical disk, the next track pulse signal is changed to a spindle motor drive pulse. It has a counter that counts the time until it is output from the generator.

Accordingly, it is possible to monitor an error with respect to the arrangement of the clock pulse signal for the true formatter within one track of the optical disk.

According to a third aspect of the present invention, in the first or second aspect, the formatter pulse generator generates one or a plurality of types of pulse signals having a phase difference between the output pulse signals of the programmable oscillator. A phase difference pulse generation circuit, a latch circuit for latching the rise of the track pulse signal to the H level or the fall to the L level, and first after the latch circuit latches the rise or the fall of the track pulse signal, A determination circuit for determining which of the rising edge to the H level or the falling edge to the L level is at least one of the out-of-phase pulse signal of the output pulse signal of the programmable oscillator and the out-of-phase pulse signal; , It is determined that the signal has first risen to the H level. It comprises a signal selection circuit supplied to the formatter selects a pulse signal.

Accordingly, in addition to the output pulse signal of the programmable oscillator, a pulse signal having a phase difference is generated, and of these plural pulse signals, the track pulse signal rises to H level or falls to L level. Thereafter, a pulse signal determined to have risen to the H level or fall to the L level first can be selected as a clock pulse signal for the formatter.

According to a fourth aspect of the present invention, in the third aspect, the phase difference pulse generation circuit includes an inverter for generating an inverted pulse signal of an output pulse of the programmable oscillator.

Therefore, an inverted pulse signal can be generated as a pulse signal having a phase difference between the output pulse signals of the programmable oscillator.

According to a fifth aspect of the present invention, in the third or fourth aspect, the phase difference pulse generating circuit includes a delay circuit for generating a pulse with a phase delay from an output pulse of the programmable oscillator.

Therefore, a pulse signal which is a phase difference between the output pulse signals of the programmable oscillator can be generated with various magnitudes of phase delay.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, the delay circuit can set a phase delay time in a programmable manner.

Therefore, it is possible to generate a pulse signal, which is a phase difference between the output pulse signals of the programmable oscillator, with accurate time intervals.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment of the Invention] FIG.
1 is a block diagram of the overall configuration of an optical disc master disc exposure apparatus 1 according to a first embodiment of the present invention. As shown in FIG. 1, the exposure apparatus 1 includes a turntable 2 on which a photoresist master D of an optical disc is placed. The turntable 2 is rotationally driven by a spindle motor 4 driven by a spindle motor driver 3. In addition, the turntable 2 is moved in the horizontal direction (the direction of the surface of the photoresist master D) by the transverse motor 6 driven by the transverse motor driver 5.

The Ar laser generator 11 (light source) is a light source for exposing the photoresist master D.
The mirror 13 reflects the Ar laser 12 emitted from the laser generator 11, and the optical modulator 14 driven by the optical modulator driver 17 is turned on and off to convert it into an optical signal of information to be written on the photoresist master D. . Then, the objective lens 15 focuses the Ar laser 12 on the photoresist master D into an extremely small light spot to form an exposure beam. The formatter 16 is a programmable generator of data to be written on the photoresist master D, and continuously encodes the data and outputs the data to the optical modulator driver 17.

The crystal oscillator 21 supplies a basic clock f0 to a spindle motor drive pulse generator 22 and a transverse motor drive pulse generator 23. The spindle motor drive pulse generator 22 outputs a pulse signal Tf for a drive command of the spindle motor 4 to the spindle motor driver 3, and for each rotation of the turntable 2, a reference position in the circumferential direction of the optical disc (track reference). Track pulse signal T for generating position
P / is output to the formatter pulse generator 24. The traversing motor drive pulse generator 23 outputs to the traversing motor driver 5 a pulse signal Sf for drive command of the traversing motor 6 completely synchronized with the pulse signal Tf.
Means for synchronizing the pulse signal Tf and the pulse signal Sf are disclosed in Japanese Patent Application Laid-Open Nos. 4-146540 and 6-188726, and therefore, detailed description is omitted.

The programmable oscillators 25 and 26 have 10
Output frequency of 0MHz or more, jitter specification 0.8nsec
The following can be achieved: The time required for setting the output frequency (e.g., the PLL settling time) is not problematic even if it is several milliseconds. For example, a direct digital synthesizer PCK-80 manufactured by DS Technology Co., Ltd.
Etc. can be used. Programmable oscillator 25
Outputs a pulse signal f1, and the programmable oscillator 26 outputs a pulse signal f2 to the pulse generator 24 for formatter. The formatter pulse generator 24 generates a formatter clock pulse signal Fclk from the pulse signal f1 or the pulse signal f2 in synchronization with the track pulse signal TP /, and
Output to This formatter clock pulse signal F
clk is synchronized with the pulse signals Tf and Sf.

The setting of various control data to the spindle motor drive pulse generator 22, the lateral feed motor drive pulse generator 23, the formatter pulse generator 24, and the setting of the oscillation frequency to the programmable oscillators 25 and 26 are performed by the MPU 27.

With the circuit configuration described above with reference to FIG.
Generation of a clock pulse Fclk for the formatter 16 necessary for exposure of the photoresist master D in the MCAV format in synchronization with the rotation of the turntable 2 and instantaneous switching of the formatter clock pulse frequency in accordance with the zone switching of the optical disk. It is possible.

FIG. 2 is a timing chart showing the relationship between the track pulse signal TP / and the formatter clock pulse signal Fclk. As shown in the figure, the formatter clock pulse signal Fclk is not a continuous pulse train but an intermittent pulse train. That is, in the n-th track, control is performed such that the number of pulses (N) required for this track is output (output pulse total number control method). Does not output a pulse in the n-th track. Then, from the start position of the next (n + 1) th track (when the track pulse signal TP / rises in FIG. 2),
Also, pulse output for the number of pulses required for the track is started. Needless to say, the time from the output of the total pulse of the n-th track to the start of the output of the total pulse of the (n + 1) -th track (GAP time in FIG. 2) is desirably as short as possible. .

A formatter clock pulse signal Fcl of N pulses corresponding to one track is provided.
Since k is used to cut out a part of a continuous pulse train of the pulse signal f1 or the pulse signal f2, its jitter component depends on the jitter of the pulse signals f1 and f2, and a high-precision formatter clock is used. A pulse signal Fclk can be obtained. In the MCAV format, jitter components of pits to be preformatted and alignment of each pit in the radial direction of the optical disk pose a problem, but a temporary lack of pulses for each track due to GAP is small enough to not cause a problem. It is quite possible to do that.

FIG. 3 is a block diagram showing a detailed configuration of the formatter pulse generator 24. As shown in FIG. As shown in the figure, the formatter pulse generator 24
A clock pulse generating circuit 31 for generating a formatter clock pulse signal Fclk from the pulse signal f1; and a formatter clock pulse signal F from the pulse signal f2.
A clock pulse generation circuit 31 'for generating clk is provided. The clock pulse generation circuits 31 and 31 'have the same circuit configuration.

That is, the clock pulse generation circuit 31
(31 ') includes a latch circuit 32 (32'). The latch circuit 32 (32 ') latches the total number data DFPN of the pulses of the track of the formatter clock pulse signal Fclk, and in accordance with a command from the MPU 27, generates the formatter clock pulse signal Fclk for the track to be exposed. Total data DF
Store the PN. The counter circuit 33 (33 ') receives the track pulse signal TP / and the pulse signal f1 (f2) and counts the number of input pulses of the pulse signal f1 (f2) in synchronization with the track pulse signal TP /. In accordance with the total data DFPN, a latch circuit 41 (4
1 '), 42 (42'), 51 (51 '), 52 (5
2 ′) a gate reset signal Gf1 to be a reset signal
/ (Gf2 /) and an error pulse signal EP1 (EP2) which is a pulse train of the pulse signal f1 (f2) during the GAP period (see FIG. 2), and the former is supplied to the phase adjustment gate circuit 34 (34 '). , The latter being the track length error latch circuit 3
5 (35 ').

Track length error latch circuit 35 (35 ')
An error pulse signal EP1 (EP2), a track pulse signal TP /, and a pulse signal f1 (f2) are input to (which is an example of the counter of the present invention). Then, the number of pulses of the error pulse signal EP1 (EP2) is counted, and the counted value is latched in synchronization with the track pulse signal TP /. The gate reset signal Gf1 / (Gf2 /), the track pulse signal TP /, and the pulse signal f1 (f2) are input to the phase adjustment gate circuit 34 (34 '), and the pulse signal is synchronized with the track pulse signal TP /. f1 (f2)
Of the gate reset signal Gf1 / (G
f2 / (f2 /), the pulse signal f1o (f2) having the number of pulses corresponding to the total number of pulses of the track to be exposed.
The signal is output to the clock switching circuit 36 as o).

The latch pulse 37 receives the track pulse signal TP /, latches the clock switching command output from the MPU 27, and outputs the clock switching command to the clock switching circuit 36 in synchronization with the track pulse signal TP /. . The clock switching circuit 36, in accordance with the clock switching command, synchronizes with the track pulse signal TP /
It switches between 1o and f2o and outputs it as a formatter clock pulse signal Fclk.

According to the circuit configuration described with reference to FIG. 3, it is possible to monitor the track length error data and control the track total pulse number data so as to minimize the GAP. The output frequency of the pulse signal f2o may be changed during the output of the pulse signal f1o to prepare the formatter clock pulse signal Fclk for the next zone.

FIG. 4 shows the phase adjustment gate circuit 34 (3
It is a block diagram which shows the detailed structure of 4 '). A pulse signal f1 (f2) is supplied to an S terminal of a latch circuit 41 (41 ′) (which is an example of the latch circuit of the present invention) composed of a positive edge trigger type RS flip-flop by an inverter 43 (43 ′) ( A pulse signal f1 / (f2 /), which is a signal inverted by a phase difference pulse generation circuit according to the present invention), is input to the latch circuit 42 (42) also formed of a positive edge trigger type RS flip-flop. ') (Which is an example of the latch circuit of the present invention) receives the pulse signal f1 (f2) as it is at the S terminal. Also, the latch circuits 41 (41 '), 42
The (42 ') R terminal has a gate reset signal Gf1 /
(Gf2 /) is input, and the track pulse signal TP / is input to the synchronization input terminal.

The input terminal of the AND circuit 44 (44 ') (which constitutes an example of the judgment circuit of the present invention) has the output signal a (a') of the latch circuit 41 (41 ') and the pulse signal f.
1 (f2) is input. The AND circuit 45 (4
5 ') (which constitutes an example of the determination circuit of the present invention) has an input terminal b which is the output signal b of the latch circuit 42 (42').
(B ') and the pulse signal f1 (f2) are
(46 ′) a pulse signal f1 / (f2) which is a signal inverted by (which is an example of the phase difference pulse generation circuit of the present invention)
/) Is input. AND circuits 44 (44 ') and 45
The output signals c (c ′) and d (d ′) of (45 ′) are input to the input terminal of the OR circuit 47 (47 ′).

The output signal e of the OR circuit 47 (47 ') is
The latch circuit 51 (51 ′), 52 (52 ′) composed of a positive edge trigger type RS flip-flop is input to each synchronous input terminal. Also, the latch circuit 5
The output signal a (a ′) is input to the S terminal of the first (51 ′), and the output signal b is input to the S terminal of the latch circuit 52 (52 ′).
(B ') is input. Further, the latch circuit 51 (5
The gate reset signal Gf1 / (Gf2 /) is input to each of the R terminals 1 ′) and 52 (52 ′).

The output signal g (g ') of the latch circuit 51 (51') and the pulse signal f1 (f2) are input to the input terminals of the AND circuit 53 (53 '). The input terminal of the AND circuit 54 (54 ') includes a latch circuit 52 (54').
(52 ') output signal h (h') and pulse signal f1
A pulse signal f1 / (f2 /), which is a signal obtained by inverting (f2) by the inverter 46 (46 ′), is input. Output signals i of AND circuits 54 (54 ') and 55 (55')
(I ′) and j (j ′) are input to the input terminal of the OR circuit 55 (55 ′). The output signal from the OR circuit 47 (47 ') is a pulse signal f1o (f2o) (reference numeral 51).
(51 ′) to 55 (55 ′) constitute an example of the signal selection circuit of the present invention).

FIG. 5 shows the phase adjustment gate circuit 34 (3
It is a timing chart explaining operation of 4 '). In the following, referring to the figure, the phase adjustment gate circuit 34 (3
The operation of 4 ′) will be described.

That is, before the rising edge of the track pulse signal TP /, that is, after outputting the predetermined number of formatter clock pulses for a predetermined number of pulses at the time of the previous track exposure, the latch circuit 42 (4
2 ′) and 41 (41 ′) are gate reset signals Gf1
/ (Gf2 /) has been reset. At the time of the rise of the track pulse signal TP /, the latch circuit 42 (42 ') outputs the H level or L of the pulse signal f1 / (f2 /), and the latch circuit 41 (41') outputs the H level or L of the pulse signal f1 / (f2 /). Latch the state of the level. And
Pulse signal f1 (f2) and pulse signal f1 / (f2 /)
Output an H-level signal and the other an L-level signal because the phases are opposite (in the example of FIG. 5, the output signal a
(A ') goes low and the output signal b (b') goes high). And, of the AND circuit 44 (44 ') and the AND circuit 45 (45'), the one of the output signal a (a ') and the output signal b (b') which is the H level signal is input. For the AND circuit 44 (44 ')
Alternatively, the pulse signal f1 (f2) or the pulse signal f1 / (f2) input to the AND circuit 45 (45 ')
Output signal c (c ') or output signal d that matches /)
(D ′) is output (in the example of FIG. 5, since the output signal b is at the H level, the output signal d (d ′) is the pulse signal f1 /
(F2 /). ). And the output signal e
(E ′) is an output signal c (c ′) or a pulse signal that matches the output signal d (d ′) that matches the pulse signal f1 (f2) or the pulse signal f1 / (f2 /) (see FIG. 5). In the example, it matches the output signal d (d ').)

The latch circuits 51 (51 ') and 52 (5
2 ′) has already been reset by the gate reset signal Gf1 / (Gf2 /) before the rise of the track pulse signal TP /. Latch circuit 51 (51 '), 5
2 (52 ') is a rising edge of the output signal e (e'), latching the output signal a (a ') and the output signal b (b'), respectively, and outputting the output signals g (g '), h (H ') is output. AND circuit 53 (53 ') or AND circuit 5
4 (54 '), the input signal which is the H level of the output signal g (g') or the output signal h (h ') is input from the input pulse signal f1 (f2) or Output signal i that matches pulse signal f1 / (f2 /)
(I ') or the output signal j (j') is output, and the OR circuit 55 (55 ') outputs the pulse signal f1o (f2o) matching the output signal i (i') or the output signal j (j '). (In the example of FIG. 5, the output signal j (j ′) that matches the pulse signal f1 / (f2 /) is the pulse signal f1o (f2o).
Is output as).

With the above circuit configuration,
As shown in FIG. 6, the pulse signal f1o (f2o) is generated in the pulse train of the pulse signal f1 (f2) generated after the rise of the track pulse signal TP /, 1, 2,.
The pulse signal f1 is generated up to the Nth pulse, and thereafter, until the next rise of the track pulse signal TP /.
The pulse train of (f2) corresponds to the error pulse signal EP1 (EP
2). Then, the track length error latch circuit 35
(35 ') counts the number of pulses of the error pulse signal EP1 (EP2) and latches the count value in synchronization with the track pulse signal TP /, so that the MPU 27 converts the latched value into the track length error. It can be monitored as data. Then, the microprocessor can control the output frequency of the programmable oscillator 25 (26) so that the value of the error pulse signal EP1 (EP2) decreases. Further, the phase error of the formatter clock pulse Fclk from the rising position of the track pulse signal TP / is 1 of the pulse signal f1 (f2).
It is adjusted within / 2 cycle.

FIG. 7 is a timing chart schematically showing an example of the output signal waveform of the pulse signal f1o (f2o) generated by the above circuit configuration. Pulse signal f1o
Examples of (f2o) are shown from (A) to (E). The pulse signal f1 (f2) and the inverted pulse signal f
1 / (f2 /) and the pulse signal f1 (f2) or the pulse signal f according to the circuit configuration described with reference to FIG.
An output signal e whose phase is shifted from 1 / (f2 //) in the range of 0 to 1/2 cycle is generated, and the output of the pulse signal f1o (f2o) is started at the first rising timing of the output signal e. Therefore, the actual start position of the track (the pulse signal generated after the rise of the track pulse signal TP /) is compared with the true start position (the rise position of the track pulse signal TP /) of each track of the photoresist master D. f1o (rising position of f2o) is the pulse signal f1o
The phase fluctuates in the range of 0 to 1/2 of the period of (f2o), the phase is adjusted within that range, and the position of the last pulse of the track also fluctuates. However, the jitter accuracy of the formatter clock pulse Fclk in the track and the alignment of the pits in the radial direction of the optical disk can be maintained at a sufficiently high level.

In the example of FIG. 7, the pulse signal f1o (f2
o) are those of (a) to (c) and those of (d) to (o),
The frequency is different. This is because the microprocessor controls the output frequency of the programmable oscillator 25 (26) as described above.

[Second Embodiment of the Invention] The second embodiment is different from the first embodiment in that the phase adjustment gate circuit 34 (34 ') is replaced with the following. It is provided with a phase adjustment gate circuit 61 (61 ') to be described, and the other circuit elements and the like are denoted by the same reference numerals as described above, and detailed description is omitted.

FIG. 8 shows a phase adjustment gate circuit 61 (6
It is a block diagram which shows the circuit structure of 1 '). As shown in FIG. 8, the delay circuit 62 (62 ') (which is an example of the phase difference pulse generation circuit of the present invention) is, for example, a two-stage delay circuit, and has, for example, one cycle of the pulse signal f1 (f2).
/ 6 delays. Then, a pulse signal fd11 (fd12) obtained by delaying the pulse signal f1 (f2) by 周期 of the cycle and a pulse signal f1
A pulse signal f obtained by delaying (f2) by 2/6 of the period
d21 (fd22) is output. The pulse signal f1 (f
2), fd11 (fd12), fd21 (fd22)
Are the inverters 63 (63 ') and 64 (6
4 '), 65 (65') (these inverters are examples of the phase difference pulse generation circuit of the present invention), and pulse signals f1 / (f2 /), fd11 / (fd) are inverted.
12 /) and fd21 / (fd22 /). Further, the pulse signals f1 (f2), fd11 (fd1
2) and fd21 (fd22) are inverter 6
6 (66 '), 67 (67'), 68 (68 ') (these inverters are examples of the phase difference pulse generation circuit of the present invention), and the pulse signal f1 /
(F2 /), fd11 / (fd12 /), fd21 /
(Fd22 /) is output.

The pulse signals f1 (f2), fd11 (fd
12), fd21 (fd22), f1 / (f2 /), f
d11 / (fd12 /), fd21 / (fd22 /)
Are all input to the selector 71 (71 ′).
AND circuits 72 (72 ') and 73 (7
3 '), 74 (74'), 75 (75 '), 76 (7
6 '), 77 (77'). Further, pulse signals f1 (f2), fd11 (fd12),
fd21 (fd22) is input to each S terminal of a latch circuit 81 (81 ′) having three S terminals and Q terminals (which is an example of the latch circuit of the present invention). Further, inverters 66 (66 '), 67 (67'), 68 (6
8 ′), a pulse signal f1 / (f2 /),
fd11 / (fd12 /), fd21 / (fd22 /)
Is a latch circuit 82 (82 ′) also having three S terminals and Q terminals (an example of a latch circuit of the present invention).
Is input to each of the S terminals. The outputs of the latch circuits 82 (82 ') are respectively connected to AND circuits 72 (72') and 74 (7 ').
4 ′) and 76 (76 ′), and the output of the latch circuit 81 (81 ′) is 73 (7 ′).
3 '), 75 (75'), and 77 (77 '). Also, the latch circuits 81 (81 '), 82
(82 ') are all output from the latch circuit 78 (7
8 ').

The AND circuits 72 (72 ') and 73 (7
3 '), 74 (74'), 75 (75 '), 76 (7
6 ′) and 77 (77 ′) are output from the OR circuit 83 (8
3 '), and the OR circuit 83 (8
The output signal of 3 ′) is output to the synchronization input terminal of the latch circuit 78 (78 ′). The latch circuit 78 (78 ')
Each pulse signal f1 (f2), fd11 (fd12), fd21 (fd) when the track pulse signal TP / rises
22), f1 / (f2 //), fd11 / (fd12
/) And fd21 / (fd22 /) at the H level / L level, and from the latched data, the pulse signal f1 (f
2), fd11 (fd12), fd21 (fd22),
f1 / (f2 //), fd11 / (fd12 /), fd2
The first rising pulse signal of 1 / (fd22 /) is selected by the selector 71 (71 ′).
A decoder circuit for outputting the pulse selection signal PSEL is also provided (AND circuits 72 (72 ′), 73 (73 ′),
74 (74 '), 75 (75'), 76 (76 '), 7
7 (77 '), latch circuit 78 (78'), OR circuit 8
3 (83 ') is an example of the determination circuit of the present invention. The selector 71 (71 ') is an example of the signal selection circuit of the present invention. ).

In the phase adjustment gate circuit 34 (34 ') having the above circuit configuration, the inverter 63 (6'
3 '), 64 (64'), 65 (65 '), 66 (6
6 '), 67 (67') and 68 (68 ') correspond to the inverters 43 (43') and 46 (46 '), and the latch circuits 81 (81') and 82 (82 ') correspond to the latch circuits. 41
(41 ') and 42 (42'), and the AND circuit 72
(72 '), 73 (73'), 74 (74 '), 75
(75 '), 76 (76'), 77 (77 ') correspond to the AND circuits 44 (44'), 45 (45 '), and the OR circuit 83 (83') corresponds to the OR circuit 47 (47 '). ). In this embodiment, a plurality of pulse signals fd11 (fd12) and fd21 (fd2), which are the phase delay of the pulse signal f1 (f2), are generated by the delay circuit 62.
2) (this delay time may be within 1/2 of the phase of the pulse signal f1 (f2)), and pulse signals f1 / (f2 /), fd1 which are inverted signals of these pulse signals.
When 1 / (fd12 /) and fd21 / (fd22 /) are also included, as shown in FIG.
At positions l, m, n, o, and p, the adjustment resolution is reduced to 1/3 and the adjustment accuracy is improved three times as compared with the first embodiment. It should be noted that if the signal of the phase delay of the pulse signal f1 (f2) is further subdivided and generated, the adjustment resolution and the adjustment accuracy can be further improved.

The delay circuit 62 (62 ') may be fixed when the frequency range required for the formatter clock pulse signal Fclk is narrow to some extent, but may be fixed when the required frequency range is widened. It is desirable to improve the phase adjustment accuracy by using a programmable delay circuit capable of setting a delay time in a programmable manner according to the output frequency.

[0051]

According to the first aspect of the present invention, there is provided a turntable on which a photoresist master of an optical disk is mounted and rotated, a spindle motor for rotating the turntable, and a direction in which the turntable is oriented in the surface of the photoresist master. , A light source for emitting a laser beam for exposing the photoresist master, a formatter for encoding a signal of information to be written on the photoresist master, and turning the laser light ON and OFF according to the encoded signal. By doing so, an optical modulator that converts the laser light into an optical signal whose pulse width is adjusted, and a pulse signal for a drive command of the spindle motor is generated,
A spindle motor drive pulse generator for generating a track pulse signal for determining a reference position of a track on the optical disc, a traverse motor drive pulse generator for generating a pulse signal for a drive command of the traverse motor, a programmable oscillator, And a formatter pulse generator that outputs a predetermined number of output pulses of the programmable oscillator as the formatter clock pulse signal in synchronization with the track pulse signal. Since it can be used as a clock pulse signal for formatter in synchronization with the pulse signal, it is suitable for exposure of the master disc of the MCAV format or the like, which requires a high cutting frequency and low jitter specifications. .

According to a second aspect of the present invention, in the first aspect, after outputting a predetermined number of formatter clock pulse signals for one track of the optical disk, the next track pulse signal is changed to a spindle motor drive pulse. Since a counter for counting the time until output from the generator is provided, it is possible to monitor an error with respect to the arrangement of the clock pulse signal for the true formatter within one track of the optical disc, so that temperature drift, aging change For example, it is possible to correct a change in the frequency of the programmable oscillator due to, for example, bringing the actual pulse signal closer to the arrangement of the clock pulse signal for the true formatter.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the formatter pulse generator generates one or more types of pulse signals having a phase difference between the output pulse signals of the programmable oscillator. A phase difference pulse generation circuit, a latch circuit for latching the rise of the track pulse signal to the H level or the fall to the L level, and first after the latch circuit latches the rise or the fall of the track pulse signal, A determination circuit for determining which of the rising edge to the H level or the falling edge to the L level is at least one of the out-of-phase pulse signal of the output pulse signal of the programmable oscillator and the out-of-phase pulse signal; , It is determined that the signal has first risen to the H level. And a signal selection circuit for selecting a pulse signal and supplying it to the formatter.In addition to the output pulse signal of the programmable oscillator, a pulse signal having a phase difference is generated. After the track pulse signal rises to the H level or falls to the L level, a pulse signal that is determined to have first risen to the H level or fall to the L level is selected, and a clock pulse signal for a formatter is selected. Therefore, the phase shift of the formatter clock pulse signal between the tracks of the optical disk can be reduced.

According to a fourth aspect of the present invention, in the third aspect, the phase difference pulse generation circuit includes an inverter for generating an inverted pulse signal of an output pulse of the programmable oscillator. Since the inverted pulse signal can be generated as a pulse signal having a phase difference between the output pulse signals, it is possible to reduce the phase shift of the formatter clock pulse signal between the tracks of the optical disk within a half cycle of the output frequency. it can.

According to a fifth aspect of the present invention, in the third or fourth aspect of the present invention, the phase difference pulse generating circuit includes a delay circuit that generates a phase-lagged pulse from an output pulse of the programmable oscillator. Since a pulse signal which is a phase difference of an output pulse signal of a programmable oscillator can be generated with a phase delay of various magnitudes, a phase shift of a formatter clock pulse signal between tracks of an optical disc can be further reduced. .

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the delay circuit can set the phase delay time in a programmable manner. Can be generated with accurate time intervals, so that the phase shift of the formatter clock pulse signal between the tracks of the optical disk can always be minimized corresponding to a wide range of output frequencies.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an exposure apparatus for an optical disc master according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a track pulse signal and a formatter clock pulse signal by the exposure apparatus for the master optical disc.

FIG. 3 is a block diagram showing a circuit configuration of a pulse generator for a formatter of the exposure apparatus for the master optical disc.

FIG. 4 is a block diagram showing a circuit configuration of a phase adjustment gate circuit of the formatter pulse generator.

FIG. 5 is a timing chart illustrating an operation of the phase adjustment gate circuit.

FIG. 6 is a timing chart of a track pulse signal, a formatter clock pulse signal, an error pulse signal, and a gate reset signal in the optical disk master exposure apparatus.

FIG. 7 is a timing chart of a track pulse signal and a formatter clock pulse signal in the exposure apparatus for the master optical disc.

FIG. 8 is a block diagram showing a circuit configuration of a phase adjustment gate circuit of an exposure apparatus for an optical disc master according to a second embodiment of the present invention.

FIG. 9 is a timing chart illustrating the operation of the phase adjustment gate circuit.

FIG. 10 is a block diagram illustrating a conventional optical disc master exposure apparatus.

EXPLANATION OF SYMBOLS 1 Exposure device for optical disk master 2 Turntable 4 Spindle motor 6 Lateral feed motor 11 Light source 12 Laser light 14 Optical modulator 16 Formatter 21 Crystal oscillator 22 Spindle motor drive pulse generator 23 Horizontal drive motor drive pulse generator 24 Formatter Pulse generator 25 Programmable oscillator 26 Programmable oscillator 35, 35 'Counter 41, 41' Latch circuit 43, 43 'Phase difference pulse generation circuit 44, 44' Judgment circuit 45, 45 'Judgment circuit 51, 51'-55, 55' Signal selection circuits 62, 62 'Phase difference pulse generation circuits 63, 63' to 65, 65 'Phase difference pulse generation circuits 66, 66' to 68, 68 'Phase difference pulse generation circuits 71, 71' Signal selection circuits 72, 72 '~ 78, 78' Judgment circuit 81 81 ', 82, 82' Latch circuit 83, 83 'Judgment circuit D Photoresist master fo Basic clock f1 Output pulse signal of programmable oscillator f2 Output pulse signal of programmable oscillator Tf Pulse signal for spindle motor drive command Sf Transverse motor drive command Pulse signal TP / Track pulse Fclk Clock pulse signal for formatter

Claims (6)

[Claims] A turntable for rotating a photoresist master of an optical disc mounted thereon; a spindle motor for rotating the turntable; a transverse motor for moving the turntable in the direction of the surface of the photoresist master; A light source for emitting laser light for exposing the photoresist master, a formatter for encoding a signal of information to be written on the photoresist master, and turning on and off the laser light according to the encoded signal
By performing FF, an optical modulator that converts the laser light into an optical signal whose pulse width is adjusted, a pulse signal for driving the spindle motor, and a reference position of a track on the optical disc are determined. A spindle motor drive pulse generator for generating a track pulse signal; a transverse motor drive pulse generator for generating a pulse signal for a drive command of the transverse motor; and a spindle motor drive pulse generator and a transverse motor drive pulse generator. A crystal oscillator that supplies a clock; a programmable oscillator; and a formatter pulse generator that outputs a predetermined number of output pulse signals of the programmable oscillator as the formatter clock pulse signal in synchronization with the track pulse signal. light The exposure apparatus of the disk master. 2. A counter for counting the time from outputting a predetermined number of formatter clock pulse signals for one track of an optical disk to outputting the next track pulse signal from a spindle motor drive pulse generator. An exposure apparatus for an optical disk master according to claim 1. 3. A pulse generator for a formatter, comprising: a phase difference pulse generation circuit for generating one or a plurality of types of pulse signals which are different in phase of an output pulse signal of a programmable oscillator; A latch circuit for latching a fall to a level; and a latch circuit for latching a rise or a fall of the track pulse signal, and then rising first to an H level or falling to an L level first. A decision circuit for deciding which of the output pulse signal of the oscillator and the pulse signal of the out-of-phase is at least one of the pulse signals of the out-of-phase; and a pulse signal which is determined to first rise to the H level by the decision circuit. A signal selection circuit for selecting and supplying to the formatter; Provided by and claims exposure device of an optical disk master according to 1 or 2. 4. The exposure apparatus according to claim 3, wherein the phase difference pulse generation circuit includes an inverter that generates an inverted pulse signal of an output pulse of the programmable oscillator. 5. The apparatus according to claim 3, wherein the phase difference pulse generation circuit includes a delay circuit that generates a pulse with a phase delay from an output pulse of the programmable oscillator. 6. The exposure apparatus according to claim 5, wherein the delay circuit can set a phase delay time in a programmable manner.