JPH11145824A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit(IC) which can be developed and prepared in a short time, without producing an IC for every specification change, while suppressing the generation of new development cost for preparing the IC again each time, when the specification of a glass mask required for producing the IC is changed for the specification changes which are capable of being realized with only slight changes on a logic circuit which are generally called master slice. SOLUTION: A circuit specifications are changed by executing the state setting of whether or not a fuse element built in the IC is to be cut at the time of an IC wafer check process. Plural input circuits 10 composed of fuse elements 4 and pull-down resistors 5 are provided. The state setting is performed corresponding to whether or not the fuse elements 4 of plural input terminals 1 are to be cut, and a signal 101 showing the potential states of the respective input terminals is inputted to a decode circuit 8. The decode circuit 8 outputs a decode signal 80 for operation switching corresponding to the state or combining the input signals 101. A circuit 9 for switching circuit operation according to the decode signal 80 for operation switching is able to change a circuit operating function which corresponds to the inputted decode signal 80 for operation switching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having a MIS structure.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device having a MIS structure (hereinafter referred to as an "IC"), when a circuit operation specification is generally changed, a logic circuit design is required for a cell-based IC or a standard cell type IC. And the layout design of the IC has to be redesigned. That is, it was necessary to develop one IC for one model. In addition, it has been necessary to make changes after the wiring step in the manufacture of ICs, such as gate arrays. Alternatively, if the circuit modification scale of the specification change is small, the IC is provided with a switching terminal for switching the circuit operation specification, and the switching terminal is set to a high level or a low level outside the IC to change the specification. I have responded.

[0003]

However, in the conventional development method as described above, when it is intended to implement even a slight change in circuit specifications generally called a master slice,
In cell-based ICs and standard cell ICs, I
It was necessary to redesign the layout design of C from the beginning, and there was a problem that the development cost and the development period were too long. Also, even if changes are made after the wiring process, as in the case of gate arrays, the development cost and development period will be reduced as compared with the initial process of design and manufacturing, but it will not be eliminated at all but fundamentally. It didn't work out. In addition, in a method corresponding to the outside of the IC, a mounting area and a mounting process increase. Alternatively, there has been a problem that the cost of the mounting surface is increased, such as a need to change the mounting substrate.

Therefore, the present invention solves such a problem, and an object of the present invention is to deal with a change in the specifications of an IC that can be realized by a slight change in a logic circuit generally called a master slice in advance. An IC that can be developed and created in a short period of time without the need to manufacture new ICs every time a specification change is required. To provide.

[0005]

In a semiconductor integrated circuit device having a MIS structure, a fuse element for electrically shorting or opening is connected between at least one power supply terminal and an input terminal, and the other power supply terminal is connected to the input terminal. A circuit configuration in which a resistance element having a higher resistance than the short-circuited resistance value of the fuse element is connected therebetween, and a circuit whose circuit operation function is switched according to the potential state of the input signal using the input terminal as an input signal is connected. It is characterized by the following.

A decoding circuit having a plurality of the input terminals and outputting a decode signal indicating a combination state of the plurality of input signals using a potential state of the plurality of input terminals as an input signal; And a circuit configuration in which a circuit whose circuit operation function is switched is connected.

[0007] A polysilicon element is used as the fuse element.

The invention is characterized in that an aluminum element used as a wiring material in a semiconductor integrated circuit device is used as the fuse element.

[0009]

According to the above-described circuit configuration of the present invention, it is determined whether or not the fuse element built in the IC should be cut in response to a change in specifications which can be realized by a slight circuit change generally called a master slice in advance. By performing the setting during the wafer inspection process of the IC, it is possible to change the circuit specifications. Therefore, there is no need to create a new glass mask, and it is possible to suppress development costs. Further, since it is necessary to develop the IC every time the specification is changed, it is possible to create and deliver the IC in a short time.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Reference numeral 1 denotes an input terminal using a fuse element, and 2 denotes a first power supply terminal (hereinafter referred to as a “VDD terminal”) which supplies a potential to the entire circuit of the IC, or a potential to the entire circuit of the IC. This is a fuse cutting power supply terminal in which a resistance element and the like are connected in series from a power supply terminal for supplying the power supply. Reference numeral 3 denotes a second power supply terminal (hereinafter referred to as a "VSS terminal"), a power supply terminal for supplying a potential to the entire IC circuit, or a resistance element or the like in series from a power supply terminal for supplying a potential to the entire IC circuit. Is a fuse cutting power supply terminal connected to the power supply. Reference numeral 4 denotes a fuse element built in the IC, which is realized by using a polysilicon resistance element of about 100Ω or an aluminum wiring material used for internal wiring of the IC.

FIG. 10 is a plan layout diagram of an embodiment of a fuse element realized by a polysilicon resistance element, and FIG. 11 is a plan layout diagram of an embodiment of a fuse element realized by an aluminum wiring material. 30 is a pad area. 31 is a fuse element using a polysilicon resistance element. 32 is
Fuse element using aluminum wiring material element. 33 is
Power wiring area. Numeral 34 denotes an electrostatic protection element arrangement area.
Reference numeral 5 denotes a pull-down resistance element, and FIGS. 5 and 6 show examples of the circuit configuration. In FIG. 5, it is realized by a depletion type N-channel MIS transistor 51, and in FIG. 6, it is realized by a depletion type N-channel MIS transistor 51, an enhancement type N-channel MIS transistor 52 and an inverter circuit 53. The depletion type N channel MIS
The transistor 51 has a constant current circuit configuration, but may have a circuit configuration in which a gate electrode is connected to a VDD terminal. Reference numeral 6 denotes a circuit whose circuit operation function is switched by a signal 101 indicating the potential state of the input terminal 1. FIG. 9 shows an example implemented by a counter circuit.

Next, the operation of the embodiment shown in FIG. 1 will be described.

In FIG. 1, when the fuse element 4 is connected, the resistance value of the fuse element 4 is set lower than the resistance value of the pull-down resistance element 5, so that a signal indicating the potential state of the input terminal 1 is provided. 101 goes high. When the fuse element 4 is cut and is in an open state, the signal 101 indicating the potential state of the input terminal 1 becomes low level by the pull-down resistor 5. The fuse element 4 can be opened by blowing a current between the VDD terminal 2 and the input terminal 1 to blow it.

FIG. 9 shows an example of a counter circuit as an example of the circuit 6 whose circuit operation functions are switched. 61 is a clock signal input terminal, 62 is a reset signal input terminal, 63 is
The counter circuit output terminal 64 is a circuit operation switching signal input terminal. In FIG. 1, when the fuse element 4 is connected, the input terminal 1 is at a high level. When a high level is input to the circuit 6 whose circuit operation is switched by the signal 101 indicating the potential state of the input terminal, the counter of FIG. 9 operates as a quinary counter. In the wafer inspection process, when the fuse element 4 is cut and the input terminal 1 is set to low level, the counter of FIG. 9 operates as a hexadecimal counter by the signal 101 indicating the potential state of the input terminal. That is,
By setting the potential state of the input terminal 1 to a high level or a low level depending on whether or not the fuse element 4 of the input terminal 1 is cut in the wafer inspection process, the operation specification of the counter circuit is changed to the IC of the quinary counter operation specification. The circuit operation specification can be switched to an IC having a binary counter operation specification, and an IC having a different circuit operation specification can be created in the wafer inspection process. In general, the circuit increase of the circuit 6 whose circuit operation function can be realized at the master slice level is as follows.
At present, the integrated circuit technology has been improved to several percent in terms of chip area, and the increase in cost is negligible.

Therefore, as shown in FIG. 9, if a circuit 6 whose circuit operation is switched according to the master slice specification prepared in advance in the logic circuit design stage of the IC according to the potential state of the input terminal 1 is prepared inside the IC, In a wafer inspection process stage after completion of the wafer, the input terminal 1 is determined by whether or not the fuse element is cut so as to satisfy a circuit operation specification to be created.
Having a desired function by setting the potential state of
C can be created.

In FIG. 2, a similar circuit configuration can be realized by the fuse element 4 and the pull-up resistor 7. Reference numeral 7 denotes a pull-up resistance element, and a configuration example is shown in FIGS. In FIG. 7, it is realized by a depletion-type P-channel MIS transistor 54, and in FIG. 8, it is realized by a depletion-type P-channel MIS transistor 54, an enhancement-type P-channel MIS transistor 55, and an inverter circuit 53. The depletion-type P-channel MIS
The transistor 54 is a constant current circuit, but may have a circuit configuration in which a gate electrode is connected to a VSS terminal.

FIG. 3 shows an embodiment in which a plurality of the input terminals 1 are provided. In the embodiment of FIG. 3, a plurality of input circuits 10 each including a fuse element 4 and a pull-down resistor 5 are provided. Fuse element 4 of a plurality of input terminals 1
And a signal 101 indicating the potential state of each input terminal is input to the decoding circuit 8.
The decoding circuit 8 outputs an operation switching decode signal 80 corresponding to the combination state of the input signal 101.
The circuit 9 whose circuit operation is switched by the operation switching decode signal 80 can change the circuit operation function in accordance with the input operation switching decode signal 80. Therefore, while only two states can be set in FIG. 1, three or more operation functions can be switched according to the number of input terminals. FIG. 4 also has a plurality of input circuits 20 each including a fuse element 4 and a pull-up resistor 7.
A function change similar to that of FIG. 3 can be realized.

[0019]

As described above, according to the present invention, in a wafer inspection process, a fuse of an input terminal having a fuse element can be used for a specification change which can be realized by a slight circuit change generally called a master slice. An IC that performs a desired operation function by setting the state depending on whether the element is cut or not
, It is not necessary to manufacture an IC from a wafer process every time a specification is changed, it is possible to eliminate the development cost of a new glass mask and the like, and to produce a desired IC in a short time. It has excellent effects such as being able to do. In addition, since only one type of IC needs to be manufactured in the wafer manufacturing process, there is an excellent effect such as rationalization of process management and inventory management.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing an embodiment of an input pull-down resistor.

FIG. 6 is a circuit diagram showing an embodiment of an input pull-down resistor.

FIG. 7 is a circuit diagram showing an embodiment of an input pull-up resistor.

FIG. 8 is a circuit diagram showing an embodiment of an input pull-up resistor.

FIG. 9 is a circuit diagram showing an embodiment of a circuit whose circuit operation is switched by an input signal.

FIG. 10 is a plan layout view of a fuse element formed on a semiconductor substrate with a polysilicon resistor.

FIG. 11 is a plan layout view of a fuse element formed of an aluminum wiring element on a semiconductor substrate.

[Explanation of symbols]

1 is an input terminal using a fuse element, 2 is a VDD terminal, 3 is a VSS terminal, 4 is a fuse element, 5 is a pull-down resistor, and 6 is a pull-down resistor. The up-resistance element 8 is a decoding circuit 9. The circuit 10 whose circuit operation function is switched by a decoding signal. The input circuit 20 is composed of a pull-down resistor and a fuse element. The input circuit 20 is composed of a pull-up resistance and a fuse element. Is a pad region 31 is a fuse element using a polysilicon resistance element 32 is a fuse element 33 using an aluminum wiring material 33 is a power supply wiring area 34 is an electrostatic protection element area 51 is a depletion type N-channel MIS The transistor 52 is an enhancement type N-channel MIS transistor Data circuit 54, a depletion-type P-channel MIS transistor 55, an enhancement-type P-channel MIS transistor 61, a clock signal input terminal 62, a reset signal input terminal 63, a counter circuit output terminal 64, and a circuit operation switching terminal. A signal input terminal 80 is a circuit operation switching decode signal 101 is a signal indicating the potential state of the input terminal.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/088

Claims (6)

[Claims] In a semiconductor integrated circuit device having a MIS structure, a fuse element for electrically shorting or opening is connected between at least a first power supply terminal and an input terminal;
A resistance element having a higher resistance than the short-circuited resistance value of the fuse element is connected between the power supply terminal and the input terminal;
A semiconductor integrated circuit device having a circuit configuration in which a circuit whose circuit operation function is switched according to a potential state of the input signal with the input terminal as an input signal is connected. 2. A semiconductor integrated circuit device having an MIS structure, wherein a fuse element for electrically shorting or opening is connected between at least a second power supply terminal and an input terminal, and
A resistance element having a higher resistance than the short-circuited resistance value of the fuse element is connected between the power supply terminal and the input terminal;
A semiconductor integrated circuit device having a circuit configuration in which a circuit whose circuit operation function is switched according to a potential state of the input signal with the input terminal as an input signal is connected. 3. A fuse element for electrically shorting or opening between at least a first power supply terminal and an input terminal according to claim 1, wherein said fuse element is electrically connected between a second power supply terminal and said input terminal. A decode signal having a plurality of input terminals to which a resistance element having a higher resistance than the resistance value in the short-circuit state is connected, and a potential state of the plurality of input terminals is used as an input signal to indicate a combined state of the plurality of input signals. And a circuit for switching a circuit operation function by using the decode signal as an input. 4. A fuse element for electrically shorting or opening between at least a second power supply terminal and an input terminal according to claim 2, wherein said fuse element is electrically connected between said first power supply terminal and said input terminal. A decode signal having a plurality of input terminals to which a resistance element having a higher resistance than the resistance value in the short-circuit state is connected, and a potential state of the plurality of input terminals is used as an input signal to indicate a combined state of the plurality of input signals. And a circuit for switching a circuit operation function by using the decode signal as an input. 5. A semiconductor integrated circuit device using a polysilicon element as the fuse element according to claim 1 or 2. 6. A semiconductor integrated circuit device according to claim 1, wherein an aluminum element used as a wiring material in the semiconductor integrated circuit device is used as the fuse element according to claim 1.