JPH11145819A - Output buffer circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of obtaining a desired output amplitude, even when the power supply voltage of an internal circuit is lowered in a semiconductor integrated circuit for outputting the signal of a small amplitude such as a GTL level by using a push-pull type output step. SOLUTION: A push-pull type output step is provided with a P-channel MOSFET (Q1) and an N-channel MOSFET (Q2) in a serial mode. Between the gate terminal of the P-channel MOSFET connected to a power supply voltage terminal on the side of a high potential and a logic gate circuit (G1) forming the control signal of this gate terminal, a control voltage drop circuit composed of a first switch MOSFET (M1) to be turned on/off corresponding to a data signal to be outputted, a second switch MOSFET (M2) to be turned on/off complementarily with the first switch MOSFET (M1) while being connected between the source and drain of the first switch MOSFET (M1) a capacitor (C1) and a rectifying means (M3) for limiting the charging voltage of the capacitor (C1).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology particularly effective when applied to a push-pull type output buffer circuit in a semiconductor integrated circuit technology and a logic integrated circuit, for example, a technology suitable for use in a GTL output buffer circuit. About.

[0002]

2. Description of the Related Art Conventionally, as an output buffer circuit of a CMOS logic LSI, a push-pull GT as shown in FIG.
An L (Gunning Transceiver Logic) output buffer circuit is known. In this circuit, an output stage 1 is composed of two N-channel MOSFETs Q1 'and Q2 in a serial form, and each output MOSFET is a CMOS inverter and a NAND.
An output control circuit 2 composed of a gate is configured to be turned on and off, and an output stage 1 is connected to a power supply voltage Vc of an internal circuit.
It is driven by a power supply voltage VTT such as 1.2 V which is smaller than c (3.3 V), a pull-up resistor 11 is connected to the terminal side of the transmission line 12, and a signal is transmitted with a low amplitude (0 to 1.2 V). By doing so, low power consumption and high speed signal transmission are achieved.

[0003]

Conventionally, the above G
In the TL output buffer circuit, the output stage 1 has 1.2 V
Although the output control circuit 2 is driven by a low power supply voltage as described above, the output control circuit 2 operates at 3.3 V. Therefore, the pull-up MOSFET Q1 'and the pull-down MOSFET
The high-level control signal supplied to the gate terminal of the FET Q2 is 3.3 V, which is sufficiently higher than the power supply voltage of the output stage of 1.2 V. Therefore, any of the output MOSFETs can be sufficiently turned on.
A signal having an amplitude of 2 V could be output, and the output buffer circuit could be operated without any problem.

However, in recent years, the power supply voltage of a semiconductor integrated circuit has been reduced due to a demand for lowering the withstand voltage of the element and a reduction in power consumption due to higher integration, and the internal power supply voltage of the LSI will be 1.8 V in the future. Low voltage is expected.

[0005] When the internal power supply voltage drops as described above,
When the output stage is constituted by an N-channel MOSFET push-pull circuit as shown in FIG. 3, the high level of the output signal is equal to the gate voltage of the output MOSFET Q1 '(1.8).
V) lower than the potential (1.8-V) by the threshold voltage Vth.
th) only. Besides, MOSFET Q
1 'is a so-called substrate effect, in which the threshold voltage is increased. That is, the base (substrate or well region) of the MOSFET Q1 'is set to Vss (0 V), but the voltage of the source region connected to the output terminal varies in a range of 0 to 1.2 V according to the output voltage. Therefore, when the source voltage Vs is at the low level output equal to the base voltage Vb, the threshold voltage of Q1 'is about 0.2 V, but when the source voltage Vs is at the high level output higher than the base voltage Vb, the threshold voltage of Q1' is high. The voltage increases to about 0.7V. As a result, the output amplitude became 0 to 1.1 V, and it became clear that there was a problem that 0 to 1.2 V specified for the GTL interface could not be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to output a signal having a small amplitude such as a GTL level using a push-pull type output stage. An object of the present invention is to provide an output buffer circuit in which a desired output amplitude can be obtained even when the power supply voltage of an internal circuit is reduced in an integrated circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the push-pull type output stage of the output buffer circuit is composed of a serial P-channel MOSFET and an N-channel MOSFET,
P-channel MO connected to the power supply terminal on the high potential side
A first switch MOSFET that is turned on and off according to a data signal to be output between a gate terminal of the SFET and a logic gate circuit that forms a control signal for the gate terminal.
A second switch MOSFET connected between the source and the drain of the first switch MOSFET and turned on and off complementarily to the first switch MOSFET, a capacitor, and a rectifier for limiting a charging voltage of the capacitor. A control voltage drop circuit is provided.

According to the above-described means, when the P-channel MOSFET constituting the output stage is turned off, its gate terminal is charged via the first switch MOSFET and a sufficient potential difference is generated in the capacitor. P
When the channel MOSFET is on, its gate terminal is in a floating state and the second switch MOSFET is turned on.
, The gate voltage can be reduced to a negative potential by the attraction effect of the capacitor, thereby sufficiently turning on the output P-channel MOSFET and reliably increasing the output amplitude to the power supply voltage level of the output stage. Can be.

A so-called diode-connected MOSFET having a gate and a drain coupled as the rectifier.
It is good to use. As a result, the output P-channel MO can be reduced compared to the case where a PN junction diode is used.
By increasing the storage potential difference of the capacitor when the SFET is off, the gate-source voltage when the output P-channel MOSFET is on can be increased.

Further, the first switch MOSFET is constituted by a P-channel MOSFET, and the second switch MOSFET is constituted by an N-channel MOSFET. Accordingly, the data signal supplied from the internal circuit can be directly supplied to the gate terminals of the first switch MOSFET and the second switch MOSFET to perform complementary ON / OFF operations, thereby simplifying the configuration of the output control circuit. can do.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

The output buffer circuit of this embodiment has a power supply voltage terminal VTT having a lower potential than the power supply voltage Vcc of the internal circuit.
(For example, 1.2 V) and a grounded potential (0 V), a push-pull type output stage 1 composed of a P-channel MOSFET Q1 and an N-channel MOSFET Q2 connected in series, and each of the output MOSFETs Q1 and Q2. And an output control circuit 2 for forming a gate control signal. The power supply voltage Vcc of the internal circuit is not particularly limited, but is about 1.8 V in this embodiment.

The output control circuit 2 has a NOR gate G having an input signal of a data signal DT supplied from an internal circuit and an enable signal / EN for controlling the output of data.
2 and a NAND having a signal obtained by inverting the data signal DT and the enable signal / EN by the inverter INV1 as input signals
And a gate G1. The above NOR gate G
Although the enable signal / EN input to 2 may be an internal signal as it is, in this embodiment, a signal inverted twice by two inverters INV1 and INV2 is used as an input signal. The output signal of the NOR gate G2 is supplied to the gate terminal of the output side N-channel MOSFET Q2 on the ground side.

A control voltage lowering circuit 3 is provided between the output terminal of the NAND gate G1 and the gate terminal of the output P-channel MOSFET Q1. The control voltage drop circuit 3 has a source and a drain connected to the output terminal of the NAND gate G1 and the gate terminal of the output P-channel MOSFET Q1, respectively, and is turned on and off in accordance with a data signal to be output.
ET M1, a second switch MOSFET M2 connected between the source and drain of the first switch MOSFET M1, the data signal DT being input to the gate terminal, a capacitor C1, and a MOS for limiting the charging voltage of the capacitor C1.
FET M3.

The first switch MOSFET M1 is P
Channel MOSFET and second switch MOSF
ET M2 is composed of an N-channel MOSFET, and includes a first switch MOSFET M1 and a second switch M
The OSFET M2 receives the data signal DT at its gate terminal and is turned on and off complementarily to each other. On the other hand, the MOSFET M3 is a so-called diode-connected MOSFET having a gate and a drain coupled to each other, and has a gate and a drain connected to the second switch MOSFET.
It is connected to the connection node N2 between T M2 and the capacitor C1, and the source is connected to the ground point.

Next, the operation of the output buffer circuit, particularly the control voltage drop circuit, will be described with reference to the waveform diagram of FIG.

In the output buffer circuit of this embodiment, when the enable signal / EN is set to the high level, the output MOSF
ET Q1 and Q2 are both turned off and output terminal OU
T is in a high impedance state. When the enable signal / EN is set to the low level, the output buffer circuit is brought into an operating state, and the output M is set according to the data signal DT at that time.
One of the OSFETs Q1 and Q2 is turned on, and a signal Dout at a corresponding level is output from the output terminal OUT to the outside.

First, consider a case where the enable signal / EN is at a low level and the data signal DT changes from a high level such as Vcc (1.8 V) to a low level (0 V) (period T1 in FIG. 2). At this time, the output of the NOR gate G2 changes from low level to high level, the output N-channel MOSFET Q2 shifts from off state to on state, and the output signal Dout changes from high level to low level. Further, the output of the NAND gate G2 changes from low level to high level (1.8V),
Since the data signal DT changes from high level to low level, the first switch MOSFET M1 shifts from off to on, and the output signal of the NAND gate G1 changes to M1.
Is transmitted to the gate terminal of the output P-channel MOSFET Q1 and charged to raise it to the Vcc level, so that the potentials of the nodes N1 and N3 are changed as shown in FIG.
(D) from low level to high level (1.8V)
Is changed to Thereby, the output P-channel MOS
The FET Q1 shifts from the on state to the off state, and the output signal Dout becomes the ground potential (0 V).

On the other hand, since the potential of the node N2 is connected to the node N1 via the capacitor C1, the potential of the node N2 once rises as the potential of the node N1 rises as shown by the symbol A in FIG. Since a diode-connected MOSFET M3 is connected between the node N2 and the ground point, the electric charge at the node N2 is drawn toward the ground point via the MOSFET M3 due to the rise in the potential of the node N2. The potential of N2 is higher than that of the ground point (0 V)
The potential drops to a potential higher by the threshold voltage Vth (about 0.2 V) of M3, and then this potential is held until the data signal DT changes to a high level (period T2 in FIG. 2).

Next, the data signal DT goes low (0
V) to a high level such as Vcc (1.8 V), the output of the NOR gate G2 changes from the high level to the low level, and the output N-channel MOSFET Q2
Is shifted from the on state to the off state. Also, NAND
Since the output of the gate G1 changes from high level to low level, the potential of the node N1 also changes from high level to low level, and the data signal DT changes from low level to high level.
T M1 changes from on to off and the second switch MOSFET
TM2 shifts from off to on. Therefore, the gate terminal (N3) of the output P-channel MOSFET Q1 is connected to the node N2.

As a result, the potential of the node N2 is induced by the voltage drop of the node N1 via the capacitor C1.
, The gate voltage of the node N3, that is, the gate voltage of Q1, also drops to -0.6V.
As a result, the output P-channel MOSFET Q1 shifts from the OFF state to the ON state, and at this time, a large voltage such as 1.8 (= 1.2 + 0.6) V is applied between the gate and the source. Is turned on,
The output signal Dout is at the same level (1.2 V) as the power supply voltage VTT of the output stage 1.

The output stage 1 is simply connected to a P-channel MOSFET Q1 and an N-channel MOSFET Q as shown in FIG.
2 is a push-pull circuit in which the N-channel MOSFETs 2 are connected in series, a voltage close to a withstand voltage of 1.8 V is applied between the gate and source of the N-channel MOSFET Q2 on the ground side when the P-channel MOSFET Q1 is turned on. Since only a voltage of 1.2 V is applied between the gate and the source of the N-channel MOSFET even when turned on, there is a disadvantage that the operation speed is slower than that of the N-channel MOSFET Q2 on the ground side. Is provided with a control voltage dropping circuit 3 so that 1.2 + 0.6 = 1.8 between the gate and the source when the P-channel MOSFET Q1 is turned on.
Since the same voltage as V between the gate and the source of the N-channel MOSFET Q2 on the ground side can be applied, the operation speed can be made equal to that of the N-channel MOSFET Q2. As a result, the performance of the output buffer circuit can be significantly improved as compared with the circuit of FIG. 4 having no control voltage drop circuit.

In the above embodiment, the output P-channel MOSFET Q1 is provided with a control voltage dropping circuit for increasing the gate-source voltage on the side of the MOSFET Q1. If permitted, that is, if the breakdown voltage of the N-channel MOSFET is sufficiently higher than the power supply voltage Vcc (1.8 V in the embodiment), a control voltage boosting circuit for increasing the gate-source voltage of the output N-channel MOSFET Q2 is provided. May be provided.

In the circuit of the embodiment, a PN junction diode can be used in principle instead of the diode-connected MOSFET M3. In the case of the PN junction diode, the forward voltage is about 0.7 V. On the other hand, in the diode-connected MOSFET, the forward voltage is almost equal to the threshold voltage (0.2 V), so that the output P is higher than when a PN junction diode is used.
By increasing the accumulated potential difference of the capacitor C1 when the channel MOSFET Q1 is off, the output P-channel M
The gate-source voltage at the time of turning on the OSFET Q1 can be increased to just before the breakdown voltage.

Further, in the above embodiment, the first switch M
The OSFET is composed of a P-channel MOSFET, and the second switch MOSFET is composed of an N-channel MOSFET.
FETs, but MOs of the same conductivity type
It is also possible to use an SFET. However, if they are of the same conductivity type, an inverter for inverting the gate control signal (data signal DT in the embodiment) is required to turn them on and off in a complementary manner. It is slightly more complicated than in the embodiment.

Further, in the GTL output buffer circuit, by designing the impedance of the output P-channel MOSFET Q1 so as to match the impedance Z0 of the transmission line, it is possible to prevent signal reflection at the end of the transmission line. It can be omitted.
However, in the GTL output buffer circuit as shown in FIG. 4, since the gate-source voltage of the output P-channel MOSFET Q1 is small, the region C where the change in the source-drain voltage-drain current characteristic curve shown in FIG. Since MOSFET Q1 will be used in
The impedance of Q1 is changed to the impedance Z0 of the transmission line.
Even if it is designed so as to conform to the above, the variation in impedance becomes large due to the process variation. for that reason,
As shown in FIG. 4, it is necessary to connect the pull-up resistor 11 to the terminal side of the transmission line 12.

On the other hand, in the GTL output buffer circuit of the above embodiment, the output P-channel MOSFET
Since the gate-source voltage of Q1 is large, Q1 is used in the region D where the change in the source-drain voltage-drain current characteristic is small, and the variation in the impedance of the output MOSFET due to the process variation is reduced. This makes it easy to match the impedance of Q1 with the impedance Z0 of the transmission line,
There is also an advantage that connection without terminating resistance of the transmission line can be performed.

As described above, in the output buffer circuit of the above embodiment, a push-pull type output stage is connected
A signal is to be output between a gate terminal of a P-channel MOSFET connected to a high-potential-side power supply voltage terminal and a logic gate circuit for forming a control signal for the gate terminal. A first switch MOSFET that is turned on and off in response to a data signal, and the first switch MOSFET
The first switch M connected between the source and drain of
Second switch M which is turned on / off complementarily to OSFET
Since the control voltage drop circuit including the OSFET, the capacitor, and the rectifying means for limiting the charging voltage of the capacitor is provided, the P-channel MOSFET constituting the output stage is provided.
When T is off, its gate terminal is connected to the first switch MOS.
By charging through the FET and generating a sufficient potential difference in the capacitor, when the P-channel MOSFET is turned on, its gate terminal is set in a floating state and the second switch MOSFET is turned on, so that the attraction action by the capacitor is performed. Can lower the gate voltage to the negative potential, and thereby the output P-channel MOSF
By sufficiently turning on ET, the output amplitude can be reliably increased to the power supply voltage level of the output stage, and the operating speed of the output P-channel MOSFET can be increased by the output N-channel M
There is an effect that it can be improved to the same degree as the OSFET.

A so-called diode-connected MOSFET having a gate and a drain coupled as the rectifying means.
Is used, the storage potential difference of the capacitance when the output P-channel MOSFET is turned off is increased as compared with the case where a PN junction diode is used, and the gate-source voltage when the output P-channel MOSFET is turned on is increased. There is an effect that can be.

Further, since the first switch MOSFET is constituted by a P-channel MOSFET and the second switch MOSFET is constituted by an N-channel MOSFET, a data signal supplied from an internal circuit is directly transmitted to the first switch MOSFET. In addition, complementary ON and OFF operations can be performed by supplying the signal to the gate terminal of the second switch MOSFET, and the configuration of the output control circuit can be simplified.

Although the present invention has been described in detail with reference to the embodiments, it is needless to say that the present invention is not limited to the above embodiments, and various changes can be made without departing from the scope of the invention. . For example, in the above embodiment, the case where the present invention is applied to the GTL output buffer circuit has been described. However, the present invention has a push-pull type output stage in which two MOSFETs are connected in series between power supply voltage terminals, and outputs a signal with a small amplitude. The present invention can be generally applied to an output buffer circuit for outputting. Further, in the above embodiment, the description has been given of the case where the present invention is applied to a single-ended output buffer circuit.
The output buffer circuit may be configured such that two output buffer circuits are arranged side by side to input signals of opposite phases and output differentially. In the embodiment, the power supply voltage is 1.2 V in the output stage,
Although the output control circuit and the internal circuit are set to 1.8 V, these are merely examples, and the present invention is effective when applied to a case where the power supply voltage of the output control circuit is higher than the power supply voltage of the output stage.

Further, in the embodiment, the case where the present invention is applied to a tri-state buffer whose output can be in a high impedance state has been described. However, the present invention is applied to a non-tri-state output buffer, that is, an output buffer circuit of a type not controlled by the enable signal / EN. It is also possible to apply. Further, in the embodiment, the NOR logic gate circuit and the NAND logic gate circuit are used as the logic gates for forming the control signals. However, the present invention is not limited to this. A circuit may be used.

[0035]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit that outputs a signal with a small amplitude such as a GTL level by using a push-pull type output stage, a desired output amplitude can be obtained even if the power supply voltage of the internal circuit is reduced. An output buffer circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment when the present invention is applied to a GTL output buffer circuit.

FIG. 2 is a waveform chart showing changes in input / output signals and potentials at respective nodes in the GTL output buffer circuit of the embodiment.

FIG. 3 is a circuit diagram showing an example of a conventional GTL output buffer circuit.

FIG. 4 is a circuit diagram illustrating an example of a GTL output buffer circuit as a comparative example.

FIG. 5 is a graph showing source-drain voltage-drain current characteristics of a MOSFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Push-pull type output stage 2 Output control circuit 3 Control voltage drop circuit 11 Termination resistance (pull-up resistance) 12 Transmission line Q1 Output P-channel MOSFET Q2 Output N-channel MOSFET M1 First switch MOSFET M2 Second switch MOSFET M3 Diode connection MOSFET (rectifying means) G1 NAND gate circuit (first logic gate circuit) G2 NOR gate circuit (second logic gate circuit) DT Data signal

Claims (4)

[Claims] 1. A P-channel MO connected in series between a power supply voltage terminal receiving a first power supply voltage and a ground point.
A push-pull type output stage comprising an SFET and an N-channel MOSFET, and a P-channel based on a data signal to be output which is supplied from an internal circuit upon receiving a second power supply voltage higher than the first power supply voltage. MOSFET
And an output control circuit including a first logic gate circuit and a second logic gate respectively controlling an N-channel MOSFET, wherein at least the first logic gate circuit and the P-channel MOSF
A first switch MOSFET that is turned on and off in response to the data signal between the gate terminal of the ET, and a first switch MOSFET that is connected between a source and a drain of the first switch MOSFET and that is turned on complementarily to the first switch MOSFET; An output buffer circuit comprising: a control voltage dropping circuit comprising a second switch MOSFET and a capacitor to be turned off, and a rectifier for limiting a charging voltage of the capacitor. 2. The output buffer circuit according to claim 1, wherein said rectifying means comprises a MOSFET having a gate and a drain coupled to each other. 3. The first switch MOSFET comprises a P-channel MOSFET, and the second switch MO
3. The output buffer circuit according to claim 1, wherein the SFET comprises an N-channel MOSFET. 4. A semiconductor integrated circuit comprising the output buffer circuit according to claim 1.