JPH11144492A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device in which an increase in the number of terminals can be suppressed to a required minimum and in which a redundant memory can be inspected nondestructively while an increase in the area of a chip is being suppressed by a method wherein an input terminal is owned jointly. SOLUTION: When a defective memory cell is detected in a normal memory 30, the address of the defective memory cell is registered on a redundancy selection circuit 102. When a memory is accessed, the redundancy selection circuit 102 is set so as to be accessed to either the normal memory 30 or a redundant memory 20 according to the compared result of an input address with a registered address. According to a control signal RSEL, redundancy coersion selection circuit 101 selects and accesses a memory cell in the redundancy memory 20 according to the input address irrespective of the existence of the registered address. As a result, a redundancy memory cell can be inspected nondestructively. When the input terminal of the addresses is owned jointly, an increase in the number of terminals can be suppressed, an increase in the area of a memory chip can be suppressed to a required minimum, and the cost of a semiconductor memory device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a redundant memory cell for replacing a defective memory cell in a normal memory cell array.

[0002]

2. Description of the Related Art With the advance of semiconductor fine processing technology, the capacity of semiconductor memory devices has been increasing. On the other hand, as the storage capacity increases, the probability that defective memory cells will occur in the memory chip increases, which is a major cause of reducing the yield of the memory chip. For this reason, a redundant memory cell that substitutes for a defective memory cell is previously arranged on a memory chip,
When a defective memory cell is detected when a product is inspected, a redundancy measure for relieving the defective memory cell with the redundant memory cell is generally adopted.

The relief by the redundant memory cells is performed in units of memory cells in one row along a word line or one column along a bit line in a normal memory cell array. An address corresponding to the location of one row or one column of memory cells including a defective memory cell is stored in an address registration circuit by address registration. When an attempt is made to access a memory cell in a row or a column including a defective memory cell at the time of memory access, a match between the address registered in the address registration circuit by the redundant circuit and the address input from the outside is obtained. Detected, and according to this matched detection result,
The redundancy switching circuit accesses a one-row or one-column redundant memory cell group composed of redundant memory cells instead of the one-row or one-column memory cell group including the defective memory cell.

Normally, address registration in the address registration circuit is performed by cutting a fuse by a laser or an overcurrent. This address registration is also called programming. That is, programming performed according to the location of the defective memory cell is an irreversible operation, and the address once registered is fixed as it is. Therefore, it is not possible to non-destructively inspect a redundant memory cell before repairing a defective memory cell.

However, due to the increase in the capacity of the memory chip,
The capacity of the redundant memory also increases, and the area occupied by the redundant memory tends to increase. Therefore, the probability that a defective memory cell occurs in the redundant memory increases. If a normal memory cell is rescued by the defective memory cell, the success rate of the rescue decreases. In addition, there is a problem that performing repair with a redundant memory having a defect wastes time required for programming and the like and lowers work efficiency. Therefore, there is a need for a method for non-destructively testing a redundant memory before repairing a regular memory. One way is to
Equipped with a redundant forced selection function that forcibly selects a redundant memory cell according to the externally input redundant address before programming, accesses it, and checks whether it operates normally. Semiconductor storage devices have been proposed.

FIG. 3 shows a configuration example of a semiconductor memory device having such a redundant forced selection function. As shown in the figure, the semiconductor memory device of the present example has a redundancy switching circuit 10
a, redundant memory cell array 20, memory cell array 3
0, address buffer 40, row decoder 50, control buffer 60, column decoder 70, sense amplifier / write driver 80, and input / output buffer (I / O
(Buffer) 90.

[0007] As shown in the figure, the redundancy switching circuit 10a includes a redundant compulsory selection circuit 101a and a redundancy selection circuit 10a.
2a. In the semiconductor memory device of this example, one row of memory cells including a defective memory cell in the memory cell array 30 is replaced by one row of redundant memory cells in the redundant memory cell array 20. A row address specifying a memory cell row including a defective memory cell is registered in the memory cell array 30 by programming in the redundancy selection circuit 102a. At the time of memory access, among the (m + 1) -bit addresses A0... Am input to the address buffer 40, the row address is compared with the registered address, and if these addresses match, the redundancy selection circuit 102a sets the row The decoder 50 is set to an inactive state, that is, a stopped state. Instead, one is selected from a plurality of redundant word lines RWL according to the registered redundant address and activated. That is, a high-level voltage, for example, a voltage slightly higher than the power supply voltage V _DD is applied to the selected redundant word line RWL.

When the row address does not match the registered address among the input (m + 1) -bit addresses A0... Am, the row decoder 50 outputs a word designated by the row address from a plurality of word lines WL. Select a line and activate it. In this case, the selection of the redundant word line RWL is not performed.

The redundant compulsory selecting circuit 101a responds to a redundant compulsory selecting signal RSEL from the outside, regardless of the presence or absence of address registration in the redundant selecting circuit, and the redundant addresses RA0.
The redundant memory cell specified by Ar is forcibly selected and accessed.

Specifically, when the forced selection of the redundant memory cell is not performed, the input terminal of the redundant forced selection signal RSEL is set to the open state. In this case, the redundancy selection circuit compares the row address at the input address A0... Am with the address registered by programming, and accesses either the memory cell array 30 or the redundant memory cell array 20 according to the comparison result. Do.

When the forced selection is performed, the redundant forced selection signal R
SEL is set to a certain level, for example, a power supply voltage level. In response, the redundant forced selection circuit 101a
The externally input redundant addresses RA0 to RAr are input to the redundant selection circuit 102a. Redundancy selection circuit 102a
Selects a specified word line from the redundant word lines RWL according to the redundant address from the redundant forced selection circuit 101a. Also, when performing the redundant selection, the row decoder 5
0 is set to the inactive state.

As described above, by providing the redundant forced selection circuit 101a, a predetermined redundant memory cell row is selected from the redundant memory cell array 20 in accordance with a redundant address input from the outside, regardless of the registration of the address. Access to the redundant memory cell can be performed. Therefore, the redundant memory cells can be inspected non-destructively, and the success rate of the relief by the redundant memory can be improved.

[0013]

In the conventional semiconductor memory device described above, a redundant address input terminal (pad) is provided to a memory chip in order to input a redundant address.
It is necessary to provide. For this reason, there is a disadvantage that the area of the memory chip is increased and the cost is increased.

The present invention has been made in view of such circumstances, and an object of the present invention is to minimize the number of terminals by sharing the existing terminals on the chip to avoid an increase in the memory chip area. It is an object of the present invention to provide a semiconductor memory device capable of realizing input of a redundant address while suppressing redundancy, and realizing non-destructive inspection of a redundant memory.

[0015]

In order to achieve the above object, a semiconductor memory device of the present invention has a redundant memory cell for replacing a defective memory cell in a normal memory cell array,
By registering the address of the defective memory cell,
A semiconductor memory device for accessing said redundant memory cell instead of said defective memory cell at the time of memory access, wherein an input address and said registered address are compared, and when these addresses match, access to said normal memory cell array is performed. And a redundancy switching circuit for selecting the redundant memory cell, and when receiving a predetermined control signal from the outside, at least one bit of the input address is taken out as a redundant address, and the redundant memory is selected according to the redundant address. A redundant forced selection circuit for selecting a cell and prohibiting access to the normal memory cell.

Further, in the present invention, it is preferable that a normal decoder for selecting a predetermined memory cell of the normal memory cell array in accordance with the input address is provided, and the redundancy switching circuit includes the input address and the registered address. When the values match, the normal decoder is set to a non-operating state, and further, the redundancy forced selection circuit sets the normal decoder to a non-operating state when receiving the predetermined control signal.

Further, in the present invention, preferably, the semiconductor memory device has a plurality of the redundant memory cells, and the redundant forced selection circuit selects a predetermined memory cell from the plurality of the redundant memory cells according to the redundant address. It has a redundant decoder.

Further, in the present invention, the address registration of the defective memory cell is performed by cutting the fuse.

According to the present invention, when a defective memory cell is detected in the normal memory cell array, the address of the defective memory cell is stored by address registration. At the time of memory access, the input address and the registered address are compared by the redundancy switching circuit, and access is made to a normal memory cell or a redundant memory cell according to the comparison result.
Furthermore, in the present invention, a redundant compulsory selection circuit is provided, irrespective of the presence or absence of address registration, a part or all of the input address is set as a redundant address according to a control signal from the outside, and a redundant memory cell is set according to the redundant address Is selected and access is made to it.

As a result, the redundant memory cell can be selected according to the external input address by the redundant forcible selection circuit before the address is registered by fuse cutting or the like. For this reason, by sequentially selecting the redundant memory cells and performing writing and reading on the selected redundant memory cells, the quality of the redundant memory cells can be confirmed, so that the success rate of the relief by the redundant memory can be improved. Further, by sharing the address input terminal, an increase in the number of terminals can be avoided, an increase in the chip area can be suppressed, and a reduction in cost can be realized.

[0021]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention. As illustrated, the semiconductor memory device of the present embodiment includes a redundancy switching circuit 10,
It comprises a redundant memory cell array 20, a memory cell array 30, an address buffer 40, a row decoder 50, a control buffer 60, a column decoder 70, a sense amplifier / write driver 80, and an input / output buffer 90.

As shown, the redundancy switching circuit 10
It is composed of a redundant selection circuit 101 and a redundancy selection circuit 102. In the semiconductor memory device of the present embodiment, one row of memory cells in the word line direction including a defective memory cell in the memory cell array 30 is replaced by one row of redundant memory cells in the redundant memory cell array 20, that is, a so-called row redundancy. The method is adopted. Note that the present invention is not limited to this, and a so-called column redundancy system in which one column of memory cells including a defective memory cell in the bit line direction is replaced with a redundant memory cell column can be employed.

The memory cell array 30 includes a plurality of memory cells arranged in a matrix. The memory cells arranged in each row are connected to the same word line, and the memory cells arranged in each column are connected to the same bit line. As described above, in this embodiment, when a defective memory cell is found in the memory cell array 30, the address of the memory cell row including the defective memory cell is registered in the redundancy selection circuit 102. At the time of memory access, one row of memory cells including the defective memory cell is replaced by one row of redundant memory cells in the redundant memory cell array 20. That is, when an arbitrary memory cell in one row including a defective memory cell is specified by the input address,
A comparison result is obtained in which the registered address matches the row address in the input address by the redundancy selection circuit. In response, row decoder 50 is set to the inactive state, and the selection of word line WL is not performed. Instead, only one of the redundant word lines RWL is selected and activated according to the registered redundant address.

When a row other than the memory row containing the defective memory cell is designated by the input address, the row decoder 50 selects one of the word lines WL of the memory cell array 30 according to the row address of the input address. Activate it.

The address buffer 40 temporarily holds (m + 1) -bit input addresses A0... Am, and stores the held addresses in the redundancy selection circuit 10 in the redundancy switching circuit 10.
2 or the row decoder 50.

The row decoder 50 includes an address buffer 4
0, a plurality of word lines W
Select only one from L and activate it. That is,
The row decoder selects a predetermined address row according to the row address.

The control buffer 60 responds to a plurality of externally input control signals, for example, a chip enable signal / CE, a write enable signal / WE and a read enable signal / OE.
0, a control signal is output to the sense amplifier / write driver 80 and the input / output buffer 90 to control each operation. Here, “/” indicates an active state at a low level. That is, the above-described control signals input to the control buffer 60 are normally held at a high level, that is, in an inactive state, and when held at a low level, the enable states indicated by the respective control signals become valid.

The column decoder 70 receives a column address for selecting a column from the addresses input from the address buffer 40, and selects a predetermined bit line of the memory cell array 30 according to the column address.

As described above, the row decoder 50 and the column decoder 70 select the word line and the bit line specified by the input address A0... Am, and select the memory cell connected to the selected word line and the selected bit line. You. At the time of memory access, writing or reading is performed on the selected memory cell.

The sense amplifier / write driver 80 amplifies the data of the bit line selected by the column decoder 70 at the time of reading and outputs the data to the input buffer 90.
At the time of writing, input data from the input / output buffer 90 is amplified and output to the bit line selected by the column decoder 70.

The input / output buffer 90 latches read data output from the sense amplifier / write driver 80 at the time of reading, and inputs data terminals I / O0.
n. Input terminals I / O0 ... I /
The write data input to On is latched and output to the sense amplifier / write driver 80.

The configuration and operation of the redundancy switching circuit 10 will be described in detail below. As shown in FIG. 1, the redundancy switching circuit 10 includes a forced redundancy selection circuit 101.
And a redundancy selection circuit 102. Redundancy selection circuit 102
Has an address registration circuit (not shown). The address registration circuit includes, for example, a plurality of fuses.
A predetermined fuse is cut by programming according to the registered address.

When a defective memory cell is detected in the memory cell array 30 during inspection before shipment, a row address designating a memory cell row including the defective memory cell in the memory cell array 30 is registered in the redundancy selection circuit 102 by programming. . During memory access, address buffer 4
Am of (m + 1) bits input to 0
Are compared with the registered address, for example, the row address, for example, the address (A + 1)... Ar of (r + 1) bits, and when these addresses match, the redundancy selection circuit 102
The row decoder 50 is set to the inactive state. Instead, one is selected from a plurality of redundant word lines RWL according to the registered redundant address and activated.

On the other hand, when the row address A0... Ar does not match the registered address, the row decoder 50 selects a word line specified by the row address from a plurality of word lines WL and activates it. In this case, the selection of the redundant word line RWL is not performed.

As described above, the registered address and the input address are compared by the redundancy selection circuit 102 during normal memory access, and when the addresses match, access to the memory cell array 30 is prohibited. Access to the redundant memory cell array 20 is performed.
When the registered address does not match the input address, access to the memory cell array 30 is performed. That is, according to the address registered in the address registration circuit and the input address during normal memory access, the redundancy selection circuit 10
2, the normal memory and the redundant memory are switched.

Since the address registration in the address registration circuit, that is, the programming is performed by cutting the fuse as described above, the registered address cannot be changed. Therefore, means for non-destructively testing the redundant memory cell array 20 is required. In this embodiment,
By providing the redundant switching circuit 10 with the redundant forcible selection circuit 101, each redundant memory cell of the redundant memory cell array 20 is forcibly selected regardless of address registration.
By accessing, non-destructive inspection of the redundant memory cell array 20 is realized.

The forced redundancy selection circuit 101 responds to an externally required forced redundancy selection signal RSEL.
Address buffer 4
Am of (m + 1) bits input to 0
, For example, a row address A0... A of (r + 1) bits
r is taken in as a redundant address, the redundant word line RWL designated by the redundant address is forcibly selected and activated.

A portion of the address A0... Am input from the outside is taken in as a redundant address, and the redundant word line RWL is selected accordingly, so that there is no need to provide a dedicated redundant address terminal and input the redundant address. In this way, by sharing the address terminals,
The number of terminals of the memory chip can be suppressed to a necessary minimum, and accordingly, an increase in the chip area can be suppressed, and the cost of the memory chip can be reduced.

FIG. 2 shows an example of the configuration of the forced redundancy selection circuit 101. Hereinafter, the configuration and operation will be described with reference to FIG. In FIG. 2, the redundant selection circuit 102, the redundant memory cell array 20, and the row decoder 50 are also shown for explanation of the operation.

As shown in FIG.
Are redundant decoder 111, AND gate array 112,
An OR gate array 113 and an OR gate 114 are provided. The forced redundancy selection circuit 101 operates according to a forced redundancy selection signal RSEL. As shown, the input terminal 103 of the redundant forced selection signal RSEL and the ground potential G
The transistor 105 is connected to the ND.
The transistor 105 is formed of, for example, an nMOS transistor. When a predetermined bias voltage is applied to the gate electrode, a large resistance is generated between the source and the drain of the transistor. That is, the transistor 105
It is used as a resistance element having a large resistance value.
Therefore, the input terminal 103 of the redundant forced selection signal RSEL
Is in an open state (open), the input terminal 103 is held at the ground potential GND level.

In this case, the output terminal of each AND gate of the AND gate array 112 is kept at a low level.
Since a low-level signal is input to the enable signal terminal ENB of the redundancy selection circuit 102, the redundancy selection circuit is set to an operation state. The input address A0... Am is taken into the redundancy selection circuit 102, the input address is compared with the registered address, and a high-level signal is output to the redundancy enable signal line 110 when the comparison result matches. In response, the output terminal of the OR gate 114, that is, the row decoder enable signal line is held at a high level, and the enable signal terminal ENB of the row decoder 50 is held at a high level. Is set to

Further, in this case, the redundancy selection circuit 102
Outputs a selection signal for selecting a redundant memory according to the redundant address to the redundant memory selection signal line 109. In accordance with this, the output signal of each OR gate of OR gate array 113 is determined, and only the redundant word line specified by the redundant address among redundant word lines 107 is activated.

On the other hand, when the redundant selection circuit obtains a comparison result indicating that the redundant address does not match the registered address, it outputs a low-level signal to the redundant enable signal line 110. In response, the output terminal of the OR gate 114, that is, the row decoder enable signal line 108 is held at a low level, and the enable signal terminal ENB of the row decoder 50 is held at a low level. Is set. The row decoder 50 activates only the word line specified by the row address among the plurality of word lines WL according to the row address among the input addresses.

As described above, the redundant forced selection signal RSEL
When there is no high-level signal input to the input terminal 103, the redundant selection circuit 102 is kept in the operating state, and either the redundant memory or the normal memory is selected according to the comparison result between the input address and the registered address. You.

When the redundant compulsory selection signal RSEL is set to a high level, the input terminal 103 is held at a high level, and the redundancy selection circuit 102 is set to a non-operating state accordingly. Further, since the output terminal of the OR gate 114 is held at the high level, the enable signal terminal ENB of the row decoder 50 is held at the high level, and the row decoder 50 is set to the non-operating state.

The redundant addresses A0... Ar input from the redundant address signal line 104 are input to the redundant decoder 111. The redundancy decoder 111 generates a redundancy memory selection signal for selecting a redundancy memory cell according to the redundancy address, and inputs the signal to each AND gate of the AND gate array 112. AND gate array 112 according to an input signal
Output signal of each AND gate is set, and the OR gate 1
13 is input. In this case, the redundant memory selection signal line 1
Since all the bits 09 are held at the low level by the redundancy selection circuit 102, the output signal of each OR gate of the OR gate 113 is set according to the output signal of the redundancy decoder 111. That is, only one of the redundant word lines 107 is selected and activated according to the input redundant address A0... Ar.

By setting the redundant selection signal RSEL to a high level, the redundancy selection circuit 102 is held in a non-operating state, and the inner row addresses A0... Ar of the input addresses are taken into the redundancy decoder 111 as redundant addresses.
According to the redundant address, the redundant memory cell array 20
Out of the redundant word lines 107, only one designated redundant word line is selected. In this case, since the row decoder 50 is set to the non-operation state, the normal memory is not accessed. Thus, the redundancy selection circuit 1
Regardless of the registered address of 02, any redundant memory cell in the redundant memory cell array 20 can be selected according to an externally input address, and the redundant memory can be inspected nondestructively.

As described above, according to the present embodiment, when a defective memory cell is detected in the memory cell array 30, the address of the defective memory cell is registered in the redundancy selection circuit 102. At the time of memory access, the redundancy selection circuit 102 sets access to either the memory cell array 30 or the redundant memory cell array 20 according to the result of comparison between the input address and the registered address. The redundant forcible selection circuit 101 forcibly selects a memory cell in the redundant memory cell array 20 according to the input address regardless of the presence or absence of the registered address according to the control signal RSEL.
Since access is performed, redundant memory cells can be inspected nondestructively, and by sharing address input terminals, an increase in the number of terminals can be suppressed, and an increase in the area of the memory chip can be suppressed to a necessary minimum. Reduction can be realized.

[0049]

As described above, according to the semiconductor memory device of the present invention, an increase in the area of the memory chip can be suppressed.
By sharing the existing terminals on the chip, the input of the redundant address can be realized while suppressing the increase in the number of terminals to a necessary minimum, and there is an advantage that the redundant memory can be inspected nondestructively.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a redundant forced selection circuit;

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device having a redundant function.

[Explanation of symbols]

10, 10a: redundancy switching circuit, 20: redundancy memory cell array, 30: memory cell array, 40: address buffer, 50: row decoder, 60: control buffer, 70: column decoder, 80: sense amplifier / write driver, 90: input Output buffer, 101, 101
a: redundancy forced selection circuit, 102, 102a: redundancy selection circuit, 103: control signal RSEL input terminal, 104: redundancy address signal line, 105: transistor, 106: address input terminal, 107: redundancy word line, 108: row Decoder enable signal line, 109: redundant memory selection signal line, 110: redundant enable signal line, 111: redundant decoder, 112: AND gate array, 113: OR gate array, 114: OR gate, V _CC : power supply voltage, G
ND: ground potential.

Claims (6)

[Claims] The present invention has a redundant memory cell in which a defective memory cell of a normal memory cell array is replaced. By registering an address of the defective memory cell, the redundant memory cell is replaced with the redundant memory cell at the time of memory access. A semiconductor memory device to be accessed, wherein an input address is compared with the registered address, and when these addresses match, a redundancy switching circuit for inhibiting access to the normal memory cell array and selecting the redundant memory cell; Upon receiving a predetermined control signal from the outside, at least one bit of the input address is taken out as a redundant address, the redundant memory cell is selected according to the redundant address, and access to the normal memory cell is prohibited. A semiconductor memory device having a redundant forced selection circuit. 2. The semiconductor memory device according to claim 1, further comprising a normal decoder for selecting a predetermined memory cell of said normal memory cell array according to said input address. 3. The semiconductor memory device according to claim 2, wherein said redundancy switching circuit sets said normal decoder to an inactive state when said input address and said registered address match. 4. The semiconductor memory device according to claim 2, wherein said redundant compulsory selection circuit sets said normal decoder to a non-operating state when receiving said predetermined control signal. 5. The semiconductor memory device according to claim 1, further comprising a plurality of said redundant memory cells, wherein said redundant forced selection circuit includes a redundant decoder for selecting a predetermined memory cell from said plurality of redundant memory cells according to said redundant address. 13. The semiconductor memory device according to claim 1. 6. The semiconductor memory device according to claim 1, wherein the address registration of said defective memory cell is performed by cutting a fuse.