JPH11144064A - Processor and method for information processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change the function of a processing unit without stopping the operation of a drawing pipeline by providing a selector means which receives control lines for processing contents together with information obtained from a host device and supplies it to the drawing pipeline. SOLUTION: The information processing system 11 converts three-dimensional data into data which can be displayed on a display part 17 such as a display and outputs them. A host computer 12 decomposes the three-dimensional data into graphic elements and performs geometric transformation and then supplies result as data in packet form to the information processor 13. The information processor 13 performs a previously set process for the three-dimensional data supplied from the host computer 12 and generates and expands image data to be drawn on a frame memory 14. A microprogram execution part 19 analyzes the date in packet form supplied from the host computer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus and an information processing method, and more particularly to an information processing apparatus and an information processing method for performing information processing of three-dimensional graphics. In recent years, semiconductor integrated circuits for realizing multimedia information processing apparatuses have been actively developed. In the multimedia field, it is required to realize various types of data such as moving images, audio, and CG data on one device.
In addition, with the progress of semiconductor integrated circuits, those that have been realized by using a plurality of semiconductor integrated circuits have now become one.
It has become possible to realize equivalent functions in the device. However, it is extremely difficult to handle various types of data and to build all functions in a semiconductor integrated circuit of a limited scale.

Therefore, a basic logical operation function provided in a semiconductor integrated circuit is described in a program by a control method based on a stored program method (a method for realizing a necessary logical function by a generally used microprogram). Thus, the desired functions are realized in various combinations. In the above method, even if the same logical function can be realized as a whole, the number of instructions to be combined increases or decreases, so that processing may not actually be completed within a predetermined time. In terms of aspects, processing functions (algorithms) in all fields cannot be realized by only one set of logical functions (instruction sets).

[0003] Therefore, the purpose of use and the frequently used logic function that is mainly used are defined in advance as one instruction, and optimization is performed so that the instruction can be executed at high speed by hardware. ing. On the other hand, when high-speed information processing of three-dimensional graphics is performed, it is effective to execute a combination of relatively monotonous processing and relatively complicated capturing processing performed to simplify the processing. This requires a processing device that combines processing by the stored program method and processing by hardware.

[0004]

2. Description of the Related Art FIG. 55 is a block diagram showing an example of a conventional information processing apparatus. The host computer 41 is connected to a display device 44 via a graphic processing unit 42 and a frame memory 43. Host computer 41
The three-dimensional image data formed in the frame memory is expanded two-dimensionally by the graphic processing unit 42, and the frame memory 4
3 and displayed on the display device 44.

The graphic processing section 42 includes a DDA (linear interpolation processing) section 42a for interpolating data based on the data of each vertex of the polygon from the host computer 41, a texture processing section 42b for performing a pattern attaching process on the polygon, Drawing data based on data functions, etc.
The image forming apparatus includes a drawing condition determining unit 42c for determining non-drawing and a blender unit 42d for performing a blender process for mixing colors before and after a pixel. The processing of each unit is performed by pipeline processing.

The data processed by the graphic processing section 42 is developed on a frame memory 43. Display device 4
4 displays an image corresponding to the data developed on the frame memory 43. The graphic processing unit 42 is configured to execute only dedicated processing by pipeline processing, and corrects data for processing by the graphic processing unit 42, for example, by changing coordinates of a polygon to be drawn to coordinates of display pixels. Capturing processing such as matching with the host computer has been performed in the host computer 41 in advance.

[0007]

In the conventional information processing apparatus, the calculation of the end points between the vertices of the polygonal figure requires complicated processing such as correction, and is therefore performed on the host computer having a high degree of freedom in processing. I was As a result, the processing load on the host computer increases, and data must be read from the host computer. Therefore, switching of the viewpoint position and the like cannot be performed at high speed, and the processing of the three-dimensional image can be efficiently performed. There were problems such as inability to do so.

[0008] The present invention has been made in view of the above points, and an object of the present invention is to provide an information processing apparatus and an information processing method capable of efficiently processing information.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, a first information processing means 1 executes a dedicated process set in advance on input information. The second information processing means 2 can execute processing in parallel with the first information processing means, and executes processing on the input information according to control information.

An object of the present invention is an information processing apparatus connected to a memory means for storing first information indirectly involved in generation of image information to be displayed.
A drawing pipeline for performing pipeline processing on the first information and second information directly related to generation of image information to be displayed, and supplying generated image information to the memory unit; , N is a natural number, a processing unit having an operation means for calculating the second information and an interpretation means for interpreting the first information, and a register for storing the output of the processing unit are alternately set to n. And selector means for collectively receiving a control line of processing contents corresponding to each of the n-stage processing units together with the second information obtained from a higher-level device and supplying the control line to the drawing pipeline. It can also be achieved by an information processing device.

According to a second aspect of the present invention, in the first aspect of the invention, information for handling both the first and second information and one of the first and second information are used. Means for supplying information comprising a tag indicating whether there is a tag to the drawing pipeline, wherein each processing unit of the drawing pipeline detects the tag and processes the supplied information by the arithmetic means. Decide whether to process with the interpretation means.

According to the third aspect of the present invention, the first or second aspect is provided.
In the invention described above, an end point tag indicating an end point is added to the last point of the polygon when the polygon information from a higher-level device is decomposed into points, the end point tag being added to the second stage. And a lock unit provided in a stage immediately before the processing unit that needs the first information from the memory unit in the drawing pipeline. When the end point tag added to the input second information is on, the second information is regarded as the end point information of the polygon, and the second information is included in the drawing pipeline including the second information. Processing is performed to stop the subsequent information until all the remaining information is output from the drawing pipeline.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the output means has means for outputting an end point tag only when a waiting process is required. According to a fifth aspect of the present invention, in the third or fourth aspect, the lock unit stops the subsequent information until all the information remaining on the drawing pipeline is output from the drawing pipeline. A mechanism and means for activating the lock mechanism by the end point tag only when there is a waiting process.

According to a sixth aspect of the present invention, in the first aspect of the present invention, the first processing unit is used as an address presenting unit and used only for giving an address to the memory means. A second processing unit for receiving data output from the memory means and used as a data receiving unit; and a plurality of pipelines for absorbing a delay corresponding to a latency between the first and second processing units. And a register.

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the request is provided between the memory means and the drawing pipeline, and when the memory means is performing a read operation, a request for a read queue is prioritized. While the memory means is performing the write operation, the request in the write queue is preferentially processed and the write operation is continuously performed so that the write operation is performed continuously. Arbitration means for suppressing a loss time due to switching to a read operation is further provided.

According to an eighth aspect of the present invention, in the first aspect of the present invention, the memory means comprises a synchronous memory. The above object is achieved by claim 9,
An information processing apparatus connected to a memory unit for storing first information indirectly involved in generation of image information to be displayed, wherein the information processing apparatus is directly involved in generation of the first information and image information to be displayed. A drawing pipeline for performing pipeline processing on the second information and supplying generated image information to the memory unit; the drawing pipeline performs an operation on the second information when n is a natural number; Arithmetic means and the first
A processing unit having interpretation means for interpreting the information of
The register for storing the output of the processing unit is alternately n
The memory means is composed of a synchronous memory and comprises a first memory connected to the arbitration circuit, and a second memory connected to the display means. Both the read operation and the write operation are performed from the drawing pipeline, and both the write operation from the drawing pipeline and the access request processing from the display unit are performed on the second memory, The first
Is achieved by an information processing apparatus having a first storage area for storing original image information and a second storage area for storing control information provided one-to-one with the original image information. Is done.

According to a tenth aspect of the present invention, in the ninth aspect of the present invention, the drawing pipeline has an address presenting unit and a data accepting unit connected to the arbitrating means, and the address presenting unit and the data The receiving units each include means for caching control information. According to an eleventh aspect of the present invention, in the invention of the tenth aspect, the address presentation unit includes a unit for storing information indicating which address of the second storage area is being cached, and the control information has already been stored. When caching is performed, the address at which the original image information is stored is presented to the first memory, and the control information is not cached, or an address different from the cached control information is used. When the control information is required, the address at which the control information is stored is changed to the first address.
When the control information is the first value, the data receiving unit transmits the data received from the first memory to the next unit of the drawing pipeline, and the control information is In the case of the second value, a predetermined value is transmitted to the next unit of the drawing pipeline.

According to a twelfth aspect of the present invention, in the ninth aspect of the present invention, the drawing pipeline has a processing unit that is incorporated in a final stage thereof and has a control information caching function. An object of the present invention is an information processing method in an information processing apparatus connected to a memory means for storing first information indirectly involved in generation of image information to be displayed, according to claim 13, A first step of performing pipeline processing on the first information and second information directly involved in generation of image information to be displayed, and supplying the generated image information to the memory means; , N is a natural number, a processing unit having an operation means for calculating the second information and an interpretation means for interpreting the first information, and a register for storing the output of the processing unit are alternately n. Using a drawing pipeline provided in a stage, a control line of processing contents corresponding to each processing unit of the n stages is collectively received together with the second information obtained from a higher-level device and supplied to the drawing pipeline. It can be achieved by an information processing method including a second step.

According to the first and second aspects of the present invention, the function of each processing unit can be changed without stopping the operation of the drawing pipeline. According to the third to fifth aspects of the present invention, it is possible to operate the drawing pipeline without causing inconsistency in the generated image information even for information related to overlapping images.

According to the present invention, the drawing pipeline can be operated at high speed by using a high-speed memory such as a cyclonic memory. According to the thirteenth aspect, the function of each processing unit can be changed without stopping the operation of the drawing pipeline.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
Various embodiments will be described as examples.

[0022]

FIG. 2 is a block diagram showing a first embodiment of the information processing apparatus according to the present invention. The information processing system 11 to which the present embodiment is applied converts three-dimensional image data into data that can be displayed on a display unit 17 such as a display, and outputs the data. The information processing system 11 supplies three-dimensional image data and operates as a host system. The information processing apparatus 13 processes data supplied from the host computer 12 and develops the data into image data to be drawn. , A frame memory 14 for storing image data developed by the information processing apparatus 13, an information processing apparatus 13
A local memory 15 for storing a processing program for 3D image data and three-dimensional image data to be displayed, a texture memory 16 for storing texture data for attaching a pattern to the surface of a display body, and a frame memory 14 Display unit 1 for reading and displaying two-dimensional image data
7.

The host computer 12 decomposes the three-dimensional image data into graphic elements, performs geometric transformation, and supplies the data to the information processing apparatus 13 as data in a packet format. The information processing device 13 executes a predetermined process on the three-dimensional image data supplied from the host computer 12, creates image data to be drawn, and develops the image data on the frame memory 14. Information processing device 13
Corresponds to a first information processing means in the claims, and is a graphic dedicated hardware unit 18 for processing supplied image data by dedicated hardware set in advance therein;
A microprogram (μP) execution unit 19 that operates in parallel with the graphics-dedicated hardware unit 18 and executes processing according to the program, a graphics-dedicated hardware unit 18, A frame memory control unit 20 that controls writing and reading of image data to and from the frame memory 14 in accordance with an instruction from the microprogram execution unit 19, and writing and reading of a microprogram and processed image data to and from the local memory 15. It is composed of a local memory control unit 21 that performs control, and a texture memory control unit 22 that controls writing and reading of texture data to and from the texture memory 16.

The frame memory 14 has a VRAM (Video Random Access Memory) corresponding to a third information storage means.
), And stores the R, G, B color data and α value in 8 bits each. The local memory 15 is composed of an SDRAM or the like corresponding to the first information storage means, and stores drawing data and user data such as microprograms, R, G, and B color data, α values for blending, and Z values for depth. .

The texture memory 16 is composed of SDRAM, SRAM, PROM and the like corresponding to the second information storage means, and stores texture data composed of R, G, B color data and α value. In the texture memory 16,
Since data is managed in page units for each pattern of the texture data, and data may be referred to for each page, access to the texture memory 16 can be performed at high speed.

The graphics-specific hardware unit 18
A dedicated hardware unit for performing three-dimensional graphics drawing, a linear interpolation operation (DDA) unit 23 for performing a process of interpolating each pixel constituting the inside of a figure (polygon) constituting three-dimensional graphics; Interpolator 2
A texture processing unit 24 that executes a process of setting the pattern of the portion interpolated in step 3 based on the data in the texture memory 16, and determines whether or not to draw the pixel based on the data in units of pixel. A condition determination unit 25 and a blender unit 26 that mixes a color value of a pixel to be drawn with a color value of a pixel already drawn under the pixel are set, and necessary parameters are set and activated. Thus, the processing is performed independently of the microprogram execution unit 19.

The linear interpolation calculator 23 calculates the coordinates (X, Y, Z) of the pixel at the interpolation start point, the colors (R, G, B, α),
Texture coordinates (S, T, Q), depth skew value (D), increment value (ΔX, ΔY,
ΔZ, ΔR, ΔG, ΔB, ΔA, ΔS, ΔT, ΔQ, Δ
D) and the number of interpolation operations. The linear interpolation calculation unit 23 adds the increment value to the initial value by the set number of interpolation calculations and outputs the result as an interpolation value.

The microprogram execution unit 19 analyzes packet data supplied from the host computer 12 and controls access to the frame memory 14, the local memory 15 and the texture memory 16 connected to the information processing apparatus 13. A host interface (I / F) unit 27 for performing the control, an execution control unit 28 for controlling the entire information processing apparatus 13 according to a program stored in the local memory 15, and an execution control unit 28 corresponding to a processing information storage unit in claims. An instruction cache 29 for temporarily storing an instruction block interpreted and executed by the CPU, a main operation unit 30 corresponding to a first operation unit in the claims, and executing various operations in accordance with an instruction from an execution control unit 28; A sub-operation that executes various operations in parallel with the main operation unit 30 according to the instruction from 28 31, In the claims, the shared corresponds to the storage means, reading data in parallel to the main calculating section 30 and the sub calculation section 31, composed of a writable shared registers 32, and the shared memory 33.

The host interface unit 27 has a buffer (not shown) for temporarily storing polygon data to be drawn, and data is sequentially read from the host interface unit 27. The main operation unit 30 has a program execution control function, and the sub operation unit 31 has a function of controlling the graphic dedicated hardware unit 18. The main and sub arithmetic units 30 and 31 are configured to operate synchronously with parallel instruction codes.

The microprogram execution section 19 controls RISC corresponding to various processes by combining basic instructions in order to control the processes by the microprogram.
It is configured to correspond to a type instruction set. The frame memory control unit 20 includes a frame memory 14, a graphics dedicated hardware unit 18, and a microprogram execution unit 1.
9 in response to requests from the graphics dedicated hardware unit 18 and the microprogram execution unit 19.
8. It controls writing of image data from the microprogram execution unit 19 to the frame memory 14 and reading of image data from the frame memory 14 to the graphic dedicated hardware unit 18 and the microprogram execution unit 19.

The frame memory control unit 20 makes the access to the frame memory 14 write-only at the time of drawing a three-dimensional image, thereby improving the access speed to the frame memory 14. The local memory control unit 21 is connected to the local memory 15, the graphic dedicated hardware unit 18, and the microprogram execution unit 19, and executes the μ program from the graphic dedicated hardware unit 18, the microprogram execution unit 19 to the local memory 15, It controls writing of various data such as color data (R, G, B, α), Z value, window ID, etc., and reading of various data from the local memory 15 to the graphic dedicated hardware unit 18 and the microprogram execution unit 19.

The local memory controller 21 stores color system data (R, G, B,
In addition to (α), texture-based data such as (Z, S, T, Q, D) is copied. Therefore, the frame memory 14
It is not necessary to store the texture data in the frame memory 14, and the access speed to the frame memory 14 can be improved.
Higher processing speed has been realized.

The texture memory control unit 22 is connected to the texture memory 16, the graphics dedicated hardware unit 18 and the microprogram execution unit 19, and receives the graphics data from the texture memory 16 in response to a request from the graphics dedicated hardware unit 18 and the microprogram execution unit 19. The reading of the texture data to the dedicated hardware unit 18 and the microprogram execution unit 19 is controlled, and the writing of the texture data from the microprogram execution unit 19 to the texture memory 22 is controlled by a request from the microprogram execution unit 19.

The frame memory control unit 20, local memory control unit 21, and texture memory control unit 22 can access the frame memory 14, local memory 15, and texture memory 16 from the graphic dedicated hardware unit 18 and the microprogram execution unit 19, respectively. ,
Since there is no contention for access to the memory and there is no data waiting time in the processing, data processing can be performed efficiently.

The execution control unit 28 controls execution of an instruction fetch (F), an instruction interpretation (D), a data read (R), and an operation execution / data storage (E) in the order of a four-stage pipeline. The execution control unit 28 has a three-field instruction system for controlling the processing of the main processing unit 30, the sub-processing unit 31, and the hardware unit 17 for graphics, and is configured to be able to control each of them.

The display unit 18 displays an image based on the color system data (R, G, B, α) stored in the frame memory 14. FIG. 3 is an operation flowchart showing an overall flow at the time of information processing in the first embodiment. When performing information processing, the information processing apparatus 13 of the present embodiment first performs initialization (step S1-1).

Next, the presence or absence of an unprocessed packet is determined.
If there is an unprocessed packet, a table process corresponding to the packet is executed (steps S1-2 and S1-3). When the packet processing corresponding to the packet is completed, the data processing corresponding to the packet is executed for the next unprocessed packet (steps S1-4, S1-2, S1-3).

If there is no unprocessed packet, the process stands by until the next packet is supplied (step S1--).
2). As described above, the information processing apparatus 13 of the present embodiment receives the processing data from the host computer 12 in the form of a packet, and executes the processing for each packet. Next, a description will be given of a specific data processing drawing process of three-dimensional graphics information.

FIG. 4 is a flowchart showing the operation of the microprogram execution unit 19 during the rasterizing process in the first embodiment. First, in the microprogram executing unit 19, the coordinates (X, Y, Z) of the vertices of the polygon necessary for drawing the image from the host interface unit 27 (R,
G, B, α), texture coordinates (S, T, Q), and depth skew values (D) (X, Y, Z, R, G,
B, α, D, S, T, Q) increment values (dX, dY, dZ, dR, dG, dB, dα, dD,
dS, dT, dQ) are read (step S2-1).

Next, the end points forming the sides between the vertices of the polygon are calculated (step S2-2). At this time, as will be described later, since the sides of the polygon do not always coincide with the pixels, correction calculation of the end point is executed so that the polygon is accurately drawn. Next, the graphic dedicated hardware unit 1
It is determined whether there is an interpolation processing end notification indicating that the interpolation processing for one end point has been completed from step S8 (step S2).
-3).

Here, upon receiving the interpolation processing completion notification from the graphic dedicated hardware unit 18, the microprogram execution unit 19 provides the DDA unit 23, which is dedicated hardware for executing the linear interpolation processing of the graphic dedicated hardware unit 18. Is supplied with the (X, Y, Z, R, G, B, α, D, S, T, Q) values of the end points already calculated in step S1-2 (step S2-4).

At this time, the microprogram execution unit 19
Is not supplied from the graphics-dedicated hardware unit 18, that is, while the interpolation process is not completed in the DDA unit 23 of the graphics-dedicated hardware unit 18, the next process is not performed and a standby state is set. (Step S2-5). The processing of steps S2-2 to S2-5 is repeated until a single polygon is formed (step S2-6).

FIG. 5 shows the D of the hardware unit 18 dedicated to graphic processing at the time of rasterizing processing in the first embodiment.
5 shows an operation flowchart of the DA unit 23. First, the graphic-dedicated hardware unit 18 first calculates (X, Y, Z, R,
G, B, α, D, S, T, Q) values, the number of interpolation processes n required for interpolation of one line, and (X, Y,
Z, R, G, B, α, D, S, T, Q) value increment (d
X, dY, dZ, dR, dG, dB, dα, dD, d
(S, dT, dQ) are read (step S3-1).

Next, the graphic dedicated hardware section 18
The number of interpolation processes n read by
Repeat counter (RC) built in the hardware unit 18
(Step S3-2). Then graphic
The dedicated hardware unit 18 is the microprogram execution unit 1
(X) of the end point read from₀, Y₀, Z₀, R₀,
G₀, B₀, Α₀, D₀, S ₀, T₀, Q₀) Value DD
The texture processing unit 24 as the first data in the A unit 23
(Step (S3-3)).

Next, the graphic dedicated hardware unit 1
8 in the DDA unit 23, the initial value (X ₀, Y₀, Z₀, R
₀, G₀, B₀, Α₀, D₀, S₀, T₀, Q₀)
The increment value (dX (= 1), d read in step S2-1)
Y (= 0), dZ, dR, dG, dB, dα, dD, d
S, dT, dQ) (X₀+1, Y₀, Z ₀
+ DZ, R₀+ DR, G₀+ DG, B₀+ DB, α₀+
dα, D₀+ DD, S ₀+ DS, T₀+ DT, Q₀+ D
Q) is set as the value of the current pixel (step S3-4).

Next, the pixel value (X ₀ +1,
Y ₀ , Z ₀ + dZ, R ₀ + dR, G ₀ + dG, B ₀ + d
B, α ₀ + dα, D ₀ + dD, S ₀ + dS, T ₀ + d
T, Q ₀ + dQ) is supplied to the texture processing unit 24, the repeat counter RC is started, and 1 is subtracted from the set number of times of interpolation processing n to set the number of times of interpolation processing to (n-1) (step ( S3-5).

Next, the graphic dedicated hardware unit 18
Is the previous pixel value (Xn _-1 , Yn _-1 , Zn _-1 , Rn _-1 , G
n _-1 , Bn _-1 , αn _-1 , Dn _-1 , Sn _-1 , Tn _-1 , Qn
₋₁ ) to the increment value (1, 0, dZ, dR, dG, dB, d
α, dD, dS, dT, and dQ) are added to obtain the current pixel value, which is supplied to the texture processing unit 24, and subtracts 1 from the number of interpolation processes (step S3-6).

The above steps S3-5 and S3-6 are repeated until the value of the repeat counter RC becomes "0". When the value of the repeat counter RC becomes "0", a notice of the completion of the interpolation processing is sent to the microprogram execution unit. 19 is notified (steps S3-7, S3-8). As described above, the interpolation of the data inside the polygon can be executed only by repeating the predetermined interpolation process from the end point a predetermined number of times. For this reason, the processing for interpolation is simplified, and can be realized by simple pipeline processing.

FIGS. 6 to 9 are explanatory diagrams of the operation during the rasterizing process in the first embodiment. FIG. 6 is a diagram for explaining data provided at the time of drawing a triangular polygon and a processing procedure. Figure 6 when drawing a triangular polygon
As shown in the figure, the pixel values (xs, ys,
rs, gs, bs, αs, zs, ss, ts, qs),
(Xa, ya, ra, ga, ba, za, sa, ta,
qa) and incremental values (dxDv, drDv, dgDv, dαDv, dzD) in the direction of arrow A from vertex s to vertex a.
v, dsDv, dtDv, dqDv), the increment value (dxDv ₂ , dr) in the direction of arrow B from the vertex a to the remaining vertex b
Dv ₂ , dgDv ₂ , dbDv ₂ , dzDv ₂ , dsD
v ₂ , dtDv ₂ , dqDv ₂ ) and the increment value (dxDu, drD) of the value in the direction of the arrow C (the direction of the arrow y) from the end point determined from the pixel of the vertex s, a and the increment value of the direction of the arrow A.
u, dgDu, dbDu, daDu, dzDu, dsD
u, dtDu, dqDu), and are rendered by interpolating pixels based on these values.

First, the microprogram execution unit 19 calculates an end point from the vertex s to the vertex a (in the direction of the arrow A) from the pixel value of the vertex s and the increment value thereof. The pixel value inside the polygon is determined from the pixel value at one end point calculated by the microprogram execution unit 19 and the increment value in the arrow C direction by the DDA unit 23.

After calculating the full score from the vertex S to the vertex a, the microprogram execution unit 19 calculates the vertex a
From the vertex a to the vertex b from the pixel value of
The endpoints up to are calculated, and each time the one-end point is calculated, the DDA unit 23 of the graphic-dedicated hardware unit 18 obtains the pixel value inside the polygon subjected to the interpolation processing from the pixel value of the endpoint and the increment value in the direction of arrow C. .

FIG. 7 is a diagram for explaining the operation of the end point calculation processing and the interpolation processing. If it is requested to draw a side corresponding to the coordinates indicated by the solid line in FIG. 7, the vertex data and the pixel data do not match. In such a case, correction is necessary so that pixels inside the side are drawn. The calculation of such correction is executed by the microprogram execution unit 19 when calculating the end points.

The calculation formula of the end point is shown below. The vertex s
Pixel coordinates Xa and Xvb including the X coordinate (Sx) are obtained. xa (0) = xs xb (0) = xe At this time, it is assumed that Xa (0) and Xb (0) are not drawn since they are located outside the polygon. The value of the next end point of the vertex s is obtained as follows.

First, the y coordinate is set to ys (n) = ys (n-1) +1, and is sequentially increased so as to have a value at a position where a pixel exists. Further, the X coordinate end value is obtained by xb (n) = xb (n-1) + dxeDv according to the increment of the X coordinate, and the X coordinate of the start point is sequentially incremented, and xa (n) = xa ( Similarly, the increment value is sequentially added to other values below n (1) + dxDv, and ra (n) = ra (n-1) + drDv ga (n) = ga (n-1) + dgDv ba (n) = ba ( n-1) + dbDv aa (n) = aa (n-1) + daDv za (n) = za (n-1) + dzDv sa (n) = sa (n-1) + dsDv ta (n) = ta (n- 1) + dtDv It is obtained by qa (n) = qa (n-1) + dqDv.

The value of the pixel to be interpolated is calculated according to the following equation based on the value of the correction end point calculated by the above equation. First, the values (initial values) of the end points are xu (n) (0) = xa (n) ru (n) (0) = ra (n) gu (n) (0) = ga (n) bu (n) (0) = ba (n) au (n) (0) = aa (n) zu (n) (0) = za (n) su (n) (0) = sa (n) tu (n) (0 ) = Ta (n) qu (n) (0) = qa (n) The value of the interpolation point following the initial value is xu (n) (m) = xa (n) (m-1) +1 ru (n) (m) = ra (n) (m-1) + duDr gu (n) (M) = ga (n) (m-1) + duDg bu (n) (m) = ba (n) (m-1) + duDb au (n) (m) = aa (n) (m-1) + duDa zu (n) (m) = za (n) (m-1) + DuDzsu (n) (m) = sa (n) (m-1) + duDstu (n) (m) = ta (n) (m -1) + duDt qu (n) (m) = qa (n) (m-1) + duDq At this time, xu (n) (m)
<Xb (n) pixels are drawn.

FIG. 8 is a timing chart of the DDA process during the rasterizing process. When the correction calculation of the first end point is performed at time T ₀ by the microprogram execution unit 19, the pixel value of the first end point is supplied to the graphic dedicated hardware unit 18 at the time t ₀ at which the calculation is completed, and the microprogram execution unit The pixel value to be interpolated at time T ₁ ′ from time t ₀ is calculated based on the pixel value of the end point supplied from 19. After supplying the pixel value of the first end point to the graphic dedicated hardware unit 18, the microprogram execution unit 19 performs correction calculation of the next end point from time t ₀ . In this case, when completing the calculations in microprogram execution unit 19 at time t ₁ microprogram execution unit 19 waits until the interpolation processing graphics dedicated hardware 18 is completed, the processing of the graphics dedicated hardware portion 18 terminates and supplies the pixel values of the end point which has been calculated at time t ₀ ~t ₁ time T ₁ at time t ₂ when the interpolation processing end notification is supplied to the graphics dedicated hardware portion 18.

Hereinafter, similarly, the microprogram execution unit 1
While the pixel value to be interpolated is calculated by the graphic dedicated hardware unit 18 based on the pixel value of the end point previously calculated in 9, the graphic dedicated hardware unit 1 is executed in the next process.
The pixel value of the end point used in 8 is calculated by the microprogram execution unit 19. FIG. 9 is a diagram illustrating a data flow of the first embodiment. The data in the packet format from the host computer 12 which has just been subjected to the geometric conversion is transmitted to the host I / F.
The packet analysis processing is performed by the unit 27, the correction calculation of the end point is performed by the microprogram execution unit 19, and the DDA unit 2
In step 3, the correction end point is calculated, and the interpolation calculation is performed.

After the interpolated pixel data is subjected to texture processing by the texture processing unit 24 by the pipeline processing by the texture processing unit 24 and the drawing condition determination unit 25 determines the drawing condition such as the Z value comparison process, and then blended by the blender unit 26, all the processed pixel values (X, Y, Z, R, G, B, α, D, S, T,
Q) is stored in the local memory 15 and only the color data (R, G, B, α) among the pixel values is stored in the frame memory 1.
4 is stored in a storage portion corresponding to the coordinates (X, Y).

As described above, the microprogram execution unit 1
The image drawing can be efficiently executed by performing the endpoint calculation and the interpolation processing while operating the hardware unit 9 and the graphic dedicated hardware unit 18 in parallel. In this embodiment, the example in which the microprogram execution unit 19 executes the correction calculation of the end point has been described. However, the present invention is not limited to this. Support for multimedia is easy.

FIG. 10 is a flowchart showing an operation of accessing the shared register of the main / sub arithmetic unit in the first embodiment. In the access control to the shared register 32, when an access request occurs, it is determined whether the request is a write request or a read request (steps S4-1 and S4-2). If a request is issued from the main / sub operation units 30 and 31 at the same time when a write request is issued, the data from the main operation unit 29 is transferred to the shared register 3.
2 and the data from the sub-operation unit 31 is ignored (steps S4-3, S4-4).

When there is a write request only from the main processing unit 30, the data from the main processing unit 30 is stored.
1 is written into the shared register 32 (steps S4-5, S4-4, S4-6). When a read request is issued, if the request is issued from the main / sub-operation units 30 and 31 at the same time, the data written in the shared register 32 is supplied to both the main / sub-operation units 30 and 31 at the same time. Occurs, the data of the shared register 32 is supplied to the requestor (step S4-7,
S4-11).

FIG. 11 is a diagram for explaining the shared memory 32 of the first embodiment. FIG. 11A shows the shared memory 3
3, FIG. 11B shows the distribution of data in the shared memory 33, FIG. 11C shows the read timing of the shared memory 33, and FIG. 11D shows the write timing of the shared memory. The shared memory 33 is connected to the main bus MB, and writes a data to be processed via the main bus MS.
And a sub-bus memory unit 33b for writing data to be processed via the sub-bus SB.

The main bus system memory unit 33a and the sub bus system memory unit 33b are composed of, for example, memories 33a-1, 33b-1, and 33a- each composed of 40 bits and 128 words.
Address decoder 33a-
2, 33b-2, address decoders 33a-2, 33b
The gate units 33a-3 and 33b-3 switch and output data read from the memory 33a-1 or the memory 33b-1 in response to the control signal from the memory -2.

Address decoders 33a-2 and 33b-2
Are supplied with actuators from the main bus MB and the sub-bus SB. The address decoder 33a-2 receives a main bus write control signal WEA, and the address decoder 33b-2 outputs a sub bus write control signal WE.
B is supplied, the address decoder 33a-1 controls only the writing of data from the main bus MB, and the address decoder 33b-1 controls only the writing of data from the sub-bus SB.

For example, if addresses 00H to FFH (hexadecimal notation) are set as all addresses of the shared memory 33, 00H to 7FH are allocated to the memory 33b-1 as shown in FIG. -1 are assigned addresses 80H to FFH, and the memory 33a-1
Is supplied with write data from the main bus MB, the memory 33b-1 is supplied with write data from the sub-bus SB, and the read data is supplied to the gates 33a-3 and 33b-3.
Are supplied to the main bus MB and the sub-bus SB via

At this time, data is written and read at the timings shown in FIGS. 11 (C) and 11 (D). The gates 33a-3 and 33b-3 are supplied with output switching signals from the address decoders 33a-2 and 33b-2. The address decoders 33a-2 and 33b-2 output the gate data of the other memory when the address is not the address managed by itself.
-3, 33b-3.

As described above, the memory 33a can be written only from the main bus MB system.
b can be written only from the sub-bus SB system, and data can be read from the memories 33a and 33b simultaneously from both the main bus MB and the sub-bus SB. Therefore, data can be written without competing between data writing from the main bus MB and data writing from the sub-bus SB, and reading can be performed simultaneously from the memories 33a and 33b. Access conflicts are eliminated, and data processing in the main processing unit 30 and the sub-processing unit 31 can be performed efficiently.

The shared memory 33 can access the area corresponding to any of the main and sub operation units 30 and 31 at the time of reading data. The data calculated by the unit 31 can be supplied to the main calculation unit 30. Therefore, data processing can be performed while sharing the data between the main processing unit 30 and the sub-processing unit 31, so that efficient data processing can be performed.

FIG. 12 is a flowchart showing the operation of the microprogram execution unit 19 when executing a program in the first embodiment. First, in the microprogram execution section 19, the program counter PC is reset (step S5-1). Next, if there is an instruction in the instruction cache 29, the instruction of no instruction cache 29 is executed and the PC is updated (steps S5-2 to S5-4).

When there are no more instructions in the instruction cache 29, the pipeline is stopped and made to wait, and the instructions are read from the local memory 15 (step S5-5). By holding the program in the instruction cache 29,
There is no need to access the local memory 15 for each instruction to read out the program. Therefore, when the program is executed, there is a conflict between the reading of the μ program and the access to the local memory 15 from the graphic dedicated hardware unit 18. And can efficiently execute data processing.

FIG. 13 is a block diagram of the execution control unit 28 according to the first embodiment. The execution control unit 28 corresponds to an execution control unit, and the main operation control unit 28- corresponds to a first execution control unit.
1. a sub-operation control unit 28- corresponding to a second execution control unit;
2. Operation of graphic dedicated hardware control unit 28-3 corresponding to third execution control means, fetch control unit 28-4 for controlling fetching of instructions from instruction cache 29, and graphic dedicated hardware control unit 28-3 Is controlled by a pipeline control unit 28-5.

The main operation unit 28-1 and the sub-operation unit 28-2 are control pipeline units 28-11,.
28-21, decoding units 28-12 and 28-22 for decoding instruction codes from the instruction cache 29, and data pipelines 28-12 and 28 for controlling data flow.
−22, data access control units 28-13 and 28− that control access to the shared register 32 and the shared memory 33.
23, a data actuator generating unit 28-14, 28-24 for generating a data address, and a pipeline stop request for controlling access competition according to the data address generated by the data address generating unit 28-15, 28-25. Access contention control units 28-16, 2 for generating signals
8-26, operation control units 28-17 and 28-27 for performing operation control according to the instruction code, and extended operation control units 28-18 and 28-28 for controlling the flow of data during the extended operation. Further, the graphic dedicated hardware control unit 28-3 includes a control pipeline 28-31.

Main operation control unit 28-1, sub operation control unit 28
-2, the graphic dedicated hardware control unit 28-3 issues an instruction in accordance with a signal from the pipeline control unit 28-5,
And controls the data flow so that the operations are performed in synchronism as a whole. The pipeline control unit 28-5 includes a fetch control unit 28-4, an access contention control unit 28-16,
In response to the pipeline stop request (pipeline extension request) generated from the extended operation control units 28-18 and 28-28, the request from each unit is arbitrated and until all the extension requests are released. A latch control signal is supplied to the control pipeline unit 28-11 to stop the pipeline.

The stop request generated by the fetch control unit 28-4 is generated when a required program is not in the cache memory and a read operation is started from the external memory (so-called cache miss bit). The stop request generated by the access contention control units 28-16 and 28-26 is generated when the time for executing the access to the external memory is extended, or when the memory read and the write are simultaneously performed in the R and E stages.

A stop request generated by the extended operation control units 28-18 and 28-28 is generated when an instruction such as a conditional load instruction, a store instruction, or a multiplication instruction that cannot be completed in one cycle is executed. Occur. FIG. 14 is a diagram for explaining the operation of the pipeline control unit 28-5. FIG. 14 shows FIG.
3 is divided into locks by function. The fetch control unit 28-4 of FIG. 13 includes a fetch stage 28a, decode units 28-14, 28-24, and a data address generation unit 28-15. , 28-25 are the decoding stage 28b and the access contention control units 28-16, 18-
26, the data access control units 28-13 and 28-23 are read stage 28c, and the operation control units 28-17 and 28-
27, extended operation control units 28-18, 28-28, main operation unit 30, sub operation unit 31 is execution stage 28d, and control pipeline 28-11 is each stage 28a, 28b, 28.
c, a control pipeline 28e, 2 provided between 28d
8f, 28g, 28h.

The fetch stage 28a reads one instruction from an address indicated by a PC (program counter). The decode stage 28b performs instruction resolution and data access address generation. Lead stage 2
8c reads data from a register, a memory or the like.

The execution stage 28d includes an operation and a register,
Write data to a memory or the like. A control pipeline 28e composed of a transparent latch is provided between the fetch stage 28a and the decode stage 28b.
Control pipeline 28 consisting of D and flip-flops
f, an instruction fetched in the fetch stage 28a is latched by a latch control signal (Latch EN) from the pipeline control unit 28-5, and a pipeline stop request (Pipe- L
(ine Stop), the instruction supplied to the decode stage 28b is held in the previous state.

Control pipelines 28f and 28h composed of D flip-flops are arranged between the decode stage 28b and the REIT stage 28c and between the read stage 28c and the execution stage 28d. Pipeline stop request (Pipe-Line St
op), the read stage 28c and the execution stage 28
Hold the instruction supplied to d in its previous state.

FIG. 15 is a state transition diagram of the execution control unit 28, and FIGS. 16 to 19 are explanatory diagrams of the operation of the execution control unit 28. In FIG. 15, S0 to S5 indicate different functions,
(0, 0), (0, 1) (1, 0), (1, 1) indicate that P of (P, Q) is 0 or 1, and Q is 0 or 1, If P is 0, no cache miss has occurred. If 1, P indicates a cache miss occurred. If Q is 0, no event has occurred. If 1 is 1, an event has occurred. Indicates the status. AS indicates a state in which the latch control signal (Latch EN) is asserted.

The state SD is (P, Q) = (0, 0), the state S1 is (P, Q) = (0, 0) → (0, 1), and the state S2 is (P, Q). ) = (0,1) → (1,1)
The state S3 is (P, Q) = (1, 1) → (1,
0), the state S4 is (P, Q) = (0, 0) →
The state of (1,1) and state S5 are (P, Q) = (1,1)
→ Indicates the state of (0, 1).

FIG. 16A shows a case where only an extension request other than a cache miss has occurred, that is, (P, Q) = (0,
A case where the state transits to the state of 1) (state S0 → S1)
In this case, the inverted latch control signal (Latch EN) becomes low level, the control pipeline 28e is stopped, and A
S state and inversion pipeline stop request (inversion Pi
pe-Line Stop) goes low to stop the control pipelines 28f, 28g, 28h.

FIG. 16B shows a case where there is an extension request due to the occurrence of a cache miss, that is, (P, Q) = (1, 0).
In this case, the inverted pipeline stop request (inverted Pipe-Line Stop) becomes low level, and the control pipelines 28f, 28g, and 28h are stopped. FIG. 17A shows a case where another extension request is issued one cycle before the occurrence of a cache miss and then the cache miss is released, that is, (P, Q) = (0, 1) → (1, 1).
→ (0, 1) A state where a transition is made from state S1 → S2 → S1 is shown. In this case, the same state as state S1 is maintained. That is, the inversion pipeline stop request (inversion Pipe-Line Sto
p) is set low, the inverted latch control signal (Latch EN) is set low, and all the control pipelines 28e to 28h are stopped.

FIG. 17B shows a case where another extension request is issued one cycle before the occurrence of a cache miss and the extension request is released later, that is, (P, Q) = (0, 1) → (1,
1) → (1, 0) and the transition from state S1 → S2 → S3 are performed. In this case, the state is maintained as in FIG. 17 (A). FIG. 18A shows a case where a cache miss and another extension request are generated at the same time and released at the same time.
Q) = (0,0) → (1,1) → (0,0). In this case, an inverted pipeline stop request (inverted Pipe-Line St
op) is set to low level and the control pipeline 28f
28h are stopped (0, 0), and at the same time, the inverted pipeline stop request (inverted Pipe-Line Stop) is set to the high level, and the stop of the control pipelines 28f to 28h is released.

FIG. 18B shows a case where a cache miss and another extension request occur at the same time, and the extension request is released later.
(P, Q) = (0,0) → (1,1) → (0,1) →
(0, 0). In this case, the state is maintained as in FIG. FIG.
(A) is a case where a cache miss and another extension request occur at the same time, only the cache miss is subsequently released, and then the extension request is released. That is, (P, Q) = (0, 0) →
(1,1) → (0,1) → (0,0). In this case, when (P, Q) = (1,1), the inverted pipeline stop request (Pipe-Line Stop) becomes low level. And the control pipelines 28f to 28h are stopped, and (P, Q) =
In (1,1) → (0,1), the control pipeline 28f ~
28h is stopped and the inverted latch control signal (Latc inverted)
h EN) becomes low level and the control pipeline 28e
Are latched and returned at (0,0).

FIG. 19B shows a case where another extension request is issued one cycle before the occurrence of a cache miss, and then the cache miss and the extension request are simultaneously released. Then, (P, Q) =
(0,0) → (0,1) → (1,1) → (0,0). In this case, when (P, Q) = (0,1), the inverted latch control signal (Latch EN ) And the inverted pipeline stop request (inverted Pipe-Line Stop) go low,
The control pipelines 28e to 28h are controlled to the latched state, maintain the same state even when (P, Q) = (1, 1), and return when (P, Q) = (0, 0).

As described above, the control pipeline 28
The decode stage 28b, the read stage 28c, and the execution stage 28d can be held in a standby state by f to 28h, the instruction fetched in the fetch stage 28a can be made to wait by the control pipeline 28e, and the next instruction can be fetched by the fetch stage 28a. Becomes

Therefore, the control pipelines 28e to 28e-2
8h, processing can be performed while synchronizing the processing states of the control units 28-1, # 28-2, and 28-3. For example, tertiary processing can be performed while synchronizing the processing of the microprogram execution unit 19 with the processing of the graphic hardware 18. The original graphic processing can be executed at high speed. According to this embodiment, since the graphics-specific hardware unit capable of asynchronously / parallel execution of various drawing control and memory management / control can be program-controlled, the processing method has already been determined, and it is necessary to perform processing in combination with the memory. is there. The processing is executed by the graphics-dedicated hardware unit, and the data management corresponding to various applications and the processing of audio data and other media data are executed by the microprogram execution unit in synchronization with the graphics-dedicated hardware unit. High-speed and efficient information processing can be performed.

By the way, the graphic dedicated hardware unit 18 shown in FIG.
Frame memory control unit 20, local memory control unit 21
If the illustration of the texture memory control unit 22 and the like is omitted, the configuration basically has the configuration shown in FIG. In FIG.
The same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

As described above, the local memory 15 has the SD
A memory such as a RAM that can be accessed at a high speed can be used, and the texture memory 16 can be used as the SDRAM or the SRA.
A memory that can be accessed at high speed, such as an M or PROM, can be used. However, a dual port VRAM or the like is generally used as the frame memory 14 for connection to the display unit 17. This dual-port VRAM has a read-only terminal to prevent data reading for display from interfering with data reading and writing for image generation, and has a function of batch writing of data, but the access speed is not very fast. Therefore, the entire pipeline processing is determined by the access speed of the frame memory 14.

Therefore, the SDRA is also stored in the frame memory 14.
It is conceivable to use a memory that can be accessed at high speed, such as M, but if connection with the display unit 17 is taken into consideration, compatibility with existing systems cannot be obtained, and the configuration of the display unit 17 and the like will be changed. Must be less preferred. In other words, in the configuration shown in FIG. 20, even if a memory capable of high-speed access is used for the local memory 15 and the texture memory 16, a VRAM having a relatively slow access speed is used for the frame memory 14 which has the highest access request. It is difficult to fully utilize the merit of the high-speed accessible memory used for the texture memory 16. Each memory has an access waiting time due to another factor unrelated to the flow of processing such as refreshing. Therefore, if the local memory 15
When the texture memory 16 is in an access waiting state even when the texture memory 16 is accessible, the operation of the drawing condition determination unit 25 waits until the operation of the texture processing unit 24 is completed. As described above, the entire pipeline processing is disturbed by the access waiting time generated for each memory.

An embodiment that can further speed up the entire pipeline processing by fully utilizing the merit of the memory that can be accessed at high speed while maintaining compatibility with the existing system will be described below. FIG. 21 is a block diagram showing a schematic configuration of a main part of a second embodiment of the information processing apparatus according to the present invention. 2, the same parts as those of FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 21, the display unit 17
The illustration of the display control unit for controlling the operation, the microprogram execution unit 19, the frame memory control unit 20, the local memory control unit 21, the texture memory control unit 22, and the like shown in FIG. In the present embodiment, the texture processing unit 24
And the drawing condition determination unit 25 performs processing in parallel.

The graphic-specific hardware unit 18 shown in FIG. 21 is connected to the D
DA units 23-1, 23-2, texture processing unit 24,
It comprises a drawing condition determination unit 25, buffers 51-1 and 51-2, and a blender unit 26. DDA units 23-1, 23-
2 are control units 23-1a, 23-
2a. The texture processing unit 24 includes a control unit 24a for controlling the texture processing unit, and the drawing condition determination unit 25 includes a control unit 25a for controlling the drawing unit. Buffers 51-1 and 51-2
Are control units 51-1a and 51-2 for controlling these, respectively.
a. Further, the blender unit 26 includes a control unit 26a for controlling the blender. The frame memory 14 includes a control unit 14a for controlling this.

The polygon is, as shown in FIG.
It is approximately represented by seven pixels. The host computer 12, which is a higher-level device, calculates the starting point and the amount of change of the pixel to be drawn in the horizontal direction among the pixels shown in FIG. The DDA units 23-1 and 23-2 calculate values to be drawn on individual pixels based on information from the host computer 12, respectively.
4. The drawing condition determination unit 25 and the blender unit 26 perform the processing described below for each pixel.

The texture memory 16 stores color data prepared for attaching a pattern or the like to a polygon and texture data composed of α values. Frame memory 14
Stores color data of a polygon to be displayed by the display unit 17. The local memory 15 stores drawing data and user data such as microprograms, color data, α values, and Z values related to depth. Note that the frame memory 14,
It goes without saying that at least two of the local memory 15 and the texture memory 16 may be constituted by a single memory device.

The texture processing section 24 reads the texture data from the texture memory 16 and pastes the pattern on the pixel. Drawing condition determination unit 2
5 determines whether to read depth data or the like from the local memory 15 and draw a pixel. Also, the blender unit 26 reads the depth data and the like of the already drawn pixels from the local memory 15 for the pixels to be drawn and blends (mixes) them with the color data to be drawn. Find the data to be written to

In this embodiment, the same color data and α values as those stored in the frame memory 14 shown in FIG. Also, only writing is performed from the graphic dedicated hardware unit 18 to the frame memory 14, so that the color data and the α value read from the frame memory 14 in the first embodiment of FIG. Read from the local memory 15.
That is, reading from the frame memory 14 is performed only from the display unit 17. Since the local memory 15 is not directly connected to the display unit 17, a memory that can be accessed at a high speed such as an SDRAM can be used as the local memory 15. Thereby, the dual port VR is stored in the frame memory 14 as in the first embodiment of FIG.
Even if the AM is used, the access frequency to the frame memory 15 is about half that of the first embodiment, and the processing efficiency of the entire system can be improved.

Further, the processing of the drawing condition determination unit 25 accessing the local memory 15 and the processing of the texture processing unit 24 accessing the texture memory 16 are performed in parallel with each other. Therefore, the drawing condition determination unit 25 can operate at the optimal timing for the local memory 15, and the texture processing unit 24 can operate at the optimal timing for the texture memory 16.

In the blender unit 26, the drawing condition determination unit 25
And the processing results of both the texture processing unit 24 and the drawing condition determination unit 25 and the texture processing unit 2 are integrated.
The blending process cannot proceed unless both processing results of Step 4 are received. On the other hand, the processing of the drawing condition determination unit 25 and the texture processing unit 24 is performed asynchronously with the processing of the entire system.
51-2 is provided between the blender unit 26, the drawing condition determination unit 25, and the texture processing unit 24.

The buffer 51-1 is provided in the drawing condition determination section 25.
The processing result of is temporarily stored. As a result, even when the processing of the blender unit 26 is stopped and the blender unit 26 cannot receive data, the buffer 51-1 temporarily stores data to be received by the blender unit 26.
The drawing condition determination unit 25 can proceed with the processing of the next data. Similarly, the buffer 51-2 temporarily holds the processing result of the texture processing unit 24. As a result, the processing of the blender unit 26 is stopped and the blender unit 26 is stopped.
Buffer 51 cannot receive data.
-2 temporarily holds the data to be received by the blender unit 26, so that the texture processing unit 24 can proceed with the processing of the next data. Buffers 51-1,
If the 51-2 is configured to hold, for example, data for a plurality of pixels, the process can proceed in advance for a plurality of pixels regardless of the state of the blender unit 26. As a result, efficient arbitration is performed, in which the rendering condition determination unit 25 and the texture processing unit 24 proceed with processing asynchronously with each other while synchronizing for the data to be processed without contradiction in the blender unit 26. .

Next, the processing sequence of the graphic dedicated hardware unit 18 shown in FIG. 20 and the graphic dedicated hardware unit 18 shown in FIG. 21 will be described with reference to FIG. 23 and FIG. FIG. 23 is a diagram showing a processing sequence of the graphic-dedicated hardware unit 18 shown in FIG. 20, and FIG. 24 is a diagram showing a processing sequence of the graphic-dedicated hardware unit 18 shown in FIG.

In FIG. 23, "DDA" indicates processing by the DDA unit 23, "texture memory read" indicates reading processing from the texture memory 16, and "texture processing".
Is a process by the texture processing unit 24, "local memory read" is a process of reading from the local memory 18,
"Drawing condition determination" indicates processing by the drawing condition determination unit 25, "frame memory read" indicates processing for reading from the frame memory 14, and "blend processing" indicates processing by the blender unit 26. The numbers "1", "2",. . . Indicates the correspondence between the processes. That is, for example, the process of “texture memory read 1” is performed on the process of “DDA 1”, and the process of “texture process 1” is
This is performed for the process of “texture memory read 1”.

As can be seen from FIG. 23, the frequency of access to the frame memory 14 in this case is relatively high.
For example, the process of “frame memory write 1”
Since the process of “frame memory read 2” by the same frame memory 14 is being executed, the process waits until the process of “frame memory read 2” is completed. For the same reason, for example, "frame memory read
The process "3" is in a standby state until the process "frame memory write 1" is completed because the process "frame memory write 1" by the same frame memory 14 is being executed. In FIG. 23, the read processing and the write processing of the frame memory 14 are illustrated as requiring about twice as much time as other processing. Often.

In FIG. 24, the same parts as those in FIG. 23 are denoted by the same reference numerals. “DDA1” is the DDA unit 23 shown in FIG.
−1, and “DDA2” is the D
The processing by the DA unit 23-2 is shown. In the case of FIG. 24, the processing sequence is roughly divided into three flows. That is, there is a flow of processing related to the texture processing unit 24, a flow of processing related to the drawing condition determination unit 25, and a flow of processing related to the blender unit 26.

As can be seen by comparing FIG. 24 with FIG. 23, in the case of FIG. 24, the entire pipeline itself is short,
Since there is no read processing to the frame memory 14 from the graphic dedicated hardware unit 18 and only write processing, the processing efficiency is improved as compared with the case of FIG. Further, since the write processing to the frame memory 14 can be performed immediately without being hindered by the read processing from the frame memory 14, the disturbance of the pipeline is small. Furthermore,
Since only the write processing is performed on the frame memory 14 from the graphic dedicated hardware unit 18, it is possible to select a more efficient access method for the frame memory 14.

FIG. 25 is a diagram showing a processing sequence of the graphic dedicated hardware unit 18 shown in FIG. 20 when an access stop factor due to refresh or the like occurs. FIG. 26 shows an access stop factor due to refresh or the like. FIG. 22 is a diagram illustrating a processing sequence of the graphic-specific hardware unit 18 illustrated in FIG. 21 in the case. FIG.
26, the same parts as those in FIGS. 23 and 24 are denoted by the same reference numerals, and the description thereof will be omitted.

In the case of FIG. 25, the refresh of the texture memory 16 is started after the first "texture memory read 1", so that the texture processing for the pixels thereafter is stopped. For this reason, although the local memory 15 is accessible, access to the texture memory 16 is not performed after the first “local memory read 1”. After that, the refresh of the texture memory 16 is completed and the texture processing is restarted. However, since the refresh of the local memory 15 is started this time, the pipeline is similarly stopped.

On the other hand, in the case of FIG. 26, the texture processing is stopped by the refresh of the texture memory 16 and even if the whole processing after the “blend processing 1” is stopped, the texture processing is not related to the local memory 15. The processing has been continued. Processing results up to the drawing condition determination unit 25 are stored in the buffers 51-1 and 51-2. Thereafter, when the refresh of the texture memory 16 is completed and the processing of the texture processing unit 24 is restarted, the refresh of the local memory 15 is started. As described above, even if the refresh of the local memory 15 is started and the processing of the drawing condition determination unit 25 is stopped, the pixels which have been processed earlier are stored in the buffer 51-.
1, 51-2, so that the blender unit 26 can proceed with the blending process as it is.

The refresh is not always performed as shown in FIGS. 25 and 26. In the case of FIG. 20, the operation of the pipeline is greatly affected by the operation stop factor such as refresh. In the case of FIG. 21, it can be seen that the pipeline operation is not so affected by the operation stop factors such as refresh. Next, the control units 23-1a, 23-2a, 24 other than the control unit 26a of the blender unit 26
The operations of a, 25a, 51-1a, 51-2a, and 14a will be described with reference to FIGS. FIG. 27 shows the control unit 26.
FIG. 28 is a diagram showing input / output of a control unit other than the control unit a.
8 is a flowchart for explaining the operation of the control unit shown in FIG.

The control units 23-1a, 23-2a, 24a,
25a, 51-1a, 51-2a, and 14a have the same configuration. For convenience, the control unit 25a of the drawing condition determination unit 25 will be described with reference to FIGS. 27 and 28 for convenience. -1a, 23-2a, 24a, 51
Illustration and description of -1a, 51-2a, and 14a are omitted.

In FIG. 27, the control unit 25a is supplied with a write request U-WE from the DDA unit 23-1, which is the preceding block, and a writable response LRDY from the buffer 51-1, which is the subsequent block. . Also, the control unit 25a sends a DDA unit 23-
1 and a write request L-WE to the buffer 51-1 which is a subsequent block are output. That is, the control unit 25a controls the control information U-WE, L
RDY, L-WE, and URDY are input and output to the preceding and subsequent blocks, and the main body of the drawing condition determination unit 25 performs processing on the image information.

The control section 25a performs a process as shown in FIG. In FIG. 28, a step S11 decides whether or not data is held therein. If the decision result in the step S11 is YES, in the step S12 the writing to the subsequent block is performed based on the write enable response LRDY from the subsequent block. It is determined whether or not it is possible. If the decision result in the step S11 is NO, or the decision result in the step S12 is YE
In the case of S, in step S13, a write request L-WE is output to the subsequent block to request writing, and a write enable response URDY is sent to the previous block.
Is output to allow writing. A step S14 decides whether or not there is a write request U-WE from the preceding block. If the decision result is YES, the data from the preceding block is taken into the control unit 25a in a step S15, and the data of the preceding block is read. / URDY is output to disable writing. On the other hand, if the decision result in the step S12 is NO, a write request L-WE is output to a subsequent block in a step S16, and / URDY to disable writing is output to a preceding block. If the determination result of step S14 is NO and step S
After 15 or S16, the process returns to step S11.

Next, the operation of the control unit 26a of the blender unit 26 will be described with reference to FIGS. FIG. 29 is a diagram showing input / output of the control unit 26a, and FIG. 30 is a flowchart for explaining the operation of the control unit 26a shown in FIG. FIG.
In FIG. 9, the control unit 26a includes a write request D-WE from the drawing condition determination unit 25 which is a preceding block, a write request T-WE from the texture processing unit 24 which is a preceding block, and a local request which is a subsequent block. A writable response LRDY from the memory 15 and a writable response FRDY from the frame memory 14, which is a subsequent block, are supplied. Also, the control unit 26a sends a write enable response DRDY to the drawing condition determination unit 25, which is the preceding block, a write enabled response TRDY to the texture processing unit 24, which is the previous block, and the local memory 15 which is a subsequent block. Write request L-WE,
Then, a write request F-WE to the frame memory 14, which is a subsequent block, is output. That is, the control unit 26a
Are control information D-WE, T-WE, LRDY, FRDY,
DRDY, TRDY, L-WE, and F-WE are input / output to the preceding and subsequent blocks, and the main body of the blender unit 26 processes the image information.

The control section 26a performs a process as shown in FIG. In FIG. 30, in step S21, it is determined whether or not the blending process is completed, and data is held therein. If the determination result is YES, writing to the local memory 15 and the frame memory 14 is possible in step S22. WRDY, FR
The determination is made based on DY. If the decision result in the step S21 is NO, or the decision result in the step S22 is YES, a write request L-WE is output to the local memory 15 in step S23, and a write request F-WE is output to the frame memory 14 and , Outputs a writable response DRDY to the drawing condition determination unit 25, and outputs a writable response TRDY to the texture processing unit 24. On the other hand,
If the decision result in the step S22 is NO, a step S22 is executed.
Numeral 24 indicates no writing to the local memory 15 / L-
WE is output, / F-WE indicating no writing is output to the frame memory 14, and / DRDY indicating no writing is output to the drawing condition determination unit 25, and / TRDY indicating no writing is output to the texture processing unit 24. Output. After step S24, the process returns to step S21.

After step S23, a step S25 decides whether or not there is a write request D-WE from the drawing condition decision unit 25. If the decision result in the step S25 is YES, a step S26 is reached.
Fetches the data from the drawing condition determination unit 25 into
It outputs / DRDY indicating that writing is impossible to the drawing condition determination unit 25. If the decision result in the step S25 is NO or after the step S26, a step S27 is performed in the texture processing section 2
4 to determine whether there is a write request T-WE from
If the decision result is NO, the process returns to step S21.
On the other hand, if the decision result in the step S27 is YES, a step S28 takes in the data from the texture processing unit 24 into the inside, outputs / TRDY indicating that writing is impossible to the texture processing unit 24, and then proceeds to a step S2.
Return to 1.

FIG. 31 is a block diagram showing the overall configuration of a system to which the second embodiment is applied. In the figure, a three-dimensional image generation and display system includes a user input device 61, a host processor 62, and an auxiliary storage device 6 connected as shown.
3, a host memory 64, a geometric conversion processor 65, a work memory 66, an information processing device 67, a display control unit 68, and a display 69. Host processor 62
Corresponds to the host computer 12 shown in FIG.
The information processing device 67 includes a rasterizing processor 67a and a graphic-specific hardware unit 67b, and the graphic-specific hardware unit 67b corresponds to the graphic-specific hardware unit 18 illustrated in FIG. The display 69 corresponds to the display unit 17 shown in FIG.

The host processor 62 manages information such as coordinates of a three-dimensional object, a viewpoint, a light source, and the like. This information is
Stored in the host memory 64 or the auxiliary storage device 63, the host processor 62 performs processing such as deformation of an object shape and movement of a viewpoint in accordance with an input from a user input device 61 such as a keyboard, and finally a three-dimensional image to be drawn. The image information is supplied to the geometric transformation processor 65.

The geometric conversion processor 65 performs a process of converting three-dimensional image information of an object into image information of two-dimensional coordinates of a screen to be displayed. This geometric transformation processor 65
Can be omitted as long as the host processor 62 has a sufficient calculation capability. The rasterization processor 67a in the information processing device 67 has a command form suitable for dividing a polygon represented by two-dimensional coordinates in the horizontal direction and calculating a start point, the number of times of drawing, and the like. Further, the graphic dedicated hardware unit 67 b in the information processing device 67 decomposes the rasterized information into pixels, determines a color to be drawn, and writes the color into the frame memory 14. The display control unit 68 performs a process of reading information stored in the frame memory 14 and displaying the information on the display 69. Thus, a three-dimensional image can be generated and displayed in real time in response to an input from the user.

FIG. 32 shows an information processing apparatus 67 shown in FIG.
FIG. 4 is a block diagram showing a configuration of a part. In FIG. 32, FIG.
The same reference numerals are given to the same portions as those in FIG. 21 and the description thereof is omitted. In FIG. 32, a portion surrounded by a chain line is formed of one semiconductor chip 70. The frame memory 14, the local memory 15, and the texture memory 16 are each external to the semiconductor chip 70. For example, the frame memory 14 has MB818251
VRAM can be used.
The SDRAM 811181621 can be used in the texture memory 16.
An M or MB 82208 SRAM can be used.

As described above, only writing from the semiconductor chip 70 to the frame memory 14 is performed, and the color data and α value read from the frame memory 14 in the first embodiment of FIG. The data is read from the local memory 15 together with the data. That is, the frame memory 1
4 is read only from the display controller 68 that controls the display 69. The local memory 15
Since it is not directly connected to the display control unit 68, S
A memory that can be accessed at a high speed, such as a DRAM, can be used as the local memory 15. As a result, even if a dual-port VRAM is used for the frame memory 14 as in the first embodiment of FIG.
The processing efficiency of the entire system can be improved.

Further, the processing of the drawing condition determination unit 25 accessing the local memory 15 and the processing of the texture processing unit 24 accessing the texture memory 16 are performed in parallel with each other. Therefore, the drawing condition determination unit 25 can operate at the optimal timing for the local memory 15, and the texture processing unit 24 can operate at the optimal timing for the texture memory 16.

As described above, in this embodiment, high-speed image generation and display processing can be performed, and the processing of the entire system can be sped up without being affected by the access time of the memory used. . By the way, in the graphic dedicated hardware section 18 shown in FIG. 20, the respective sections are combined in accordance with the flow of processing to perform pipeline processing. FIG. 33 is a block diagram for explaining the pipeline processing after the DDA unit 23 in the graphic dedicated hardware unit 18 shown in FIG. In FIG.
The same parts as those in FIG. 20 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 33, the host computer 12
Prepares coordinates and color information of a polygon to be drawn as polygon information. The polygon information is decomposed by the DDA unit 23 into information on each point constituting the screen of the display unit 17, and the coordinates of each point, color information, and the like are supplied to the drawing pipeline 81 as original information M. In addition, information on the already generated screen and the like stored in the frame memory 14 are supplied to the drawing pipeline 81 as original information N as needed. The drawing pipeline 81 performs a predetermined process on the original information M and N, and performs a process of storing information on a polygon to be finally drawn, that is, generated image information in the frame memory 14.

The drawing pipeline 81 has processing units 82-1 to 82-n and pipeline registers 83-1 to 83-n which are alternately connected as shown. The processing units 82-1 to 82-n are dedicated hardware corresponding to individual processes, that is, portions that perform various types of arithmetic processing by an arithmetic unit. Also, pipeline registers 83-1 to 8-3
3-n forms a group of pipeline registers.

The original information M and N are stored in each processing unit 82.
The processing is performed at -1 to 82-n, and finally, the generated image information is output from the drawing pipeline 81. Each of the processing units 82-1 to 82-n basically finishes the processing within one clock and writes the processing result to the pipeline registers 83-1 to 83-n connected to the next stage. Each of the units 82-1 to 82-n can perform the following processing every clock. Therefore, the original information M
Although n clocks are required until the first generated image information is output after the input of, the processing result is basically generated every clock after that.

For processing requiring one or more clocks, the processing is divided into a plurality of processing units and a plurality of pipeline registers, and each processing unit performs processing within one clock. I do. The processing content of each of the processing units 82-1 to 82-n is determined by a selection signal of the processing content 1 to n from the host computer 12.

The pipeline processing by the drawing pipeline 81 as described above is suitable for processing continuous information according to a predetermined processing, but the same processing is always performed when image information is generated. It is not always the case that the processing contents are switched at least in units of the generated polygon. FIG. 34A is a diagram showing processing in the case of an n-stage drawing pipeline 81, where i = 1
In the drawing, Ui and Ri in the figure represent the processing of the processing unit 82-i and the pipeline register 83-i, respectively. The input information D1, D2, D3,. . . Are sequentially input.

FIG. 34 (b) shows input information D1 first in the same n-stage drawing pipeline 81 as in FIG. 34 (a).
FIG. 10 is a diagram illustrating a case where the processing contents are switched after processing of .about.Dp to further process input information Dp + 1 to Dq.
FIG. 34B shows a state at the time when up to the input information Dp is input to the drawing pipeline 81. In this state, the input information D is stored in each of the pipeline registers R1 to Rn.
Since p to Dp- (n-1) remain, the processing contents of the processing units U1 to Un cannot be switched. Therefore, the input information after the input information Dp + 1 can be input to the drawing pipeline 81 only after n clocks when the processing for the input information Dp to Dp- (n-1) being processed on the drawing pipeline 81 is completed. There is a first disadvantage of becoming

On the other hand, in the processing of two polygons, even if the processing contents do not change, if there is an overlapping portion of the polygon to be generated on the screen as shown in FIG. There is a second disadvantage mentioned. FIG.
The polygon image B displayed on the screen is a polygon image A
And a part of the polygonal image A is hidden on the screen.

That is, the points on the polygon image A are processed to generate the polygon image A, and the original information N on the last point Pa is input to the drawing pipeline 81. It is necessary to input the original information N relating to the first point Pb of the drawing pipeline 81. However, in the pipeline processing as described above, at least the pine pipeline processing is performed from the time when the original information N relating to one point is input to the rendering pipeline 81 to the time when the processing for the point is completed and the generated image information is obtained. It takes time to complete. In addition, it is actually necessary to consider the time from completion of the pipeline processing to storage in the frame memory 14. Therefore, if the processing of the original information N relating to the first point Pb of the polygon image B is performed ignoring the pipeline processing time and the time until it is stored in the frame memory 14, the original information N of the polygon image A becomes But the previous information N
May be performed, and in that case, the polygon overlapping process cannot be performed correctly. In other words, with a pipeline that only processes the original information M and N, it is not possible to recognize the state of superimposition of polygons or the like, and the host computer 12 that controls the drawing pipeline 81 performs operations such as waiting for polygons. There is also a second disadvantage that the processing must be performed.

In addition to the above-described logical constraints, it is necessary to finally store the image information generated by the drawing pipeline 81 in the frame memory 14 and to store the original information N
In some cases, the information already stored in the frame memory 14 is read out and used again, and there is also a third disadvantage described below relating to the operation of the frame memory 14.

FIG. 36 is a diagram for explaining a read operation and a write operation of the frame memory 14. FIG.
FIG. 3 is an explanatory diagram of a read operation, and FIG. 3B is an explanatory diagram of a write operation. When reading the frame memory 14, as shown in FIG. 36A, data corresponding to an address given from the information processing system is read and output. It takes a certain time called an access time until the data k corresponding to the address k given by the information processing system is read and output. or,
It is necessary to provide a time called a precharge time from when the reading of the data k corresponding to the address k is completed and the access to the next address k + 1 is started. Therefore, one access requires at least a time called one cycle time.

On the other hand, at the time of writing to the frame memory 14, since both the address and the data from the information processing system are given to perform the writing operation as shown in FIG. 36B, the data is output as at the time of reading. You don't have to wait. However, the minimum cycle time required until the completion of writing is specified, and it is not possible to shift to the writing process to the next address earlier than this cycle time.

When a VRAM or the like is used for the frame memory 14, the above cycle time is about 30 nsec.
For this reason, even if the cycle of the pipeline processing is designed to be shorter than the cycle time, the next pipeline processing cannot be performed until the processing of the frame memory 14 is completed. Become. In recent years, higher-speed memories such as a synchronous memory using a synchronization technology have been developed. Therefore, it is conceivable to use these memories as the frame memory 14 to further speed up the operation of the frame memory 14. However, since the operation of a synchronous memory is different from that of a VRAM or the like, simply using a synchronous memory for the frame memory 14 does not lead to an increase in the speed of pipeline processing.

Furthermore, since the generated image information is stored in the frame memory 14 used for storing the generated image information, the following two requirements must be satisfied. First, the display unit 17 displays the generated image information.
Secondly, a function corresponding to the access from the display control unit 68 for controlling the display is required. Secondly, in order to realize a high-speed clearing of the screen of the display unit 17 or the like, a fixed value is collectively written to a specific area. Must have function. In each of the above embodiments, it is assumed that the VR
AM is used. On the other hand, the synchronous memory does not have a function that satisfies these two requirements, so that it is difficult to use it as the frame memory 14.

Next, an embodiment capable of solving the first to third disadvantages will be described. FIG. 37 is a block diagram showing a main part of a third embodiment of the information processing apparatus according to the present invention. 33, those parts which are the same as those corresponding parts in FIG. 33 are designated by the same reference numerals, and a description thereof will be omitted. In the present embodiment, the first disadvantage is solved. In this embodiment, information indirectly involved in the generation of image information is replaced with a path (drawing pipeline 91) similar to the path (drawing pipeline 81) for processing information directly involved in the generation of image information in FIG. With the information directly involved in the generation of the image information. Also, each processing unit 92-1 to 92-n of the drawing pipeline 91
In addition to the operation unit 92a similar to that of FIG. 33, the interpretation unit 9 for interpreting information indirectly involved in the generation of image information
2b are provided. Thereby, for each of the processing units 91-1 to 91-n of the drawing pipeline 91, the calculation of information directly related to the generation of image information in the calculation unit 92a and the generation of image information in the interpretation unit 92b are indirectly performed. Try to do both the interpretation of the information involved. The pipeline registers 93-1 to 93-n of the drawing pipeline 91 are the same as the pipeline registers 83-1 to 83-n of FIG. 33, respectively. The processing performed by the drawing pipeline 91 itself corresponds to, for example, the processing performed by the texture processing unit 24, the drawing condition determination unit 25, the blender unit 26, and the like in the above-described embodiment.

In this embodiment, information indirectly involved in the generation of image information is transmitted through the same path as information directly involved in the generation of image information. In FIG. 37, the control lines of processing contents 1 to n connected to 1 to 82-n are collectively received by the selector 95 and are supplied to the drawing pipeline 91.
The selector 95 may be provided in the DDA unit 23.

The information directly involved in the generation of the image information is, for example, the information output from the DDA unit 23. The information indirectly involved in the generation of the image information is, for example, as shown in FIG. The information is read by the blender unit 26 or, for example, information read from the local memory 15 in FIG. 21 to the drawing condition determination unit 25. Information directly related to the generation of image information on the drawing pipeline 91 is M
Bits, the information indirectly involved in the generation of image information is N
If it is a bit, as shown in FIG. 38 (a), M + N-bit information may be processed by the drawing pipeline 91 by combining both pieces of information. However, in the normal case, the information indirectly involved in the generation of image information does not change frequently, and the period for processing at least one polygon is constant. Therefore, by always supplying information indirectly involved in the generation of image information to the drawing pipeline 91, the number of necessary signal lines and the pipeline registers 93-1 to 93-1 are required.
The number of bits 93-n becomes large and waste occurs.

Therefore, in this embodiment, as shown in FIG. 38 (b), K bits of K bits for handling both information directly involved in the generation of image information and information indirectly involved in the generation of image information. The K + 1-bit information including information and a 1-bit tag F indicating whether the information is the one of the information is supplied to the drawing pipeline 91. When there is a change in the processing contents 1 to n, a column of information directly related to the generation of the image information includes
Information that is indirectly involved in the generation of image information indicating a process change is interrupted, and the information is supplied to the drawing pipeline 91 so that the tag F can identify the information. Each of the processing units 92-1 to 92-n detects the tag F, and determines whether the supplied information is processed by the calculation unit 92a or the interpretation unit 92b.

Since the M-bit information directly involved in the generation of the image information needs to be completely transmitted to the drawing pipeline 91, the value of K needs to be at least M or more. If the N-bit information indirectly involved in the generation of image information is larger than M, in addition to simply setting K to N, the processing contents 1 to n are appropriately grouped and By reconstructing the information together with an identifier for identifying whether or not the content has changed, the information can be stored in M bits or less, so that K = M can be set.

FIG. 39 is a view for explaining the pipeline processing in the third embodiment. FIG. 9 is a diagram showing processing in the case of an n-stage drawing pipeline 81 in the figure, where i = 1 to n, Ui and Ri in the figure are processing units 92, respectively.
-I and the processing of the pipeline register 93-i,
S represents the selector 95. The input information D1, D2, D3,. . . Are sequentially input.

FIG. 39A shows a state in which the drawing pipeline 91 is processing input information D1 to Dp. FIG. 39B shows a state in which the input information Dq and the processing content X are changed. As shown in FIG. 39 (c), this change is performed by the selector S by the information Dx indicating the change of the processing content X.
Is transmitted to the drawing pipeline 91.
FIG. 39D shows input information D on the drawing pipeline 91.
This shows how the input information Dq is transmitted to the drawing pipeline 91 without waiting for the completion of the output of the input information before p.

FIG. 40 is a block diagram showing a main part of a fourth embodiment of the information processing apparatus according to the present invention. In FIG.
The same reference numerals are given to the same portions as 7, and the description thereof will be omitted. In the present embodiment, the second disadvantage is solved. In the present embodiment, as shown in FIG. 40, an end point tag function is provided in the DDA unit 23, and a lock unit 96 is provided in the drawing pipeline 91.

In the case of the third embodiment shown in FIG.
The DA unit 23 simply decomposes the polygon information from the host computer 12 into points and supplies the points to the drawing pipeline 91. On the other hand, in this embodiment, when the polygon information is decomposed into points, an end point tag FE indicating an end point is added to the last point of the polygon. FIG. 41 is a diagram illustrating information to which the end point tag FE is added. The information shown in FIG.
The end point tag FE is added to the information shown in FIG.

The lock unit 96 shown in FIG. 40 is provided in the drawing pipeline 91 at a stage immediately before a unit requiring the original information N from the frame memory 14.
When the end point tag FE added to the input information is ON, the lock unit 96 regards this information as end point information of the polygon, and the information remaining on the drawing pipeline 91 including this information is determined. Until all the information is output from the drawing pipeline 91, the subsequent information is stopped.

As described above, since the information queuing process is performed at the hardware level, the host computer 12 does not need to perform the queuing process. When the host computer 12 performs the waiting process, the process is resumed from the input of the polygon information by recognizing that the process of the drawing pipeline 91 has been completed and then restarting the selector 95. , The DAA unit 23 and the drawing pipeline 91. But,
When the lock unit 96 is provided in the drawing pipeline 91 as in the present embodiment, at least the selector 95, the DAA unit 23, and the processing unit in front of the lock unit 96 in the drawing pipeline 91 even during the waiting process. Can be executed. For this reason, in this embodiment,
Processing immediately after the lock unit 96 can be started immediately after the completion of the queuing process, and loss time due to the queuing process can be minimized.

In some applications, it can be assumed that overlapping of polygons does not occur. In such a case, the above waiting process is not required, but in this embodiment, locking is performed at the hardware level. Therefore, it is desirable to control the locking according to the necessity of the waiting process. FIG. 42 (a)
FIG. 4 is a diagram showing a configuration for masking an end point tag FE in a DDA unit 23. In the figure, an end point recognition circuit 231, a wait setting circuit 232, and a mask circuit 23 are provided in the DAA unit 23.
3 are provided. The end point recognition circuit 231 detects the end point of the polygon according to whether the end point tag FE is added to the input information, and supplies the end point tag FE to the mask circuit 233. On the other hand, the queuing setting circuit 232 supplies a signal indicating the presence or absence of the queuing process to the mask circuit 233. Thus, the mask circuit 233 outputs the end point tag FE only when the waiting process is required.

FIG. 42B is a diagram showing a configuration for masking the end point tag FE in the lock unit 96. In the figure, a lock setting circuit 96 is provided in a lock unit 96.
1, a mask circuit 962 and a lock mechanism 963 are provided. The mask circuit 962 is supplied with signals indicating the presence / absence of a queuing process from the end point tag FE and the queuing setting circuit 961. The mask circuit 962 locks the end point tag FE only when there is a waiting process.
To activate the lock mechanism 963.

FIG. 43 is a diagram for explaining a read operation and a write operation when a synchronous memory is used as the frame memory 14. FIG. 44 is a block diagram showing a main part of a possible information processing apparatus.
The same reference numerals are given to the same portions as 7, and the description thereof will be omitted. FIG. 43A is a diagram for explaining the read operation of the frame memory 14 in this case. In a read operation,
The frame memory 14 outputs data to the address given by the information processing system after a clock called latency. This latency corresponds to the cycle time of a normal memory, and if attention is paid only to the time from when an address k is given to when the corresponding data k is output,
It is not much different from normal memory operation speed. But,
The synchronous memory is different from a normal memory, and the information processing system can give the next address k + 1 without waiting for the data k to be output. can do. For this reason, the cyclonos memory can operate at a clock cycle faster than the cycle time unit of a normal memory.

FIG. 43B is a diagram for explaining a write operation when a synchronous memory using a synchronous technique is used for the frame memory 14. In the write operation, the information processing system writes data by giving both the address and the data to the frame memory 14. It also takes a time corresponding to the cycle time until the frame memory 14, that is, the synchronous memory itself finally writes data therein, but the information processing system operates in the same manner as in the above read operation. It is not necessary to wait until the writing of the data is completed, and it is possible to shift to the writing operation of the next data with the next clock.

As described above, by using the synchronous memory as the frame memory 14, it is possible to perform a higher-speed operation as compared with the case where a normal memory is used.
However, as shown in FIG. 44, an effective operation is performed simply by using a synchronous memory as the frame memory 14 and exchanging the drawing pipeline 91 and the frame memory 14 with one certain processing unit 92-j. Can not. That is, in the case of FIG. 44, the next operation cannot be performed during the time from when an address is given to the frame memory 14 to when the frame memory 14 receives the data output from the drawing pipeline 91. For this reason, the read timing of the frame memory 14 is the timing shown in FIG. 45 despite the use of the synchronous memory. On the other hand, in the writing operation in this case, writing can be performed with the operation clock of the drawing pipeline 91 without waiting for the completion of the processing in the drawing pipeline 91. However, synchronous memory
When switching from a write operation to a read operation, and vice versa, from a read operation to a write operation, a certain loss time occurs. Therefore, as shown in FIG.
It is not possible to perform processing that makes use of a high-speed write operation. In FIG. 46, “R” indicates read (read),
“W” represents write.

FIG. 47 is a block diagram showing a main part of a fifth embodiment of the information processing apparatus according to the present invention. In FIG.
The same reference numerals are given to the same portions as 7, and the description thereof will be omitted. In the present embodiment, the third disadvantage is solved. In this embodiment, as shown in FIG. 47, an arbitration circuit 97 is provided between the frame memory 14 composed of a cyclonic memory and the drawing pipeline 91. This arbitration circuit 97
Will be described later with reference to FIG.

Efficiency of the read operation is realized by the processing units 92-j to 92-j + 1 in the drawing pipeline 91 shown in FIG. In the case of FIG. 44, the reading from the frame memory 14 is performed by the processing unit 92-j. In this embodiment, the processing unit 92-j is used as an address presenting unit and gives an address to the frame memory 14. Used only for. Receiving the data output from the frame memory 14 is the processing unit 92-j + 1 used as a data receiving unit. Also, the processing unit 9
Pipeline registers 93-j1 to 93-jx are provided to absorb a delay corresponding to a latency between 2-j and the processing unit 92-j + 1. With such a configuration, it is possible to consider that the read operation is subdivided and substantially incorporated into the drawing pipeline 91.

FIG. 48 is a diagram for explaining the read operation of the fifth embodiment. The processing unit 92-j receives the original information Mi supplied from the DDA unit 23 (not shown), gives the address i to the frame memory 14, and outputs the original information Mi to the pipeline register 93-j1. . Thereby, the processing unit 92-j can perform the processing of the original information Mi + 1 at the next clock. The pipeline registers 93-j1 to 93-jx are
Since the number of stages corresponding to the delay defined by the latency time of the frame memory 14 is provided, the processing unit 9
For 2-j + 1, pipeline registers 93-j1 to 93-93
-Jx and the original information Mi passed through the frame memory 14
And the data j read out from the memory are passed. Therefore, the operation speed of the frame memory 14 and the drawing pipeline 91 can be increased.

Incidentally, in order to make the writing operation more efficient,
It is necessary to reduce the switching loss between reading and reading by making the writing operation as continuous as possible. This can be realized by the operation of the arbitration circuit 97 described below. FIG. 49 is a block diagram showing a schematic configuration of the arbitration circuit 97. In the figure, an arbitration circuit 97 generally controls a selector 971, a buffer 972 for storing a read address queue, a three-state device 973, a buffer 974 for storing a write address / data queue, and an arbitration circuit 97. It comprises a control unit 975.

The selector 971 selects which address of the two queues to give to the frame memory 14 under the control of the arbitration circuit control unit 975. The three-state device 973 transmits data output from the frame memory 14 to the rendering pipeline 91 that is the read request source under the control of the arbitration circuit control unit 975 at the time of a read request. On the other hand, at the time of a write request, the three-state device 973 selects a data transfer direction for giving data of a write queue to the frame memory 14 under the control of the arbitration circuit control unit 975.

FIG. 50 is a flow chart for explaining the operation of the arbitration circuit control section 975. In the figure, step S3
1 determines whether or not a read operation is being performed on the frame memory 14, and if the determination result is NO, a step S
At 32, it is determined whether a write operation is being performed on the frame memory 14. If the determination result in step S32 is NO
In step S33, it is determined whether there is a request in the read queue, and if the determination result is NO, it is determined in step S34 whether there is a request in the write queue. If the decision result in the step S34 is NO, a step S35 waits until the next clock, and thereafter the process returns to the step S31.

If the decision result in the step S31 is YES, a decision is made in a step S36 as to whether there is a request in the read queue, and if the decision result is YES in the step S3
In step 7, the request address of the read matrix is stored in the frame memory 14.
Give to. On the other hand, if the decision result in the step S36 is NO, the process proceeds to a step S35. Step S3
If the result of the determination in step 2 is YES, it is determined in step S38 whether or not there is a request in the write queue.
If it is ES, the request address / data of the write matrix is given to the frame memory 14 in step S39. On the other hand, if the decision result in the step S38 is NO, the process proceeds to a step S35.

As described above, while the frame memory 14 is performing the read operation, the read queue request is processed preferentially, so that the read operation can be performed continuously. Also, while the frame memory 14 is performing the write operation, the request in the write queue is preferentially processed, so that the write operation can be performed continuously. As a result, it is possible to minimize the loss time due to switching between the write operation and the read operation, and to operate the synchronous memory efficiently when the synchronous memory is used for the frame memory 14.

FIG. 51 is a block diagram showing a main part of a sixth embodiment of the information processing apparatus according to the present invention. In FIG.
The same reference numerals are given to the same portions as 7, and the description thereof will be omitted. In the present embodiment, the third disadvantage is solved. In this embodiment, as shown in FIG. 51, a frame memory 14-1 composed of a synchronous memory is connected to the arbitration circuit 97, and a frame memory 14-2 composed of a VRAM is connected to the display unit 17. For the frame memory 14-1, both the read operation and the write operation are performed from the drawing pipeline 91. On the other hand, both the writing operation from the drawing pipeline 91 and the access request processing from the display unit 17 (display control unit) are performed on the frame memory 14-2. With this configuration, the frame memory 14-1 can operate independently of the display control unit, and can be regarded as the same as the local memory 15 in FIG. Thus, the access from the display unit 17 is made to the frame memory 14-2 which is a VRAM, and the frame memory 14-1 which is a synchronous memory is accessed.
Need only correspond to the processing of the drawing pipeline 91.
Note that the frame memory 14-2 is prepared for connection with the display control unit, and may be constituted by a single memory as long as the frame memory 14-1 includes the function of the VRAM. Needless to say.

However, although the synchronous memory 14-1 has some functions of the VRAM such as batch clear, it does not include all the functions, and is difficult to replace with the VRAM. If a synchronous memory is designed and manufactured exclusively for storing image information as compared with using a complicated synchronous memory, the cost of the information processing apparatus becomes too high. Therefore, a seventh embodiment of the information processing apparatus according to the present invention, which can realize an equivalently high-speed clear function even using a synchronous memory having no special function such as batch write, will be described below.

The configuration of the seventh embodiment is the same as the configuration of the sixth embodiment shown in FIG. 51, so that illustration and description thereof are omitted. In this embodiment, as shown in FIG. 52A, a frame memory 14-1 composed of a synchronous memory stores
In addition to the original information storage area 101, a control information area 102 for storing control information is provided. FIG. 52 (b)
It is a figure showing the relation between original information and control information.

As shown in FIG. 52 (b), the original information is X + 1 bits of bits 0 to X, and the frame memory 1
In contrast to 4-1, control information is stored bit by bit. That is, the control information bit C1 is stored for the original information 1 and the control information bit C2 is stored for the original information 2, so that the original information and the control information correspond one-to-one. Stored in the form. When the original information is read from the frame memory 14-1, the corresponding control information is also read, and the processing unit in the drawing pipeline 91 checks the read control information bit. If the checked control information bit is "1", the read original information value is output as it is to the next unit. On the other hand, if the checked clear control information bit is "0", it is determined that the information has been cleared, and the clear value is output to the next unit.

Since control information bits C1 to CX + 1 are on the same address, these control information bits C1 to CX + 1 can be obtained by accessing the original information only once. Writing "0" in these control information bits C1 to CX + 1 is equivalent to clearing the corresponding original information 1 to X + 1. Therefore, the clearing process can be completed in 1 / (X + 1) time compared to the case where the screen clear is realized by writing the clear value to the original information, and the high-speed clearing process can be realized.

Although the clearing of the screen has been described for the sake of convenience, it can be understood that according to the present embodiment, the function of giving meaning to the original information by different information can be realized in the same manner. Therefore, control information can be used for purposes other than clearing by interpreting information in the processing unit in the drawing pipeline 91 when reading from the frame memory 14-1. For example, the original information value is doubled to display a certain area on the screen brighter than other parts, or conversely, by halving it to display a certain area on the screen darker than other parts. It is possible to give meaning to things.

The control information is X + 1 corresponding to the original information.
Since control information is read out and held once, it is not always necessary to read out control information every time original information is accessed. Therefore, it is very convenient to incorporate a cache function for caching control information into the drawing pipeline 91. FIG. 53 is a block diagram showing a main part of an eighth embodiment of the information processing apparatus according to the present invention. The schematic configuration of the eighth embodiment is the same as the configuration of the sixth embodiment shown in FIG. 51, and the illustration and description thereof are omitted. FIG. 53A shows the drawing pipeline 9 shown in FIG.
1 shows an address presenting unit 92-j incorporated into the drawing pipeline 91, and FIG. 53B shows a data receiving unit 92-j + 1 incorporated into the drawing pipeline 91.

The address presentation unit 92-j shown in FIG. 53A includes a coordinate acquisition unit 201, a clear address cache (memory) 202, a cache test unit 203, an address processing unit 204, and a selector 205. The coordinate acquisition unit 201 extracts the coordinate information from the original information M received from the preceding stage of the drawing pipeline 91 and sets the coordinate information as the source of the address to request the frame memory 14-1 to read. The clear address cache 202 holds information indicating which address in the control information area 102 shown in FIG. 52 is being cached. The address processing unit 204 processes the address obtained by the coordinate obtaining unit 201 to generate an address at which original information is stored or an address at which control information is stored. The cache test unit 203 compares the address acquired by the coordinate acquisition unit 201 with the cached address.
If the control information has already been cached, the address at which the original information is stored is presented to the frame memory 14-1 by the address processing unit 204. On the other hand, if the control information is not cached, or if control information at an address different from the cached control information is required, the address storing the control information is stored in the frame memory 14-1. To present. Further, the selector 205 attaches a tag FC to the original information M and transmits the original information M to the next unit so that the data accepting unit 92-j + 1 described later can be identified as having accessed the control information instead of the original information.

The data receiving unit 92-j + 1 shown in FIG. 53B includes an FC interpreting unit 301, a clear data cache (memory) 302, a clear test unit 303, a register 304 for outputting a clear value, and a selector 305. The FC interpreting unit 301 interprets, that is, recognizes, based on the tag FC, whether the information read from the frame memory 14-1 is the original information or the control information.
The clear data cache 302 holds control information. When the FC interpreting unit 301 recognizes that the control information has been read, the data received from the frame memory 14-1 is written to the clear data cache 302. The clear test unit 303 extracts the coordinates from the original information M and searches the corresponding bit in the clear data cache 302 to identify whether the control information is “0” or “1”. When the control information is "1", the data is not in the clear state, and the data received from the frame memory 14-1 by the selector 305 is stored in the drawing pipeline 91.
To the next unit. On the other hand, the control information is “0”
In the case of (1), since the state is the clear state, the clear value stored in the register 304 is transmitted to the next unit of the drawing pipeline 91.

According to the present embodiment, by using the address presenting unit 92-j and the data receiving unit 92-j + 1 configured as described above, it is possible to minimize the loss accompanying access to control information. The image information generated by the drawing pipeline 91 shown in FIG. 51 is finally written in the frame memories 14-1 and 14-2, but it is necessary to write the control information at the same time. However, since the number of control information needs to be provided for X + 1 pieces of original information, it is possible to reduce the number of control information write requests by maintaining the communication state of the control information and performing the last write. is there. Therefore, a ninth embodiment of the information processing apparatus according to the present invention for realizing this will be described below.

FIG. 54 is a block diagram showing a main part of the ninth embodiment. The schematic configuration of the ninth embodiment is the same as the configuration of the sixth embodiment shown in FIG. 51, and the illustration and description thereof are omitted. FIG. 54 shows the drawing pipeline 9 shown in FIG.
1 shows the configuration of a processing unit 92-n which is incorporated in the last stage and has a control information caching function. FIG.
Medium, the processing unit 92-n includes an FC interpreting unit 401, a clear address cache (memory) 402, a clear updating unit 403, selectors 404 and 405, and an address processing unit 4.
06. The FC interpreting unit 401 interprets, that is, recognizes whether the information read from the frame memory 14-1 is the original information or the control information based on the tag FC. The clear data address cache 402 holds control information. When the FC interpreting unit 401 recognizes that the control information has been read, if the updated control information is already held in the clear data address cache 402, it is necessary to write this control information to the frame memory 14-1. Therefore, the selectors 404 and 405 are caused to wait for the original information M, and the clear data address cache 4
The write to the frame memory 14-1 is performed according to the address and data stored in the address 02. After writing to the frame memory 14-1, new control information is written to the clear data address cache 402. The clear update unit 403 updates control information, that is, control information related to clearing in this embodiment. That is, when the original information M is the original information and the original information is written into the frame memory 14-1, the clear updating unit 403 sets the corresponding bit of the control information to “1”. The address processing unit 406 processes an address obtained by meeting the selector 405 to generate an address at which original information is stored or an address at which control information is stored.

According to the present embodiment, by using the processing unit 92-n configured as described above, it is possible to minimize the loss accompanying access to control information. still,
It goes without saying that the above embodiments may be arbitrarily combined. For example, the third to ninth embodiments can be similarly applied to the second embodiment. When the sixth embodiment shown in FIG. 51 is applied to the second embodiment, the frame memory 14-1 in FIG.
The frame memory 14-2 in FIG. 51 is used as the frame memory 14 in FIG.

As described above, the present invention has been described with reference to the embodiments.
The present invention is not limited to these embodiments, and it goes without saying that various modifications and improvements can be made within the scope of the present invention.

[0172]

According to the first and second aspects of the present invention, the function of each processing unit can be changed without stopping the operation of the drawing pipeline. According to the third to fifth aspects of the present invention, it is possible to operate the drawing pipeline without causing inconsistency in the generated image information even for information related to overlapping images.

According to the present invention, the drawing pipeline can be operated at high speed by using a high-speed memory such as a cyclonic memory. According to the thirteenth aspect, the function of each processing unit can be changed without stopping the operation of the drawing pipeline.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is an operation flowchart of information processing in the first embodiment.

FIG. 4 is an operation flowchart of a microprogram execution unit during a rasterizing process in the first embodiment.

FIG. 5 is a diagram illustrating DD during rasterization processing according to the first embodiment;
It is an operation flowchart of A part.

FIG. 6 is an explanatory diagram of an operation at the time of rasterizing processing in the first embodiment.

FIG. 7 is an explanatory diagram of an operation during a rasterizing process in the first embodiment.

FIG. 8 is an explanatory diagram of an operation at the time of rasterizing processing in the first embodiment.

FIG. 9 is an explanatory diagram of an operation at the time of raster rice processing in the first embodiment.

FIG. 10 is a flowchart at the time of an operation of accessing a shared register of the main / sub arithmetic unit in the first embodiment.

FIG. 11 is a diagram illustrating a shared memory according to the first embodiment;

FIG. 12 is an operation flowchart of the microprogram execution unit at the time of executing a program in the first embodiment.

FIG. 13 is a configuration diagram of an execution control unit according to the first embodiment.

FIG. 14 is an explanatory diagram of the operation of the pipeline control of the execution control unit of the first embodiment.

FIG. 15 is a diagram illustrating the operation of the execution control unit according to the first embodiment.

FIG. 16 is a diagram illustrating the operation of the execution control unit according to the first embodiment.

FIG. 17 is a diagram illustrating the operation of the execution control unit according to the first embodiment.

FIG. 18 is a diagram illustrating the operation of the execution control unit according to the first embodiment.

FIG. 19 is a diagram illustrating the operation of the execution control unit according to the first embodiment.

FIG. 20 is a block diagram illustrating a schematic configuration of a graphics-dedicated hardware unit according to the first embodiment.

FIG. 21 is a block diagram showing a schematic configuration of a main part of a second embodiment of the information processing apparatus according to the present invention.

FIG. 22 is a diagram illustrating a polygon approximately represented by pixels.

FIG. 23 is a diagram showing a processing sequence of the graphic-specific hardware unit shown in FIG. 20.

FIG. 24 is a diagram showing a processing sequence of the graphic-specific hardware unit shown in FIG. 21.

FIG. 25 is a diagram showing a processing sequence of the graphic-dedicated hardware unit shown in FIG. 20 when an access stop factor occurs.

26 is a diagram illustrating a processing sequence of the graphic-dedicated hardware unit illustrated in FIG. 21 when an access stop factor occurs.

FIG. 27 is a diagram illustrating input and output of a control unit other than the control unit of the blender unit.

28 is a flowchart for explaining the operation of the control unit shown in FIG. 27.

FIG. 29 is a diagram illustrating input / output of a control unit of the blender unit.

30 is a flowchart for explaining the operation of the control unit shown in FIG. 29.

FIG. 31 is a block diagram showing the overall configuration of a system to which the second embodiment is applied.

FIG. 32 is a block diagram showing a main part of the system shown in FIG. 31.

FIG. 33 is a block diagram for explaining pipeline processing after the DDA unit in the hardware unit for graphics shown in FIG. 20;

FIG. 34 is a diagram illustrating an n-stage pipeline process.

FIG. 35 is a diagram illustrating a polygon image displayed on the screen in an overlapping manner.

FIG. 36 is a diagram illustrating a read operation and a write operation of the frame memory.

FIG. 37 is a block diagram showing a main part of a third embodiment of the information processing apparatus according to the present invention.

FIG. 38 is a diagram illustrating information directly and indirectly involved in generating image information to be supplied to a drawing pipeline in the third embodiment.

FIG. 39 is a diagram illustrating pipeline processing in the third embodiment.

FIG. 40 is a block diagram showing a main part of a fourth embodiment of the information processing apparatus according to the present invention.

FIG. 41 is a diagram illustrating information directly and indirectly involved in generation of image information to be supplied to a drawing pipeline in a fourth embodiment.

FIG. 42 is a diagram for explaining processing waiting in the fourth embodiment.

FIG. 43 is a diagram illustrating a write operation and a read operation when a synchronous memory is used as a frame memory.

FIG. 44 is a block diagram showing a main part of a possible information processing apparatus.

FIG. 45 is a diagram illustrating a read operation of the device illustrated in FIG. 44.

FIG. 46 is a view for explaining switching between read / write operations of the device shown in FIG. 44;

FIG. 47 is a block diagram showing a main part of a fifth embodiment of the information processing apparatus according to the present invention.

FIG. 48 is a diagram illustrating a read operation of the fifth embodiment.

FIG. 49 is a block diagram illustrating a schematic configuration of an arbitration circuit according to a fifth embodiment.

FIG. 50 is a flowchart illustrating the operation of the arbitration circuit control unit.

FIG. 51 is a block diagram showing a main part of a sixth embodiment of the information processing apparatus according to the present invention.

FIG. 52 is a diagram illustrating a configuration of a frame memory in a seventh embodiment of the information processing apparatus according to the present invention.

FIG. 53 is a block diagram showing a main part of an eighth embodiment of the information processing apparatus according to the present invention.

FIG. 54 is a block diagram showing a main part of a ninth embodiment of the information processing apparatus according to the present invention.

FIG. 55 is a block diagram illustrating an example of a conventional information processing apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first information processing means 2 second information processing means 3 communication means 4 processing information storage means 5 information storage means 6 first information storage means 7 second information storage means 8 third information storage means 11 information processing System 12 Host computer 13 Information processing device 14 Frame memory 15 Local memory 16 Texture memory 18 Graphic-specific hardware 19 Microprogram execution 23 DDA unit 24 Texture processing unit 25 Drawing condition determination unit 26 Blender unit 27 Host interface 28 Execution control unit 29 Command Cache 30 Main operation unit 31 Sub-operation unit 32 Shared register 33 Shared memory 61 User input device 62 Host processor 63 Auxiliary storage device 64 Host memory 65 Geometric conversion processor 66 Work memory 67 Information processing device 68 Table Control unit 69 displays 70 the semiconductor chip 81 and 91 rendering pipeline 92-1 to 92-n processing units 93-1~93-n pipeline register 95 Selector 96 lock unit 97 arbitration circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shigeru Sasaki 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Ritsuko Tatematsu 1015 Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (13)

[Claims] 1. An information processing apparatus connected to a memory unit for storing first information indirectly involved in generation of image information to be displayed, wherein the first information and the image information to be displayed are A rendering pipeline for performing pipeline processing on second information directly involved in generation and supplying generated image information to the memory means; and if the rendering pipeline is a natural number, the second information A processing unit having an operation means for performing the above operation and an interpretation means for interpreting the first information, and a register for storing an output of the processing unit are provided alternately in n stages. An information processing apparatus, comprising: selector means for collectively receiving a control line of processing content corresponding to a unit together with the second information obtained from a higher-level device and supplying the control line to the drawing pipeline. 2. A rendering pipeline comprising: information for handling both the first and second information; and a tag indicating which of the first and second information is the information. A processing unit of the drawing pipeline detects the tag and determines whether the supplied information is processed by the calculation unit or the interpretation unit.
The information processing device according to claim 1. 3. The apparatus is provided in a stage preceding the drawing pipeline,
When decomposing polygon information from a higher-level device into points, an end point tag indicating an end point is added to the last point of the polygon,
And a lock unit provided in a stage immediately before the processing unit that needs the first information from the memory unit in the drawing pipeline. When the end point tag added to the input second information is on, the second information is regarded as the end point information of the polygon, and the second information including the second information is displayed on the drawing pipeline. The information processing apparatus according to claim 1, wherein a process of stopping subsequent information until all remaining information is output from the drawing pipeline is performed. 4. The information processing apparatus according to claim 3, wherein said output means has means for outputting an end point tag only when a waiting process is required. 5. The lock unit comprises: a lock mechanism for stopping subsequent information until all the information remaining on the drawing pipeline is output from the drawing pipeline; and an end point tag only when there is a waiting process. The information processing apparatus according to claim 3, further comprising a unit that activates the lock mechanism. 6. The drawing pipeline is a first processing unit used as an address presenting unit and used only to give an address to the memory means, and receives data output from the memory means and receives data. The information processing apparatus according to claim 1, further comprising a second processing unit used as a unit, and a plurality of pipeline registers that absorb a delay corresponding to a latency between the first and second processing units. 7. A memory device is provided between the memory means and the drawing pipeline. When the memory means is performing a read operation, a request in a read queue is preferentially processed so that the read operation is performed continuously. During the write operation of the memory means, the arbitration means for suppressing the loss time due to switching between the write operation and the read operation by causing the request of the write queue to be processed preferentially and performing the write operation continuously. The information processing apparatus according to claim 6, further comprising: 8. The information processing apparatus according to claim 1, wherein said memory means comprises a synchronous memory. 9. An information processing apparatus connected to a memory means for storing first information indirectly involved in generation of image information to be displayed, wherein the first information and the image information to be displayed are stored in a memory. A drawing pipeline for performing pipeline processing on second information directly involved in generation and supplying generated image information to the memory unit; wherein n is a natural number; A processing unit having an operation means for calculating information and an interpretation means for interpreting the first information, and a register for storing an output of the processing unit are provided alternately in n stages. A first memory connected to the arbitration circuit, and a second memory connected to the display means. The first memory reads out and writes data from the drawing pipeline to the first memory. Both of the writing operation are performed, and both the writing operation from the drawing pipeline and the access request processing from the display unit are performed on the second memory. An information processing apparatus, comprising: a first storage area for storing original image information; and a second storage area for storing control information provided one-to-one with the original image information. 10. The drawing pipeline has an address presentation unit and a data reception unit connected to the arbitration unit, and the address presentation unit and the data reception unit each include a unit for caching control information. Item 10. The information processing device according to Item 9. 11. The address presenting unit includes means for holding information indicating which address of the second storage area is being cached, and when control information has already been cached, the original image information is stored. Is presented to the first memory and the control information is not cached, or when control information of an address different from the cached control information is required. Presenting an address at which control information is stored to the first memory, the data receiving unit, when the control information has a first value, the data received from the first memory to the drawing pipeline 11. The information according to claim 10, wherein a predetermined value is transmitted to a next-stage unit of the drawing pipeline, and when the control information is the second value, a predetermined value is transmitted to a next-stage unit of the drawing pipeline. Processing apparatus. 12. The information processing apparatus according to claim 9, wherein said drawing pipeline has a processing unit incorporated in a final stage thereof and having a control information caching function. 13. An information processing method in an information processing apparatus connected to a memory means for storing first information indirectly involved in generation of image information to be displayed, wherein the first information and the display information are displayed. A first step of performing pipeline processing on second information directly related to generation of power image information and supplying generated image information to the memory means; and the first step is a step in which n is a natural number. A processing unit having an operation means for performing an operation on the second information and an interpretation means for interpreting the first information, and a register for storing an output of the processing unit being provided alternately in n stages A second step of using a pipeline to collectively receive a control line of processing contents corresponding to each of the n-stage processing units together with the second information obtained from a higher-level device and supplying the control line to the drawing pipeline An information processing method comprising: