JPH11143684A - Carry look-ahead circuit and parallel adder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the propagation delay of a carry even in the case that an input value is turned to a specified bit state and to reduce the circuit scale in a parallel adder. SOLUTION: This circuit is provided with full adders 100 -103 for inputting carry signals from a low order and the same order bit of the input value and outputting the added value S and the carry C in the addition, exclusive OR gates 500 -503 for obtaining the exclusive OR of the same order bit in the input values A and B, an AND gate 60 for obtaining the AND of outputs from the exclusive OR gates 500 -503 and a selector 70 for selecting an input carry Cin supplied to the full adder 100 of a lowest order when the output level of the AND gate 60 is '1' and selecting the carry C3 outputted from the full adder 100 of a highest order when it is '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a look-ahead carry circuit and a parallel adder which speed up the propagation of a carry signal (carry) and reduce the circuit scale by suppressing the required number of gates.

[0002]

2. Description of the Related Art In general, a parallel adder which inputs two or more sets of values consisting of a plurality of digits and adds them in parallel for each digit is configured as shown in FIG. The parallel adder shown in the figure executes parallel addition of 4-bit input values A and B.
Full adder 10 ₃ to 10 ₀ are respectively provided corresponding to each bit, the carry and the input value A from the lower, and enter the corresponding isotopic bits of B, the addition and the added value S Is calculated and output. For example, full adder 10 ₁ corresponding to the lower 2nd bit carries carry C0 from the lower bit and input bit A
1, B1 are input, and the added value S1 and the carry C1 in the addition are output. However, in the parallel adder by such a configuration, since it is necessary to output a carry Cout propagates all full adder 10 ₃ to 10 _0, there is a problem that the addition time is prolonged.

[0003] There are various methods for solving this problem. In general, a carry and a combination of logic gates are used.
A technique is employed in which carry is calculated ahead of each digit using look ahead. When the k-th (k = 0, 1, 2,...) Carry Ck is obtained using this carry look ahead, the logical formula thereof is shown as the following formula (Japanese Patent Laid-Open No. 57-111737). Gazette).

[0004]

(Equation 1)

In this equation, i, j, and k have the following relationships. k = j + 1 = i + 2 =... Dk and Ek indicate the following relations in each bit of the input values A and B. Dk = AkBk, Ek = Ak + Bk

Using this equation, the logical equation for carry C3 in 4-bit parallel addition is shown as follows.

[0007]

(Equation 2)

However, in such carry look ahead, as the number of bits increases, as can be seen from the above equation, the required number of gates increases dramatically, and the number of bits for one gate increases. It can be seen that the number of inputs also increases. Therefore, the total number of required transistors increases exponentially with respect to the number of bits, which causes an obstacle such as an increase in chip area particularly when integrated in an LSI.

Therefore, a technique has been adopted in which a carry look-ahead is constructed in a pseudo manner to reduce the number of necessary gates while maintaining a high speed of carry propagation. FIG. 3 is a block diagram showing a configuration of a parallel adder using this technique. Parallel adder shown in this figure, the typical parallel adder shown in FIG. 2, the OR gates 20 ₀ ~
20 ₃ , an AND gate 30 and an OR gate 40 are added. Of these, the OR gate 20 _0-2
0 ₃ each is provided corresponding to each of the respective input bits, and outputs a logical sum of the corresponding isotope-bit in the input values A and B. Further, the AND gate 30 obtains an output of the OR gate 20 _{0-20 3,} a logical product of the input carry Cin to the parallel adder. The OR gate 40 obtains an output of the AND gate 30, a logical sum of the output carry C3 of the full adder 10 ₃ corresponding to the most significant bit.

According to such a configuration, a state in which at least one of the same bits of the input value A or B is "1" occurs in all the bits, and the input carry Cin to the parallel adder is "1". , That is, when the carry C3 of the most significant bit by the full adder 10 ₃ reliably transitions to “1”, the input carry Cin is output via the OR gate 40 as the output carry Cout of the parallel adder. Is done. Therefore, the carry delay in this case is equal to the sum of AND gate 30 and OR gate 40.
Requires only stage is faster than through all of the full adder 10 _{0 -} 10 _3.

[0011] If at least one of the logical sum by the OR gate 20 _{0-20 3} becomes "0", i.e., a state in which peer-bit input values A or B are both "0" is at least one When the above-mentioned bit occurs, the carry C3 is output via the OR gate 40 as the output carry Cout. However, in this case, if both of the input bits transit to “0”, the carry of the full adder corresponding to the bit unconditionally transits to “0”, and the propagation of the carry becomes “0”. Full adder and OR gate 4 corresponding to the upper bits of
Only through 0. For example, the output carry Cou
Assuming that the input bits A1 and B1 transition to “0” among the cases where the carry C3 is output as t,
Since the carry C1 of the full adder 10 ₁ transitions to “0”, the carry is propagated by the full adders 10 ₂ and 10 ₃ and the OR gate 4 corresponding to the upper bits of the input bits A1 and B1.
0.

Meanwhile, paying attention to the circuit scale, although the AND gate 30 having an input number obtained by adding 1 to the number of bits are required, other OR gate 20 ₀ corresponding to the number of bits
Because it requires a 20 ₃ and one OR gate 40, as compared with the case of using the carry look ahead according to the above equation, it is possible to significantly reduce the circuit scale.

[0013]

However, in such a parallel adder in which the carry look ahead is artificially constructed, when the input values A and B are in specific bit states, the carry is not obtained. The problem of delay occurred. Specifically, this problem is a case where a state where only one of the same bits of the input value A or B is “1” occurs in all the bits, and the input carry Cin is “0”. Occurs when transiting to. In this case, closing the AND gate 30, and is also not identified carry in the full adder 10 ₃ to 10 ₀ of any results,
The output carry Cout, all full adder 10 ₃ to 10 ₀
This is because it is necessary to propagate

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to prevent carry propagation delay even when an input value is in a specific bit state. Another object of the present invention is to provide a carry look-ahead circuit and a parallel adder which can reduce the circuit scale by suppressing the required number of gates.

[0015]

According to the present invention, there is provided, in accordance with the present invention, a carry calculating means for inputting a carry signal from a lower order and an input value to calculate and output a carry signal; Detecting means for detecting whether the carry is indefinite by adding only the input values, and, if the detection result by the detecting means is positive, selecting the carry signal from the lower order; And selecting means for selecting a carry signal by the carry calculating means if the detection result by the means is negative.

Further, in the present invention, a carry signal is provided corresponding to each digit, and a carry signal is input from the lower order and the value of the corresponding digit among the input values to calculate and output the carry signal. At least one carry calculating means, and one or more first detecting means provided corresponding to each digit and detecting whether or not the carry is indefinite by adding only the values of the corresponding digits. And the first
A second detection means for detecting whether or not all the detection results by the detection means are positive; and, if the detection result by the second detection means is positive, input to the least significant carry calculation means. And selecting means for selecting a carry signal output from the most significant carry calculation means if the result of detection by the second detection means is negative while selecting a carry signal to be performed. It is characterized by.

Further, in the present invention, an adder for inputting a carry signal from the lower order and an input value, and calculating and outputting a result of the addition and a carry signal in the addition, an input means for the carry. Detecting means for detecting whether or not the sum of the values is undefined, and if the result of the detection by the detecting means is affirmative, selecting the carry signal from the lower order; If the result is negative, there is provided a selecting means for selecting a carry signal by the carry calculating means.

In addition, according to the present invention, a carry signal is provided corresponding to each digit, and a carry signal from the lower order and a value of a corresponding digit among the input values are inputted, and the addition result and the addition result are input. And one or more carry calculating means for calculating and outputting a carry signal in the, and detecting whether or not the carry is indefinite only by adding values of corresponding digits. If the result of the detection by the one or more first detecting means and the second detecting means is affirmative, the carry signal input to the least significant adding means is selected while the second detecting And selecting means for selecting a carry signal output from the highest-order addition means if the detection result by the means is negative.

[0019]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram illustrating a configuration of the parallel adder according to the present embodiment. The parallel adder shown in this figure is different from the configuration shown in FIG.
The _{0-20 3} was replaced with the exclusive OR gate 50 _{0-50 3,} the second, provided an AND gate 60 for obtaining the logical product of the outputs from these exclusive OR gate 50 _{0-50 3,} the third,
According to the output of AND gate 60, input carry C
The configuration is such that a selector 70 for selecting either in or carry C3 is provided.

Of these, exclusive OR gates 50 ₀ to 50 ₃
Has the significance of detecting the case where the carry becomes indefinite in the full adder corresponding to the bits only by adding the same bits in the input values A and B, respectively. The selector 70 includes AND gates 71 and 73, an inverting gate 72, and an OR gate 74. Of these, the AND gate 71 calculates the logical product of the output of the AND gate 60 and the input carry Cin. The inversion gate 72 calculates the logical product of the inverted output of the AND gate 60 and the carry C3, and the OR gate 74 calculates the logical sum of the outputs from the AND gates 71 and 73. Therefore, the selector 70 by such arrangement, if the output level of the AND gate 60 is "1", while selecting the input carry Cin supplied to the full adder 10 ₀ the least significant bit as an output carry Cout, AND gate If the output level of 60 is "0",
It will select the carry C3 output from the full adder 10 ₃ most significant bits.

Here, the output of the AND gate 60 is "1".
Means that all the exclusive ORs of the exclusive OR gates 50 ₀ to 50 ₃ are “1”, that is, only one of the same bits of the input value A or B is “1”. Is a state where all bits are present. More specifically, the carry is undefined only by adding the input values A and B, and the output carry Cout is specified only depending on the input carry Cin. Is the case.
In this case, the input carry Cin is used as the output carry Cout.
Is selected, the carry delay is only two stages of the AND gate 71 and the OR gate 74 in the selector 70, and the inconvenience that occurs when a specific bit state occurs in the configuration shown in FIG. 3 is eliminated. It will be.

Further, if the if the output of the AND gate 60 becomes "0", at least one of the exclusive OR by the exclusive OR gate 50 _{0-50 3} becomes "0", i.e., the input value This is a case where a state where the same bits of A or B have the same value occurs in at least one or more bits. In this case, as the output carry Cout,
While the carry C3 by full adder 10 ₃ is selected, if certain input bit transitions both to "1", while the carry of the full adder corresponding to the bit transitions unconditionally to "1" If a certain input bit transits to “0”, the carry of the full adder corresponding to that bit transits to “0” unconditionally, so that the propagation of the carry becomes
Only through the full adder and the selector 70 corresponding to the upper bit of the bit having the same value. Therefore, even if carry C3 is selected by selector 70,
Situation that the output carry Cout propagates through all of the full adder 10 ₃ to 10 ₀ does not occur unlike the conventional. For example, assuming that the input bits A1 and B1 transition to "1" while the output of the AND gate 60 is "0", the carry C1 by the full adder 10 ₁ is assumed.
But carry -Cin, because transitions independently of "1" and C0, the propagation of the carry is to be through the full adder 10 _2, 10 ₃ and the selector 70 corresponding to the upper bits of the input bit A1, B1 Become. The same applies to the case where the input bits A1 and B1 transition to “0” because the carry C1 transitions to “0”.

On the other hand, paying attention to the circuit scale, an exclusive OR gate 50 which corresponds to the number of bits and an AND gate 60 having a number of inputs corresponding to the number of bits _{0-50 3} and it is necessary, in other selector Since only 70 is required, the circuit scale can be significantly reduced as compared with the case where the carry look ahead applying the above equation is used.

In the above-described embodiment, the input values A, B
The addition value S for determining the carry Cout by the addition, was used full adder 10 _{0 -} 10 _3, carry Cou
If only t is required, the carry calculation circuit may be cascaded. Needless to say, the full adder includes a carry calculation function. Furthermore, although the embodiment has 4 bits, it is needless to say that the present invention is not limited to this. Further, a large number of bits may be divided into a plurality of bits, and one of the blocks may be constituted by the parallel adder according to the embodiment to execute the addition of the many bits. That is, the configuration may be such that the parallel addition circuit itself according to the embodiment is divided into blocks and connected in multiple stages in cascade according to the number of bits.

[0025]

As described above, according to the present invention, even when the input value is in a specific bit state, the propagation delay of carry can be prevented and the occurrence of the necessary number of gates can be suppressed. The circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a parallel adder according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a general parallel adder.

FIG. 3 is a block diagram showing a configuration of a conventional parallel adder using a pseudo carry look ahead.

[Explanation of symbols]

10 _{0 -} 10 ₃ ...... full adders (a carry calculation means, adding means), 50 _{0-50 3} ...... exclusive OR gate (first detecting means), 60 ...... AND gate (second detection means) , 70 ... Selector (selection means)

Claims (4)

[Claims] 1. A carry calculating means for inputting a carry signal and an input value from the lower order and calculating and outputting a carry signal, and detecting whether the carry is indefinite only by adding the input values. Detecting means for selecting, if the detection result by the detecting means is positive, the carry signal from the lower order is selected, while if the detection result by the detecting means is negative, the digit by the carry calculating means is selected. Selecting means for selecting a carry signal. 2. One or more carry calculating means provided corresponding to each digit, for inputting a carry signal from a lower order and a value of a corresponding digit among input values, and calculating and outputting a carry signal. And at least one first detecting means provided for each digit and detecting whether the carry is indefinite by adding only the values of the corresponding digits, and the first detection Second detection means for detecting whether or not all the detection results by the means are positive; if the detection result by the second detection means is positive,
While the carry signal input to the least significant carry calculating means is selected, if the result of detection by the second detecting means is negative, the carry signal output from the most significant carry calculating means is selected. And a selection means for selecting. 3. An adding means for inputting a carry signal and an input value from the lower order, and calculating and outputting a result of addition and a carry signal in the addition, wherein the carry is undefined only by addition of input values. Detection means for detecting whether or not, if the detection result by the detection means is positive, select the carry signal from the lower order, while if the detection result by the detection means is negative, Selecting means for selecting a carry signal by the carry calculating means. 4. A signal provided corresponding to each digit, inputting a carry signal from a lower order and a value of a corresponding digit among input values,
One or more carry calculating means for calculating and outputting the addition result and a carry signal in the addition; provided for each digit, and the carry is undefined only by adding values of the corresponding digits. One or more first detection means for detecting whether or not the detection result is true, and if the detection result by the second detection means is positive,
Selecting means for selecting a carry signal input to the lowest-order adding means, and selecting a carry signal output from the highest-order adding means if the result of detection by the second detecting means is negative; A parallel adder comprising: