JPH11143569A - Computer control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extent a time when a CPU starts to output a data in a subsequent cycle and to prevent bus collisions by adding a function to temporarily stop a CPU clock based on an operating state of the CPU. SOLUTION: Data buses of a CPU 101, a memory 104 and an I/O 105 are all directly connected to a data bus 106. An address output 109 of the CPU 101 and all control signals 110 including read/write signals are supplied to a control circuit 103. Then a control signal 111 of the memory 104 and a control signal 112 of the I/O 105 are produced. An original clock signal 108 that is outputted from a clock generator 102 is fetched by the circuit 103, and a CPU clock 107 is outputted to the CPU 101 from the circuit 103. When a write cycle follows a read cycle in regard to the CPU cycles, the clock 107 is temporarily stopped to delay the start of data output. As a result, collisions are prevented between the read and write data, and accordingly malfunctions and failures can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a timing control method between a CPU, a memory device, and an IO device in a computer device.

[0002]

2. Description of the Related Art In FIG.
4 and a data bus of the I / O 405 are connected to a CPU data bus 406 via a buffer 410 and a buffer 411. The output of the clock generator 402 is C
It is directly connected to PU401. This will be described with reference to the timing chart of FIG. From time T53 to time T54 is the I / O read cycle of the CPU 401, and the I / O data 414 is output by the I / O read signal 503.
After the I / O read signal is negated at time T54, I
I / O data 4 within the time specified in the characteristics of / O405
14 is set to high impedance. After time T54 is a memory write cycle of the CPU 401, and write data is output to the data bus 406 from time T51.
The problem here is that the time regulation may be, for example, about 50 ns, and if the CPU clock is 18 MHz
If the data bus 406 is directly connected to the I / O data 414 on the order of z, the bus will collide during the time T51 and the time T52.

Conventionally, in order to avoid a data bus collision, the bus is divided by a buffer 410 and a buffer 411 in FIG. 4 and the buffer is opened by a control signal 407 and a control signal 408 in FIG. Data 41
4 and memory data 413.

[0004]

In the conventional bus contention prevention method, a buffer for dividing the bus is required. If the data bus of the CPU is increased to 32 bits or 64 bits, the number of buffers is accordingly increased. However, there is a problem in that the mounting space and cost are disadvantageous in terms of mounting space and cost.

[0005]

According to the present invention, there is provided a function of temporarily suspending a CPU clock according to an operation state of the CPU. By stopping the clock in this manner, the time until the CPU starts outputting data in the next cycle can be extended, and bus collision can be prevented.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The clock control method of the present invention
Since the operation state of U is constantly monitored and the clock is stopped only when necessary, an address decoder, a memory controller, an I / O, which collects information such as address information output from the CPU and whether the operation is a read operation or a write operation. It is most efficient to provide it as an additional function in the O controller or the like.

[0007] Also, due to the nature of controlling the CPU clock, the control circuit needs to operate stably at high speed, and is preferably realized by, for example, an ASIC.

[0008]

Embodiments will be described with reference to the drawings.
In FIG. 1, CPU 101, memory 104 and I / O
All data buses 105 are directly connected to the data bus 106. All the control signals 110 including the address output 109 and the read / write signal of the CPU 101 are connected to the control circuit 103 and the control signal
1 and a control signal 112 for the I / O 105 are generated.
The original clock signal 108 output from the clock generator 102 is taken into the control circuit 103,
Outputs the CPU clock 107 to the CPU 101.

The operation of the embodiment will be described with reference to FIG. In this example, the frequency of the original clock signal 108 output from the clock generator 102 is 18.4 MHz, and the clock cycle is about 54 nS. The time from the negation of the I / O read signal 201 to the high impedance of the data bus is 50 ns at the maximum. The time from the negation of the memory read signal 202 to the high impedance of the data bus is 35 ns at the maximum. C
The start of the data bus drive in the write cycle of the PU 101 is the first falling edge of the CPU clock in each cycle.

The CPU cycle is a memory read cycle in CYCLE1, and the subsequent CYCLE2 is a memory read cycle.
This is an O read cycle. The time from the negation (T1) of the memory read signal 202 to the assertion (T2) of the I / O read signal 201 is about 54 nS, and since the memory read data becomes high impedance within 35 nS from T2, bus collision cannot occur. . Therefore, the CPU clock is not stopped.

CYCLE3 is a memory write cycle, and when the CPU clock is not stopped, CCYLE3 is set to C from time T4.
The PU starts data output. However, the data output of the I / O 105 in CYCLE2 is up to 50 from time T3.
Since the nS drive is performed, a bus collision occurs for a maximum of about 23 nS. In the present invention, the clock mask signal 203 is generated and ORed with the clock original signal 108.
Since the condition is the CPU clock, the clock does not fall at time T4, and the clock falls at time T5 54 ns after time T4. Therefore, the CPU write data is also output from time T5.
In this case, since there is about 81 nS from time T3 to time T5, no bus collision occurs. At the start of the memory write cycle of CYCLE4, the clock is not stopped because no bus collision occurs.

At the start of the I / O write cycle of CYCLE5, memory data is output for a maximum of 35 nS from time T6, so that a bus collision occurs after time T7 without clock stop. Therefore, the clock is stopped similarly to the start of CYCLE3, and the start of data output is started at time T.
It has been delayed up to 8. The method for generating the clock mask signal 203 varies depending on the CPU, memory, and I / O used. An example will be described with reference to FIG. In this example, the I / O read signal 201 and the memory read signal 20
2 and a signal 205 sampled by the clock original signal 108 and the N of the R / W signal 204 of the CPU.
Generated under OR condition.

[0013]

The present invention is embodied in the form described above and has the following effects. CPU
By temporarily stopping the clock, it is possible to prevent collision between read data and write data in the case where a write cycle continues after a read cycle, thereby preventing a malfunction or failure.

Since the address output and control signal of the CPU are also included in the clock stop condition, the clock can be stopped only when a low-speed memory or I / O is read, and the processing time delay due to the clock stop is minimized. Can be kept to a minimum. Further, since a buffer for bus division is not required, it contributes to a reduction in IC mounting space and a reduction in parts cost. The effect increases as the number of bits in the bus increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus for realizing data bus collision avoidance by clock control.

FIG. 2 is a timing chart for explaining a data bus collision avoiding method using a clock mask.

FIG. 3 is an example of a clock mask signal generation circuit.

FIG. 4 is a block diagram of an apparatus having a conventional data bus collision avoidance method.

FIG. 5 is a timing chart for explaining a conventional data bus collision avoidance method.

[Explanation of symbols]

 101, 401 CPU 102, 402 Clock generator 103, 403 Control circuit 104, 404 Memory 105, 405 I / O 106, 406 CPU data bus 107 Controlled CPU clock 108 Clock source signal 109 CPU address signal 110 CPU control signal 111 Memory control signal 112 I / O control signal 201 I / O read signal 202 Memory read signal 204 CPU R / W signal

Claims (4)

[Claims] A control circuit (10) for connecting a CPU (101) to a memory (104) and an I / O (105).
A computer device having 3). 2. A function for preventing a data output of a memory (104) or an I / O (105) from colliding with a data output of a CPU (101) on a data bus (106) of the CPU. A computer device as described. 3. The computer device according to claim 1, further comprising a function of stopping the CPU clock (107). 4. A memory (104) or I / O (10)
If the write cycle continues after reading 5),
A computer device for stopping the CPU clock (107).