JPH11135054A - Charged particle beam device with parallel image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charged particle beam device for a wide range of use which can execute not only basic image processing but also quickly execute an image processing requiring higher degree of computation. SOLUTION: An image processing part is additionally equipped with a parallel image processor 310 which is composed of a master CPU to control the data transfer and a plurality of slave CPU's to perform computational processing of the data. The computing program to serve for image processing is down- loaded from a computer for controlling 110 to the master CPU and slave CPU's. The number of parallel CPU's used in the parallel image processor 301 is made variable, and the optimum number of parallel CPU's is previously decided according to the contents of processing to be performed. The method of dividing the image data to be processed is made variable according to the sort of image processing and the contents of processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charged particle beam apparatus for observing and inspecting a sample using a charged particle beam such as an electron beam or an ion beam.

[0002]

2. Description of the Related Art An electron microscope apparatus, an inspection apparatus for enlarging and inspecting a pattern formed on a semiconductor wafer or the like by an electron microscope, or a FIB using an ion beam.
(Focused ion beam) image obtained by a charged particle beam device such as a secondary electron emitted from a sample,
Since the sample signals of reflected electrons and transmitted electrons are weak,
The S / N ratio is extremely poor as compared with an image captured by a normal television camera or the like. Therefore, in order to improve the S / N ratio of the image, the detection signal is subjected to image processing such as cumulative averaging processing or recursive averaging processing for each pixel or frame by the image processing processor. Also, for automatic adjustment control of hardware such as automatic focusing, image processing techniques such as differential processing and histogram processing are used in order to obtain a feature amount representing a focus shift as a control index from an image. .

[0003] As described above, the image processing technique in the charged particle beam apparatus is an indispensable technique not only for improving the image quality of an obtained image but also for controlling the charged particle beam apparatus. 2. Description of the Related Art Conventionally, an image processor provided in a charged particle beam apparatus has been made by combining dedicated circuits that perform only individual processing at high speed in order to realize high-speed processing at low cost. Therefore, in the case of a complicated process that cannot be realized by a dedicated circuit or a process in which a dedicated circuit is not prepared, it is necessary to temporarily capture image data into a high-speed arithmetic device such as a personal computer and perform the process using software.

[0004]

As described above, the image processor provided in the conventional charged particle beam apparatus has a specific processing function such as a filtering function, a histogram processing function, a differentiation processing function, and a correlation operation processing function. Since it was a collection of dedicated circuits capable of executing only the processing functions at high speed, the functions of the image processor were not flexible.

Recently, a charged particle beam apparatus represented by an electron microscope apparatus has been widely applied not only to sample observation but also to automatic measurement and inspection in the semiconductor field in particular.
As for the contents of image processing to be processed at high speed, advanced arithmetic processing for processing large amounts of data at high speed, such as correlation processing and fast Fourier transform, has been required. When performing such advanced arithmetic processing with a conventional charged particle beam device,
The processing is performed by the main computer for control, or the processing is performed by transferring data to an external computer capable of high-speed processing. However, if the main computer for control is used for the image arithmetic processing, it takes a long processing time, and if an external computer is used to perform the arithmetic operation, it takes a long time for data transfer.

The present invention has been made in view of the present situation of such a charged particle beam apparatus, and requires not only basic image processing such as filtering and differentiation but also advanced calculations such as fast Fourier transform. SUMMARY OF THE INVENTION It is an object of the present invention to provide a charged particle beam apparatus which can execute image processing at high speed and has a wide application.

[0007]

According to the present invention, a parallel image processing processor comprising one master CPU and a plurality of slave CPUs is added to the image processing portion of the charged particle beam apparatus, so that the image processing operation can be performed at high speed. The above object is achieved by executing the program in parallel. That is, the present invention provides means for irradiating a sample with a charged particle beam, sample signal detection means for detecting a sample signal emitted from the sample, and AD conversion means for converting a detection signal of the sample signal detection means into a digital signal. A basic image processing means for processing a digital signal from the AD conversion means by a dedicated circuit, an image storage means for storing the signal processed by the basic image processing means as image data, and an image data stored in the image storage means. A charged particle beam apparatus having a display means for displaying, a master CPU and a plurality of slaves C
And a parallel image processing means including a PU, wherein the parallel image processing means transfers the image data stored in the image storage means, and the master CPU processes the transferred image data in parallel by a plurality of slave CPUs. It is characterized in that it is controlled to be performed.

[0008] The image data processed by the parallel image processing means is transferred to the image storage means and displayed on the display means. The master CPU controls data transfer to the slave CPU,
The slave CPU performs arithmetic processing on data sent from the master CPU. A program for performing image processing in the parallel image processing means is downloaded from the control computer to the master CPU and the slave CPU.

Slave C used in parallel image processing means
Means for making the number of PUs variable and means for finding the optimum number of slave CPUs according to the contents of processing can be provided. There can be provided means for changing the content according to the content. These means can be realized as one function of the control computer.

[0010] The charged particle beam apparatus of the present invention can have a function of performing automatic inspection and automatic measurement of a fine pattern on a sample. According to the present invention, by adding a parallel image processor composed of one master CPU for controlling data transfer and a plurality of slave CPUs for performing data arithmetic processing to the image processing portion, advanced image processing such as fast Fourier transform can be performed. Image processing operations can also be executed at high speed. Here, by providing a basic image processing means for processing a digital signal from the AD conversion means by a dedicated circuit and a parallel image processing means including one master CPU and a plurality of slave CPUs, real-time processing is enhanced. The relatively simple image processing can be performed by the basic image processing means, and the complicated and advanced image processing can be performed by the parallel image processing means. Can be satisfied. Also,
It is possible to easily cope with future higher image processing requirements by changing only the parallel processing means.

An arithmetic program for image processing is executed by a control computer by a master CPU and a slave CPU.
By downloading the program, the arithmetic processing is executed by a program. This makes it possible to perform not only basic image processing but also image processing that requires advanced and various operations such as fast Fourier transform at high speed, and makes charged particle beam devices such as electron microscope devices versatile. be able to.

Further, there are provided means for varying the number of slave CPUs used in the parallel image processor and means for determining an optimum number of slave CPUs in advance according to the contents of the processing, and division of image data to be processed. By providing means for changing the method in accordance with the type of image processing and processing content, image processing can be performed efficiently and processing time can be reduced.

According to the present invention, it is possible to realize a charged particle beam apparatus such as an electron microscope apparatus capable of performing high-speed automatic inspection and automatic measurement processing of fine patterns such as semiconductor patterns.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. Here, an electron microscope apparatus will be described as an example. FIG. 1 is a block diagram showing a schematic configuration of an electron microscope apparatus according to the present invention equipped with a parallel image processor. The electron microscope 102 includes an electron gun 102, an electron lens (not shown), a deflector 104 for moving an electron beam irradiation position, a sample 105, and secondary electrons and the like emitted from the sample by electron beam irradiation. An electronic detector 106 as a sample signal detector for detecting a sample signal is arranged. Electron beam 103 emitted from electron gun 102
Are converged by an electron lens (not shown), and the sample 10
5 is irradiated. The electron beam 103 is connected to the control computer 110
Is raster-scanned on the surface of the sample 105 by the action of the deflector 104 controlled by the control signal 108. The intensity of secondary electrons or reflected electrons generated from the sample surface by electron beam irradiation is detected by the electron detector 106 and amplified by the amplifier 107.

The signal output from the amplifier 107 is AD-converted in the image processor 109 to create digital image data. Also, the image processor 109
Includes an image memory for storing digital image data, an image processing circuit for performing various types of image processing, and a display control circuit for performing display control. The image data stored in the image memory is
It is displayed on the display device 111. Image processing processor 10
Reference numeral 9 denotes a basic image processing processor that performs basic image processing using a dedicated circuit, and a parallel image processing processor that includes a plurality of CPUs and performs image processing according to a program loaded into each CPU. Input means 112 such as a keyboard and a mouse is connected to the control computer 110.

FIG. 2 is a schematic diagram showing an example of a parallel image processor according to the present invention. This parallel image processor includes one master CPU 202 and a plurality of slave CPUs 204. The master CPU 202 has an image memory 203, and each slave CPU 204 image has a memory 205. The master CPU 202 mainly controls data transfer to the slave CPU 204, and the slave CPU 204 performs an arithmetic process on the transmitted data.

The image processing in the parallel image processor is executed by downloading an image processing program from the control computer 201 to the master CPU 202 and the slave CPU 204. That is, the master CPU 202
Executes a predetermined program in accordance with an instruction from the control computer 201 and transfers image data to the slave CPU 204. The slave CPU 204 is the master CPU 20
A predetermined program is executed by the control and data transfer from 2 to perform arithmetic processing.

FIG. 3 is a schematic diagram showing the configuration of the image processor 109 according to the present invention. As shown in FIG. 3, the image processor 109 in FIG. 1 includes a parallel image processor 301 together with a basic image processor 303 similar to that provided in a conventional electron microscope apparatus. The basic image processing processor 303 includes a basic image processing circuit 304 that implements basic image processing such as filter processing and differentiation processing using dedicated circuits, and an image memory 305.
And a display control circuit 307. The parallel image processing processor 301 has a parallel image processing circuit 302 including a master CPU, a slave CPU, a memory, and the like as shown in FIG.

The image signal input to the image processor 109 is A / D converted by an A / D converter 306 to be a digital signal.
The image data obtained by the processing by the basic image processing circuit 304 is transferred to the image memory 305 and stored. The image data stored in the image memory 305 is sent to a display device 308 such as a CRT through a display control circuit 307 and displayed on the display device 308.

Here, when performing advanced image processing operations such as fast Fourier transform, the parallel image processor 301
Performs the processing. The parallel image processing circuit 302 of the parallel image processing processor 301 performs necessary processing on the image data transferred from the image memory 305, and transfers the result to the image memory 305 for storage. Image memory 30
The image stored in 5 is displayed on the display device 308 via the display control circuit 307. An arithmetic program for image processing is sent from the control computer 110 to the parallel image processing circuit 3.
02 is downloaded to the master CPU and the slave CPU and executed. In other words, since the image processing operation is performed by software, any processing can be supported as long as the software is changed.
Since parallel processing is performed, a large amount of data can be processed at high speed.

FIG. 6 is a diagram for explaining a method of dividing image data processed by the parallel image processor. FIG.
(A) shows one frame of image data 601 in the column direction,
It is explanatory drawing of the division | segmentation method of dividing into 4 vertically. This division method is a division method suitable for processing in which the continuity of data must be strongly preserved in the vertical direction and processing unrelated to the x direction, such as y-direction differentiation processing. On the other hand, FIG. 6B is an explanatory diagram of a dividing method in which one frame of image data 602 is horizontally divided into four in the row direction. This division method is a division method suitable for processing in which the continuity of data must be strongly preserved in the horizontal direction or processing irrelevant to the y direction, such as x-direction differentiation processing. As described above, according to the present invention, the dividing method can be changed according to the content of the processing.

The selection of the division method is performed by preparing a file describing a division method suitable for the type of image processing in the storage device of the control computer 110 in advance, and referencing the file for each processing. It is convenient to configure to select automatically. Alternatively, a division method for the image processing may be designated from the input unit 112 according to the type of the image processing.

FIG. 4 is a time chart of data processing executed by the parallel processing processor of the present invention. FIG.
The figure shows a case where a frame is divided into four and processed by four slave CPUs (slave CPU1 to slave CPU4). As shown in FIG. 6A, one frame is
In the case of division, data of a quarter row in the section 401 of the time chart is transferred from the master CPU to the slave CPU 1.
When one frame is horizontally divided into four as shown in FIG. 6B, a quarter is obtained in the section 401 of the time chart.
The data for the frame is sent to the slave CPU 1. The slave CPU 1 receives the data in the section 408. The slave CPU 1 performs image processing of the received data in the section 409, and returns the processing result to the master CPU in the section 410. The master CPU receives the processing result in the section 406. After that, the master CPU
The next data is sent to PU1 in section 407. The slave CPU 1 receives the data in the section 411 and repeats the same processing. A section 402 in the figure is a stop time s used for transmission / reception overhead, and a section 405
Is a waiting time w generated when the image processing time is longer than the data transfer time.

An image of one frame is composed of M × N pixels (N is a column matrix, M is a row matrix), data transfer time per pixel is tr, processing time per pixel is f,
When the number of divisions is h, the sections 401, 406, 407,
The time of 408, 410, 411 is calculated by N × tr / h. Further, the time of the section 409 during which the slave CPU 1 performs the image processing is calculated by the following equation (Equation 1).

[0025]

(Equation 1) The slave CPU 2 transmits the calculation result to the master C in the section 412.
Returning to the PU, the master CPU receives the processing result in the section 403. The next data transfer from the master CPU to the slave CPU 2 is performed in the section 404, and the slave CPU 2
Receives the data in the section 413. Data transfer to other slave CPUs and master CPU for image processing results
A reply to is also made in the same way.

FIG. 5 is a diagram showing the relationship between the overall processing time (data processing time for one frame) of the parallel image processing processor of the present invention and the processing time per pixel. The parameters are the number of divisions h = 4 (indicated by ▲ in the figure), 6 (indicated by ■ in the figure), 8 (indicated by ● in the figure), image matrix M ×
N = 1000 × 1000, transfer time per pixel tr =
40 ns and overhead time s = 1 μs. The processing time f per pixel is an amount determined by the number of steps of the CPU required for the processing, and can be calculated once the content of the processing is determined. The control computer 110 has values such as a transfer time tr per pixel, an overhead time s, and a processing time f per pixel as a table in association with the type of processing.

Referring to FIG. 5, the processing time per pixel is 2
When the number is 80 ns or less, the total processing time when the number of divisions is 4 is the shortest. Also, the processing time per pixel is 280
ns to 480 ns, the total processing time when the number of divisions is 6 is the shortest, and the processing time per pixel is 48
If it exceeds 0 ns, the total processing time is the shortest when the number of divisions is set to 8, which is the maximum number of divisions in the example of FIG. That is, when the processing time per pixel is short, even if the number of divisions is large, the overall processing time is not necessarily short, and it can be seen that there is a number of divisions that can minimize the overall processing time. In the conventional parallel image processing processor, the number of divisions (the number of CPUs used) is always constant, so that the entire processing time may be extended depending on the processing state.
In the present invention, the total processing time can be efficiently reduced by optimizing the number of data divisions according to the state of image processing.

Next, a description will be given of a method of calculating the optimum number of divisions of image data to be processed by the parallel image processor by calculation. First, a case in which one frame of image data is vertically divided as shown in FIG. First, it is determined from the state parameter of the image processing whether the following conditional expression (Equation 2) holds. Here, h is a slave CPU provided in the parallel processing image processor.
Is the total number of

[0029]

(Equation 2) When the conditional expression [Equation 2] is not satisfied, the overall processing time when all the equipped slave CPUs are used is the shortest. That is, the number of divisions is h. When the state of the image processing satisfies the conditional expression [Equation 1], the parameters on the hardware and software at that time are substituted into the following [Equation 3], and the optimal division number h can be obtained. Here, [] is a Gaussian symbol, and min [] represents a minimum integer value equal to or larger than a value obtained by calculation.

[0030]

(Equation 3) Next, a case where one frame of image data is horizontally divided as shown in FIG. 6B will be described. First, it is determined whether or not the following conditional expression [Equation 4] is satisfied from the state parameters of the image processing. Here, h is the total number of slave CPUs provided in the parallel processing image processor.

[0031]

N × f−2 (h−1) (N × tr + s) + s <0 When the conditional expression [Equation 4] is not satisfied, the total processing time when all the equipped slave CPUs are used. Is the shortest. That is, the number of divisions is h. When the state of the image processing satisfies the conditional expression (Equation 4),
By substituting the parameters on the software into the following [Equation 5], the optimum division number h can be obtained. Here, [] is a Gaussian symbol, and min [] represents a minimum integer value equal to or larger than a value obtained by calculation.

[0032]

(Equation 5) The control computer 110 calculates the relationship between the processing time per pixel and the overall processing time shown in FIG.
The conditional expression of [Equation 5] and the arithmetic expression of the optimal division number are held, and the division number of the image data is determined according to the content of the image processing. The control computer 110 transmits the number of divisions of the image data to the master CPU 202 of the parallel image processing circuit 304. If the number of divisions is smaller than the number of the slave CPUs 205 provided in the parallel image processing circuit 304, the control computer 110 executes the parallel image processing. Specify the slave CPU to be used. Master CPU2
02 transfers the image data to a predetermined slave CPU according to the data division number transmitted from the control computer 110 and the instruction of the slave CPU to be used.
Receive data processed in U. As described above, by performing the parallel image processing by optimizing the number of data divisions according to the state of the image processing, it is possible to efficiently reduce the entire processing time.

FIG. 7 is a processing flow of an automatic positioning process which is an example of image processing using the parallel image processor of the present invention. When using a scanning electron microscope to measure the line width and contact hole diameter of a circuit pattern in the manufacturing and inspection processes of semiconductor devices, pattern matching using normalized correlation is a method of automatically searching for the measurement target. A method can be used.

In the initial setting of step 701, image parameters such as a matrix of the image to be searched (matrix size) are set. Next, in step 702, a template corresponding to the position to be detected is registered. In the pre-processing of step 703, image input and image processing such as signal enhancement are performed on the input image. Specifically, a local average filter for smoothing is used for noise removal, and a spatial differentiation process is used for signal enhancement. These pre-processing is performed by the basic image processing circuit 304 shown in FIG. In step 704, a matching process (automatic positioning process) is performed on the preprocessed image. In step 705, a portion having the highest similarity with the template is displayed from the correlation value calculated by the matching process.

In the matching process, a normalized correlation process is often used at present because a stable similarity determination can be expected without being affected by the level and contrast fluctuation of the input image. In the normalized correlation, although the degree of position detection is improved, the amount of data to be calculated increases, and speeding up is an essential condition for practical use. In the past, in order to speed up this correlation processing, a method of adding expensive dedicated hardware was used, but since it is dedicated hardware,
In addition to being expensive, there is no flexibility in the processing contents, and it is not possible to cope with applied calculations. Further, a method of performing software processing by a control computer or a personal computer has been proposed. However, although there is a degree of freedom in processing contents, the problem of processing speed could not be sufficiently solved.

The present invention solves these problems,
As shown at 302 in FIG. 3, a parallel image processing circuit composed of a plurality of CPUs is added. Input image matrix: 640 × 480, template matrix: 64 × 64, reduction thinning rate: 1/4, parallel processing CP
Assuming that the number of U: 4, the processing time: 50 ns / (one product sum), and the safety factor for the other calculation time: 3, the processing time of the normalized correlation in the system to which the parallel processor of the present invention is added Can be estimated as in the following [Equation 6].

[0037]

(Equation 6) In this example, even if the normalized correlation processing includes the preprocessing time,
It can be completed in seconds or less, and can meet the demand for higher speed. As described above, in the system to which the parallel image processor is added, the automatic positioning processing can be executed within a practical time. Also, as another method for speeding up the correlation processing, a fast Fourier transform method or the like is known.
The image processor of the present invention is not dedicated hardware as in the past, but is executed by downloading an arithmetic program from a control computer to a master CPU and a slave CPU, thereby executing advanced and diverse arithmetic processing such as fast Fourier transform. Is also possible. Furthermore, if this processor is used, the template image is stored in advance and the position is measured by template matching, and the time variation of the imaging position is measured by calculating the correlation processing between the temporally continuous image data. In addition, many processes that cannot be practically used due to a problem of processing time, such as obtaining a blur amount of an image by image processing and adjusting the focus position, can be realized.

Although the present invention has been described with reference to the electron microscope apparatus as an example, the present invention is not limited to the electron microscope apparatus.
A charged particle beam device that performs image observation or inspection using a charged particle beam, such as a device that inspects a fine pattern formed on a semiconductor wafer or a liquid crystal panel, and a FIB device that can observe an image while performing fine processing using an ion beam. Generally applicable.

[0039]

According to the present invention, it is possible to provide a versatile charged particle beam apparatus capable of efficiently and efficiently performing not only basic image processing but also image processing requiring advanced computation at high speed. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an electron microscope apparatus according to the present invention equipped with a parallel image processing processor.

FIG. 2 is a schematic diagram showing an example of a parallel image processor according to the present invention.

FIG. 3 is a schematic diagram showing a configuration of an image processor according to the present invention.

FIG. 4 is a data processing time chart executed by the parallel processing processor of the present invention.

FIG. 5 is a diagram showing the relationship between the overall processing time of a parallel image processing processor and the processing time per pixel.

FIG. 6 is a diagram illustrating a method of dividing image data processed by a parallel image processor.

FIG. 7 is a view for explaining a processing flow of automatic positioning processing.

[Explanation of symbols]

101: mirror section of electron microscope, 102: electron gun, 103
.., Electron beam, 104, deflector, 105, sample, 106, electron detector, 107, amplifier, 108, control signal, 109
... Image processing processor, 110 ... Control computer, 111
... Display device, 112 ... Input means, 201 ... Control computer, 202 ... Master CPU, 203 ... Memory, 204 ...
Slave CPU, 205, memory, 301, parallel image processor, 302, parallel image processor, 303, basic image processor, 304, basic image processor, 3
05 image memory, 306 A / D converter, 307 display control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaya Yasukochi 882-Chair, Oaza-shi, Hitachinaka-city, Ibaraki Pref. Inside the Measuring Instruments Division, Hitachi, Ltd. No. 1 Inside Hitachi Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] A means for irradiating the sample with a charged particle beam; a sample signal detecting means for detecting a sample signal emitted from the sample; and an AD converting means for converting a detection signal of the sample signal detecting means into a digital signal. A basic image processing means for processing a digital signal from the AD conversion means by a dedicated circuit; an image storage means for storing the signal processed by the basic image processing means as image data; A charged particle beam apparatus including a display unit for displaying image data, further comprising a parallel image processing unit including one master CPU and a plurality of slave CPUs, wherein the parallel image processing unit is stored in the image storage unit. The image data is transferred, and the master CPU determines that the transferred image data is partially A charged particle beam apparatus characterized by controlling so as to be processed in parallel. 2. The charged particle beam apparatus according to claim 1, wherein the image data processed by said parallel image processing means is transferred to said image storage means and displayed on said display means. 3. The slave CPU according to claim 2, wherein the master CPU is a slave CPU.
The charged particle beam device according to claim 1, wherein data transfer to the slave CPU is controlled, and the slave CPU performs arithmetic processing on the transmitted data. 4. The charging device according to claim 1, wherein a program for performing image processing in said parallel image processing means is downloaded from a control computer to said master CPU and said slave CPU. Particle beam device. 5. The image processing apparatus according to claim 1, further comprising: means for varying the number of slave CPUs used in said parallel image processing means; and means for determining an optimum number of slave CPUs according to the contents of the processing. The charged particle beam device according to any one of claims 1 to 4. 6. The apparatus according to claim 1, further comprising means for changing a method of dividing one frame of image data to be processed in accordance with a type of image processing and processing contents.
A charged particle beam apparatus according to any one of the preceding claims. 7. A function for performing automatic inspection and automatic measurement of a fine pattern on a sample.
The charged particle beam device according to any one of the above items.