JPH11134889A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a flash writing function by which data are written into a plurality of memory cells simultaneously in a semiconductor storage device. SOLUTION: Power supply side sensing amplifier driving signals SAP1 and SAP2 of 2 systems and ground side sensing amplifier driving signals SAN1 and SAN2 are inputted to a sensing amplifier 13. If the level of the signal SAP1 is 'H' and the level of the signal SAN1 is 'L', a bit line BL is driven to a power supply potential and a bit line NBL is driven to the ground potential. On the other hand, if the level of the signal SAP2 is 'H' an the level of the signal SAN2 is 'L', the bit line BL is driven to the ground potential and the bit line NBL is driven to the power supply potential. As the bit line potentials can be set by the sensing amplifier, a circuit which sets the bit line potentials during a flash writing operation and is necessary in a conventional constitution is not necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a flash write function of writing data to a plurality of memory cells at once.

[0002]

2. Description of the Related Art Generally, a semiconductor memory device is externally supplied with a column address and a row address in order to select an arbitrary memory cell from a memory cell matrix in which memory cells are arranged in a matrix. By activating an arbitrary word line according to a given column address and selecting an arbitrary bit line pair according to a given row address, an intersection between the activated word line and the selected bit line pair is obtained. Is selected, and data reading or writing is performed on the memory cell.

In recent years, there has been a demand for speeding up of a semiconductor memory device along with an increase in the speed of a system. For this reason, a semiconductor memory device that realizes “flash write”, which is one of the high-speed modes, has been proposed.

FIG. 16 is a circuit diagram showing a configuration of a conventional semiconductor memory device having a flash write function. FIG.
6, the bit line pair BL, NBL and the four word lines WL
Only the portion where 1, WL2, WL3 and WL4 intersect is shown. Actually, several hundred or more word lines are connected on the same bit line pair, and a memory cell matrix is constituted by a plurality of bit line pairs each connected to a plurality of word lines.

The memory cell block includes a memory cell 51 including a transistor Q51 and a capacitor C51.
And a memory cell 52 including a transistor Q52 and a capacitor C52. The memory cell 51 has a word line W
L1 and the bit line BL.
2 is connected to the word line WL2 and the bit line NBL, and both are supplied with the cell plate potential VCP.

The bit line precharge block controls the bit line pair BL, NBL to the bit line precharge level (1/2) by controlling the bit line precharge signal φBP.
Vcc).

The sense amplifier block includes a bit line pair B
There is a sense amplifier 53 connected between L and NBL.
The sense amplifier 53 includes four transistors Q53, Q5
4, Q55 and Q56. The transistor Q53 has a gate connected to the bit line NBL, a drain connected to the bit line BL, and a transistor Q53.
54 has a bit line N similar to the transistor Q53.
BL, the drain is connected to the bit line BL, and the transistor Q55 has a gate connected to the bit line BL and a drain connected to the bit line NBL,
The transistor Q56 has a gate connected to the bit line BL and a drain connected to the bit line NBL, similarly to the transistor Q55.

The sources of the transistors Q53 and Q55 are supplied with the power supply side sense amplifier drive signal SAP, and the sources of the transistors Q54 and Q56 are supplied with the ground side sense amplifier drive signal SAN. The power supply side sense amplifier drive signal SAP is normally at the same level (１ ／ Vcc) as the bit line precharge level, and transitions to the power supply potential Vcc in the active state. On the other hand, the ground side sense amplifier drive signal SAN is normally at the same level (１ ／ Vcc) as the bit line precharge level, and transitions to the ground potential Vss in the active state.

The bit line selection block selects a pair of bit lines BL and NBL in accordance with an instruction of a bit line selection signal φB provided independently for each bit line. The bit line selection signal φB is used to select a pair of bit lines BL and NBL.
At the time of normal write operation and read operation, it becomes “H” level after the sense amplifier 53 is activated.

From the connection relationship between the data input amplifier and the data output amplifier and the bit line selection block, the bit line BL
Is written into the memory cell 51 connected to the external data DIN, and the bit line NBL
Are written in the memory cell 52 connected to the external data.

[0011] The flashlight block includes:
A flash write circuit 60 composed of transistors Q61 and Q62 is configured. Transistor Q6
Gate signal φR is applied to the gate of 1 and gate signal φP is applied to the gate of transistor Q62. The flash write circuit 60 sets the potential of the bit line pair BL and NBL during the flash write operation, and a similar circuit is configured for each bit line pair.

In the semiconductor memory device shown in FIG. 16, a normal write operation is performed as follows. First, the transistors Q61 and Q61 of the write circuit 60 for flash write
Signals .phi.R and .phi.P input to gate 62 are fixed at "L" level. Next, after an arbitrary word line is activated (the potential is at “H” level), the sense amplifier 53 is operated,
The bit line potential is amplified, and then the bit line selection signal φ
B is set to the “H” level to activate the data input amplifier. With such an operation, data is written to the memory cell.

In such a normal write operation, one write operation performs one write operation on one memory cell.
Only bit data can be written.

For example, when writing external logic "L" data to all memory cells, it is necessary to sequentially select all addresses and write the external logic "L" data to the selected memory cells (1M word address). If there is space, 1,048,576 cycles (= 2 ²⁰ ) are required).

On the other hand, "flash write" is an operation mode in which the same data is simultaneously written to all memory cells on an activated word line, and the operation will be described with reference to FIG.

FIG. 17 shows that an external logic "L" is applied to a memory cell (memory cell 51 in FIG. 16) on word line WL1.
FIG. 9 is a timing chart showing an operation in the case of writing all data at once.

As shown in FIG. 17, after the bit line precharge signal .phi.BP attains "L" level and the precharging of the bit line is completed, the write circuit 60 for flash write is completed.
The gate signal φR of the transistor Q61 is set to “H” level. As a result, the bit line BL in the high impedance state gradually loses the precharged charge through the transistor Q61 and the potential thereof becomes 1/2 Vcc.
To the “L” level.

Next, the potential of the word line WL1 is set to "H" level. At this time, the capacitor C5 of the memory cell 51
Although the charge is supplied from 1 to the bit line BL, the capacitance of the capacitor of the memory cell is generally very small.
The fluctuation of the potential of the bit line BL is very small. Therefore, the write circuit 60 for flash write is
Has almost no effect on the operation of setting the potential of the pixel to the "L" level.

The potential of the bit line BL is set to the "L" level by the transistor Q61 of the write circuit 60 for flash write, and the ground side sense amplifier drive signal SAN transitions from 1/2 Vcc to the ground potential. The operation of transitioning the potential of BL to the “L” level is promoted. On the other hand, the potential of the bit line NBL changes to “H” level when the power supply side sense amplifier drive signal SAP changes from Ｖ Vcc to the power supply potential.

In this manner, the potentials of the bit line BL and the bit line NBL are set to the ground potential Vs regardless of the data written in the memory cell 51 on the word line WL1.
s, the power supply potential Vcc, and "L" data is simultaneously written to the memory cells on the word line WL1 including the memory cell 51.

In FIG. 17, the gate signal φR is set to “H”.
The timing of setting the level is before the activation of the word line WL1, but there is no particular problem even after the activation of the word line WL1 (but before the operation of the sense amplifier).

FIG. 18 shows an external logic "L" for a memory cell (memory cell 52 in FIG. 16) on word line WL2.
FIG. 9 is a timing chart showing an operation when data is written all at once.

Since the memory cell on word line WL2 is connected to bit line NBL, as described above,
External logic and inverted data are written. For example, when writing external logic “L” data, an “H” level charge is written to a memory cell connected to the bit line NBL. Therefore, the bit line N at the time of flash write is
What is necessary is just to set the potential of BL to "H" level. Therefore,
The external logic "L" is simultaneously applied to the memory cells on the word line WL2.
The operation of writing data is the same as the operation shown in FIG. 17 except that the word line WL2 is activated instead of the word line WL1.

FIG. 19 is a timing chart showing the operation when writing external logic "H" data to memory cells on word line WL1 all at once. FIG. 20 shows the word line W
FIG. 11 is a timing chart showing an operation when writing external logic “H” data to memory cells on L2 all at once.

The operation shown in FIGS. 19 and 20 sets gate signal .phi.P to "H" level instead of gate signal .phi.R, ie, sets the potential of bit line NBL to ground, as compared with the operation shown in FIGS. This is the same operation except that the potential is changed to the potential Vss and the potential of the bit line BL is set to the power supply potential Vcc, and the detailed description is omitted.

[0026]

However, the conventional semiconductor memory device has the following problems.

In the conventional semiconductor memory device shown in FIG.
A flash write circuit 60 including transistors Q61 and Q62 is provided for the bit line pair BL and NBL. That is, in order to realize the flash write function, it is necessary to add two elements (transistors) to each bit line pair. Since an actual semiconductor memory device has a number of bit line pairs, (number of bit line pairs × 2) transistors are required to realize the flash write function.

Therefore, there is a problem that adding the flash write function to the semiconductor memory device causes a large increase in the number of elements. In the case of a semiconductor device, an increase in the number of elements leads to a reduction in manufacturing yield and reliability, which is a serious problem.

In view of the above problems, the present invention provides a semiconductor memory device that realizes a flash write function without causing a large increase in the number of elements.

[0030]

Means for Solving the Problems To solve the above-mentioned problems, a solution taken by the invention of claim 1 is a plurality of memories provided at intersections of a plurality of word lines and a plurality of bit line pairs. In a semiconductor memory device including a cell and a plurality of sense amplifiers respectively connected to the plurality of bit line pairs,
The sense amplifier receives at least one of a power-supply-side sense amplifier drive signal and a ground-side sense amplifier drive signal as a two-system input, and sets a bit line pair connected according to the power-supply-side sense amplifier drive signal and the ground-side sense amplifier drive signal. It is assumed that the potential can be set. As a result, the potential of the bit line pair can be set by the sense amplifier, so that the circuit conventionally required for setting the potential of the bit line pair in the flash write operation becomes unnecessary, and the number of elements is greatly increased. The flash light function can be realized without inducing.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the sense amplifier converts the first and second power supply side sense amplifier drive signals and the first and second ground side sense amplifier drive signals. As an input, when the first power supply side sense amplifier drive signal has a high potential and the first ground side sense amplifier drive signal has a low potential, one bit line of the connected bit line pair is While driving to the power supply potential and driving the other bit line to the ground potential, when the second power supply side sense amplifier drive signal becomes high potential and the second ground side sense amplifier drive signal becomes low potential, The one bit line is driven to a ground potential and the other bit line is driven to a power supply potential.

According to the second aspect of the present invention, the sense amplifier comprises:
According to the first and second power supply side sense amplifier drive signals and the first and second ground side sense amplifier drive signals, one of the potentials of the connected bit line pair is driven to the power supply potential and the other is driven to the ground potential. I do. Therefore, since the potential of the bit line pair can be set by the sense amplifier,
A circuit conventionally required for setting the potential of the bit line pair in the flash write operation becomes unnecessary, and the flash write function can be realized without causing a large increase in the number of elements.

According to the third aspect of the present invention, in the first aspect,
The first and second power supply side sense amplifier drive signals and the ground side sense amplifier drive signal are input, and the first power supply side sense amplifier drive signal becomes high potential and the ground When the side sense amplifier drive signal has a low potential, one bit line of the connected bit line pair is driven to a power supply potential and the other bit line is driven to a ground potential while the second power supply When the side sense amplifier drive signal is at a high potential and the ground side sense amplifier drive signal is at a low potential, the one bit line is driven to a ground potential and the other bit line is driven to a power supply potential. I do.

According to the third aspect of the present invention, the sense amplifier comprises:
According to the first and second power supply side sense amplifier drive signals and the ground side sense amplifier drive signal, one of the potentials of the connected bit line pair is driven to the power supply potential and the other is driven to the ground potential. Therefore, since the potential of the bit line pair can be set by the sense amplifier, a circuit conventionally required for setting the potential of the bit line pair in the flash write operation becomes unnecessary, and the number of elements is greatly increased. The flash light function can be realized without inducing.

According to a fourth aspect of the present invention, in the semiconductor memory device of the first aspect, the sense amplifier receives first and second ground-side sense amplifier drive signals and a power supply-side sense amplifier drive signal as inputs, When the first ground-side sense amplifier drive signal has a low potential and the power supply-side sense amplifier drive signal has a high potential, one bit line of the connected bit line pair is driven to the power supply potential and the other bit line is driven. When the second ground-side sense amplifier drive signal goes low and the power supply-side sense amplifier drive signal goes high, the one bit line is driven to ground potential. Drive and drive the other bit line to a power supply potential.

According to the fourth aspect of the present invention, the sense amplifier comprises:
According to the first and second ground side sense amplifier drive signals and the power supply side sense amplifier drive signal, one of the potentials of the connected bit line pair is driven to the power supply potential and the other is driven to the ground potential. Therefore, since the potential of the bit line pair can be set by the sense amplifier, a circuit conventionally required for setting the potential of the bit line pair in the flash write operation becomes unnecessary, and the number of elements is greatly increased. The flash light function can be realized without inducing.

According to a fifth aspect of the present invention, in the semiconductor memory device of the first aspect, the sense amplifier drive signal and the ground side sense amplifier drive signal during a flash operation of writing data to a plurality of memory cells simultaneously. It is assumed that the potential of the connected bit line pair is set according to the amplifier drive signal.

[0038]

Embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, in a memory cell matrix, a bit line pair BL, NBL and four word lines WL1, WL2, W
Only the portion where L3 and WL4 intersect is shown.

The memory cell block includes a transistor Q
A memory cell 11 comprising a capacitor 11 and a capacitor C11;
And a memory cell 12 including a transistor Q12 and a capacitor C12. The memory cell 11 is connected to the word line WL1 and the bit line BL, and the memory cell 12 is connected to the word line WL2 and the bit line NBL, and both are supplied with the cell plate potential VCP.

The bit line precharge block controls the bit line pair BL, NBL to the bit line precharge level (1/2) by controlling the bit line precharge signal φBP.
Vcc).

A sense amplifier 13 composed of four transistors Q13, Q14, Q15, Q16 is connected between the bit line pair BL, NBL. The transistor Q13 has a gate connected to the bit line NBL and a drain connected to the bit line BL, and the transistor Q14 has a gate connected to the bit line NBL and a drain connected to the bit line BL similarly to the transistor Q13.
The transistor Q15 has a gate connected to the bit line BL and a drain connected to the bit line NBL. The transistor Q16 has a gate connected to the bit line BL and a drain connected to the bit line similarly to the transistor Q15. Connected to NBL.

First power supply side sense amplifier drive signal SAP
1 is supplied to the source of the transistor Q13, and the second power supply side sense amplifier driving signal SAP2 is supplied to the transistor Q1.
5 sources. The first ground-side sense amplifier drive signal SAN1 is applied to the source of the transistor Q16, and the second ground-side sense amplifier drive signal SAN2
Is applied to the source of transistor Q14.

The first and second power supply side sense amplifier drive signals SAP1 and SAP2 are normally at the same level (1/2 Vcc) as the bit line precharge level, and transition to the power supply potential Vcc in the active state. On the other hand, the first and second ground-side sense amplifier drive signals SAN1 and SAN2 are usually at the same level (1/2 Vcc) as the bit line precharge level.
, And transitions to the ground potential Vss in the active state.

The bit line selection block selects a pair of bit lines BL and NBL in accordance with an instruction of a bit line selection signal φB provided independently for each bit line. The bit line selection signal φB is used to select a pair of bit lines BL and NBL.
At the time of normal write operation and read operation, it becomes “H” level after the sense amplifier 13 is activated. on the other hand,
During the flash write operation according to the present invention, it remains inactive (“L” level).

Further, based on the connection relationship between the data input amplifier and the data output amplifier and the bit line selection block, the input data DIN is applied to the memory cell 11 connected to the bit line BL.
, While data having a phase opposite to that of the input data DIN is input to the memory cell 12 connected to the bit line NBL.

In the semiconductor memory device according to the present embodiment shown in FIG. 1, the write operation and the read operation are performed by the power supply side sense amplifier drive signals SAP1 and SAP2 divided into two systems.
Except that SAP2 and the ground-side sense amplifier drive signals SAN1 and SAN2, which are divided into two systems, are activated at the same time after the rise of the word line, the operation is the same as the write operation and the read operation in the conventional example, and the detailed description is omitted.

Next, a flash write operation in the semiconductor memory device shown in FIG. 1 will be described.

FIG. 2 is a timing chart in the case where the external logic "L" data (the capacitor of the memory cell is set to "L" level) is flash-written to all the memory cells on the word line WL1 at the same time.

Bit line precharge signal φBP is at "H"
At the time of the level, all the bit lines are precharged to 1/2 Vcc, and the bit line pairs BL and NBL are also precharged to 1/2 Vcc. At this time, the sense amplifier drive signal SA
The potentials of P1, SAP2, SAN1, and SAN2 are all 1 /
2 Vcc.

When bit line precharge signal φBP is at "L"
Level and the precharge of the bit line pair BL and NBL is completed, and then the second power supply side sense amplifier drive signal SAP
2 to “H” level and the second ground-side sense amplifier drive signal SAN2 to “L” level. Then, the charge is extracted from the bit line BL through the transistor Q14 of the sense amplifier 13 and its potential gradually transitions to the “L” level, while the bit line NBL is supplied with charge through the transistor Q15 of the sense amplifier 13 and the potential is “ H ”level.

Next, the potential of the word line WL1 is set to "H" level. At this time, the capacitor C1 of the memory cell 11
Even if the charge stored in 1 moves to the bit line BL through the transistor Q11, the operation of the sense amplifier 13 is not affected. Therefore, regardless of the data written in the memory cell 11, the potential of the bit line BL goes low while the potential of the bit line NBL goes high.

After the potentials of the bit lines BL and NBL have sufficiently become the power supply potential and the ground potential, the second power supply side sense amplifier drive signal SAP2 and the second ground side sense amplifier drive signal SAN2 remain active. By setting the potential of the word line WL1 to the “L” level, external logic “L” data is simultaneously written to all the memory cells on the word line WL1 including the memory cell 11. After the data is written, the second power supply side sense amplifier drive signal SAP2
And return the second ground-side sense amplifier drive signal SAN2 to the inactive state (1/2 Vcc). The flash write operation is realized by the above operation.

The word line WL1 is activated (the potential is at "H" level) before the activation of the second power supply side sense amplifier drive signal SAP2 and the second ground side sense amplifier drive signal SAN2. There is no problem at all. In addition, the second power supply side sense amplifier drive signal SAP2 and the second ground side sense amplifier drive signal SAN2 do not always need to transition simultaneously. Further, the first power supply side sense amplifier drive signal SAP1 and the first ground side sense amplifier drive signal S1
The potential of AN1 may be kept at 1/2 Vcc, and there is no need to activate it.

FIG. 3 is a timing chart in the case where external logic "L" data is simultaneously flash-written to memory cells on word line WL2.

As described above, in the memory cells on the word line WL2 including the memory cells 12, data whose phase is opposite (extra phase) to the external logic is written to the capacitor. Therefore, when writing external logic "L" data, the capacitor of the memory cell on word line WL2 may be set to "H" level, so that bit line NBL at the time of flash write is written.
May be set to the “H” level. Therefore, the operation in this case is the same as the operation shown in FIG. 2 except that the selected word line is changed from WL1 to WL2 as shown in FIG. 3, and the detailed description is omitted here.

FIG. 4 is a timing chart in the case where external logic "H" data (the capacitor of the memory cell is set to "H" level) is simultaneously flash-written to the memory cells on the word line WL1.

Bit line precharge signal φBP is at "H"
In the case of the level, it is the same as the case shown in FIG.

When bit line precharge signal φBP is at "L"
Level and the bit line precharge ends.
Of the power supply side sense amplifier drive signal SAP1 at "H" level and the first ground side sense amplifier drive signal SAN1.
1 is set to the “L” level. Then, a charge is supplied to the bit line BL through the transistor Q13 of the sense amplifier 13, and the potential of the bit line BL gradually transitions to the “H” level.
The bit line NBL is connected to the transistor Q1 of the sense amplifier 13.
The electric charge is discharged through 6, and the potential of the electric charge changes to "L" level. Therefore, regardless of the data written in the memory cell 11, the potential of the bit line BL goes high while the potential of the bit line NBL goes low. Subsequent operations are the same as the operations in FIG. 2, and a description thereof will not be repeated.

As in the case shown in FIG. 2, the word line WL1 is connected to the first power supply side sense amplifier drive signal SAP1.
There is no problem if the signal is activated before the activation of the first ground-side sense amplifier drive signal SAN1 (the potential is at the “H” level) or activated later. Further, the first power supply side sense amplifier drive signal SAP1 and the first ground side sense amplifier drive signal SAN1 do not always need to transition simultaneously. Furthermore, the second power supply side sense amplifier drive signal SAP2 and the second ground side sense amplifier drive signal SA
The potential of N2 may be kept at 1/2 Vcc, and need not be activated.

FIG. 5 is a timing chart in the case where external logic "H" data is simultaneously flash-written to memory cells on word line WL2.

As already described, data of a logic (inverted phase) opposite to the external logic is written into the memory cells on the word line WL2 including the memory cells 12. Therefore, when writing external logic "H" data, the capacitor of the memory cell on word line WL2 may be set to "L" level.
May be set to the “L” level. Therefore, the operation in this case is the same as the operation shown in FIG. 4 except that the selected word line is changed from WL1 to WL2 as shown in FIG. 5, and the detailed description is omitted here.

As described above, according to the present embodiment, the sense amplifier of each bit line pair is supplied with a power supply side sense amplifier drive signal and a ground side sense amplifier drive signal, each of which has two inputs. The configuration in which the potential of the bit line pair can be set by the signal and the ground side sense amplifier drive signal eliminates the need for a flash write transistor for each bit line, which was conventionally required for performing flash write. Therefore, a flash write operation can be realized without a significant increase in the number of elements.

In the case of the flash write operation in the semiconductor memory device shown in FIG. 1, the sense amplifier drive signal can be activated at an earlier point in time than in the conventional example, so that the speed can be further increased.

(Second Embodiment) FIG. 6 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. The semiconductor memory device according to the present embodiment and the first memory device shown in FIG.
The difference from the semiconductor memory device according to the second embodiment is that both the power supply side sense amplifier drive signal and the ground side sense amplifier drive signal are divided into two systems in the first embodiment, The point is that only the sense amplifier drive signal is divided into two systems. 6, the same reference numerals are given to the same components as those shown in FIG. 1, and the description thereof will be omitted.

A sense amplifier 23 composed of four transistors Q13, Q14, Q15, Q16 is connected between the bit line pair BL, NBL. The transistor Q13 has a gate connected to the bit line NBL and a drain connected to the bit line BL, and the transistor Q14 has a gate connected to the bit line NBL and a drain connected to the bit line BL similarly to the transistor Q13. Q15 has a gate connected to the bit line BL and a drain connected to the bit line NBL, and the transistor Q16 has a gate connected to the bit line BL and a drain connected to the bit line NBL, similarly to the transistor Q15.

First power supply side sense amplifier drive signal SAP
1 is supplied to the source of the transistor Q13, and the second power supply side sense amplifier driving signal SAP2 is supplied to the transistor Q1.
5 sources. Further, the ground side sense amplifier drive signal SAN is supplied to the sources of the transistors Q14 and Q16.

The first and second power supply side sense amplifier drive signals SAP1 and SAP2 are normally at the same level (１ ／ Vcc) as the bit line precharge level, and transition to the power supply potential Vcc in the active state. On the other hand, the ground side sense amplifier drive signal SAN is normally at the same level (１ ／ Vcc) as the bit line precharge level, and transitions to the ground potential Vss in the active state.

In the semiconductor memory device according to the present embodiment shown in FIG. 6, the write operation and the read operation are performed by the power supply side sense amplifier drive signals SAP1 and SAP1 divided into two systems.
Except that SAP2 is activated simultaneously after the rise of the word line, it is the same as the write operation and the read operation in the conventional example, and the detailed description is omitted.

Next, a flash write operation in the semiconductor memory device shown in FIG. 6 will be described.

FIG. 7 is a timing chart in the case where external logic "L" data is simultaneously flash-written to memory cells on word line WL1.

When bit line precharge signal φBP is at "L"
Level and the bit line precharge is completed.
Is set to the “H” level. Then, the transistor Q15 is turned on, and charge is supplied to the bit line NBL through the transistor Q15, and the potential of the bit line NBL gradually transitions to the “H” level. Next, the ground side sense amplifier drive signal SAN is set to “L” level. Then, the transistor Q14 conducts because the potential of the bit line NBL connected to the gate is at the "H" level, and the bit line BL is discharged through the transistor Q14, and its potential gradually transitions to the "L" level. . Therefore, regardless of the data written in the memory cell 11, the potential of the bit line BL goes low while the potential of the bit line NBL goes high. Subsequent operations are the same as in the first embodiment, and a detailed description will be omitted.

The word line WL1 is activated (potential is at “H” level) before or after activation of the second power supply side sense amplifier drive signal SAP2 and the ground side sense amplifier drive signal SAN. There is no problem even if activated. Also, the first power supply side sense amplifier drive signal SAP1
May be left at 1/2 Vcc and need not be activated.

FIG. 8 is a timing chart in the case where external logic "L" data is simultaneously flash-written to memory cells on word line WL2.

As already described, data of a logic (inverse phase) with respect to the external logic is written to the memory cell on the word line WL2 including the memory cell 12. Therefore, when writing external logic "L" data, the capacitor of the memory cell on word line WL2 may be set to "H" level, so that bit line NBL at the time of flash write is written.
May be set to the “H” level. Therefore, the operation in this case is the same as the operation shown in FIG. 7 except that the selected word line is changed from WL1 to WL2 as shown in FIG. 8, and a detailed description is omitted here.

FIG. 9 is a timing chart in the case where external logic "H" data is simultaneously flash-written to memory cells on word line WL1.

After the bit line precharge is completed, the first
Is set to the “H” level. Then, the transistor Q13 is turned on, the charge is supplied to the bit line BL, and the potential thereof gradually transitions to the “H” level. Next, the ground side sense amplifier drive signal SAN
To the “L” level. Then, the transistor Q16
Is turned on because the potential of the bit line BL connected to the gate is at the "H" level, the charge of the bit line NBL is discharged through the transistor Q16, and the potential gradually transitions to the "L" level. Therefore, regardless of the data written in the memory cell 11, the potential of the bit line BL goes high while the potential of the bit line NBL goes low. Subsequent operations are the same as those in the previous embodiments, and a detailed description thereof will be omitted.

Note that there is no problem if the word line WL1 is activated before the activation of the first power supply side sense amplifier drive signal SAP1 and the ground side sense amplifier drive signal SAN, or activated later. . Further, the second power supply side sense amplifier drive signal SAP2 may remain at 1/2 Vcc, and need not be activated.

FIG. 10 is a timing chart when the external logic "H" level is simultaneously flash-written to the memory cells on the word line WL2.

As already described, data of the logic opposite to the external logic (in the opposite phase) is written to the memory cells on the word line WL2 including the memory cells 12. Therefore, when writing external logic "H" data, the capacitor of the memory cell on word line WL2 may be set to "L" level.
May be set to the “L” level. Therefore, FIG.
As shown by 0, the operation in this case is the same as the operation shown in FIG. 9 except that the selected word line is changed from WL1 to WL2, and the detailed description is omitted here.

As described above, according to the present embodiment, the sense amplifier of each bit line pair is supplied with two power supply side sense amplifier drive signals, and the potential of the bit line pair is changed by the power supply side sense amplifier drive signal. By using a configuration that can be set, a flash write transistor is not required for each bit line, which was conventionally required for flash write, and flash write operation can be performed without a large increase in the number of elements. Can be realized.

(Third Embodiment) FIG. 11 shows a third embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment. The semiconductor memory device according to the present embodiment is different from the semiconductor memory device according to the first embodiment shown in FIG.
In this embodiment, both the power supply side sense amplifier drive signal and the ground side sense amplifier drive signal are divided into two systems, whereas in this embodiment, only the ground side sense amplifier drive signal is divided into two systems. . 11, the same reference numerals are given to the same components as those shown in FIG. 1 and the description thereof will be omitted.

A sense amplifier 33 composed of four transistors Q13, Q14, Q15, Q16 is connected between the bit line pair BL, NBL. The transistor Q13 has a gate connected to the bit line NBL and a drain connected to the bit line BL, and the transistor Q14 has a gate connected to the bit line NBL and a drain connected to the bit line BL similarly to the transistor Q13. Q15 has a gate connected to the bit line BL and a drain connected to the bit line NBL, and the transistor Q16 has a gate connected to the bit line BL and a drain connected to the bit line NBL, similarly to the transistor Q15.

The power supply side sense amplifier drive signal SAP is applied to the sources of the transistors Q13 and Q15. Further, the first ground side sense amplifier drive signal SAN1 is provided to the source of the transistor Q16, and the second ground side sense amplifier drive signal SAN2 is provided to the source of the transistor Q14.

The power supply side sense amplifier drive signal SAP is normally at the same level (1/1) as the bit line precharge level.
2 Vcc), and transitions to the power supply potential Vcc in the active state.
On the other hand, the first and second ground-side sense amplifier drive signals SA
Normally, N1 and SAN2 are at the same level (1/2 Vcc) as the bit line precharge level, and transition to the ground potential Vss in the active state.

In the semiconductor memory device according to the present embodiment shown in FIG. 11, the write operation and the read operation are performed by the ground-side sense amplifier drive signal SAN divided into two systems.
Except that the first and SAN2 are simultaneously activated after the rise of the word line, they are the same as the write operation and the read operation in the conventional example, and the detailed description is omitted.

Next, a flash write operation in the semiconductor memory device according to the present embodiment shown in FIG. 11 will be described.

FIG. 12 is a timing chart in the case where external logic "L" data is simultaneously flash-written to memory cells on word line WL1.

When bit line precharge signal φBP is at "L"
Level and the bit line precharge is completed.
Is set to the “L” level. Then, the transistor Q15 is turned on, the charge of the bit line BL is discharged through the transistor Q15, and the potential of the bit line BL gradually transitions to the “L” level. Next, the power supply side sense amplifier drive signal SAP is set to the “H” level. Then, the transistor Q15 conducts because the potential of the bit line BL connected to the gate is at the “L” level, and the charge is supplied to the bit line NBL through the transistor Q15, and the potential thereof gradually transitions to the “H” level. . Therefore, regardless of the data written in the memory cell 11, the potential of the bit line BL goes low while the potential of the bit line NBL goes high. Subsequent operations are the same as those of the embodiment described above.
Detailed description is omitted.

The word line WL1 is activated (“H” level) before the activation of the power supply side sense amplifier drive signal SAP and the second ground side sense amplifier drive signal SAN2.
There is no problem if activated later. The first ground-side sense amplifier drive signal SAN1 is 1 /
It may be kept at 2 Vcc, and need not be activated.

FIG. 13 is a timing chart in the case where external logic "L" data is simultaneously flash-written to memory cells on word line WL2.

As described above, in the memory cells on the word line WL2 including the memory cells 12, data whose phase is reversed (in opposite phase) to the external logic is written to the capacitor. Therefore, when writing external logic "L" data, the capacitor of the memory cell on word line WL2 may be set to "H" level, so that bit line NBL at the time of flash write is written.
May be set to the “H” level. Therefore, FIG.
As shown in FIG. 3, the operation in this case is the same as the operation shown in FIG. 12 except that the selected word line is changed from WL1 to WL2, and the detailed description is omitted here.

FIG. 14 is a timing chart in the case where external logic "H" data is simultaneously flash-written to the memory cells on word line WL1.

When bit line precharge signal φBP is at "L"
After that, the bit line is precharged and the first ground-side sense amplifier drive signal SAN1 is set to "L" level. Then, the transistor Q16 is turned on, the charge is supplied to the bit line NBL through the transistor Q16, and the potential gradually transitions to the “L” level. Next, the power supply side sense amplifier drive signal SAP is set to the “H” level. Then, the transistor Q13 conducts because the potential of the bit line NBL connected to the gate is at the “L” level, and charge is supplied to the bit line BL through the transistor Q13, and the potential gradually transitions to the “H” level. . Therefore, regardless of the data written in the memory cell 11, the potential of the bit line BL goes high while the potential of the bit line NBL goes low. Subsequent operations are the same as in the previous embodiments.
Detailed description is omitted.

It should be noted that there is no problem if the word line WL1 is activated before the activation of the power supply side sense amplifier drive signal SAP and the first ground side sense amplifier drive signal SAN1, or activated later. . Further, the second ground-side sense amplifier drive signal SAN2 may be kept at 1/2 Vcc, and need not be activated.

FIG. 15 is a timing chart in the case where external logic "H" data is simultaneously flash-written to memory cells on word line WL2.

As described above, in the memory cells on the word line WL2 including the memory cells 12, data inverted (in opposite phase) to the external logic is written to the capacitors. Therefore, when writing external logic "H" data, the capacitor of the memory cell on word line WL2 may be set to "L" level.
May be set to the “L” level. Therefore, FIG.
As shown in FIG. 5, the operation in this case is the same as the operation shown in FIG. 14 except that the selected word line is changed from WL1 to WL2, and the detailed description is omitted here.

As described above, according to the present embodiment, the sense amplifier of each bit line pair has two inputs of the ground sense amplifier drive signal, and the potential of the bit line pair is changed by the ground sense amplifier drive signal. By using a configuration that can be set, a flash write transistor is not required for each bit line, which was conventionally required for flash write, and flash write operation can be performed without a large increase in the number of elements. Can be realized.

[0099]

As described above, according to the present invention, since the potential of each bit line pair can be set by the sense amplifier, it is conventionally necessary to set the potential of the bit line pair in a flash write operation. This eliminates the need for a circuit and makes it possible to realize the flash write function without significantly increasing the number of elements.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation when flashing / writing external logic “L” data to a memory cell on a word line WL1 in the semiconductor memory device according to the first embodiment;

FIG. 3 is a timing chart for explaining an operation when flashing and writing external logic “L” data to a memory cell on a word line WL2 in the semiconductor memory device according to the first embodiment;

FIG. 4 is a timing chart for explaining an operation when flashing and writing external logic “H” data to a memory cell on a word line WL1 in the semiconductor memory device according to the first embodiment;

FIG. 5 is a timing chart for explaining an operation when flashing and writing external logic “H” data to a memory cell on a word line WL2 in the semiconductor memory device according to the first embodiment;

FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining an operation when flashing and writing external logic “L” data to a memory cell on a word line WL1 in the semiconductor memory device according to the second embodiment;

FIG. 8 is a timing chart for explaining an operation when flashing and writing external logic “L” data to a memory cell on a word line WL2 in the semiconductor memory device according to the second embodiment;

FIG. 9 is a timing chart for explaining an operation when flashing and writing external logic “H” data to a memory cell on a word line WL1 in the semiconductor memory device according to the second embodiment;

FIG. 10 is a timing chart for explaining an operation when flashing and writing external logic “H” data to a memory cell on a word line WL2 in the semiconductor memory device according to the second embodiment;

FIG. 11 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 12 is a timing chart for explaining an operation when flashing and writing external logic “L” data to a memory cell on a word line WL1 in the semiconductor memory device according to the third embodiment;

FIG. 13 is a timing chart for explaining an operation when flashing and writing external logic “L” data to a memory cell on a word line WL2 in the semiconductor memory device according to the third embodiment;

FIG. 14 is a timing chart for explaining an operation when flashing and writing external logic “H” data to a memory cell on a word line WL1 in the semiconductor memory device according to the third embodiment;

FIG. 15 is a timing chart for explaining an operation when flashing and writing external logic “H” data to a memory cell on a word line WL2 in the semiconductor memory device according to the third embodiment.

FIG. 16 is a circuit diagram showing a configuration example of a conventional semiconductor memory device having a flash write function.

FIG. 17 is a timing chart for explaining an operation when flashing and writing external logic “L” data to a memory cell on a word line WL1 in the conventional example.

FIG. 18 is a timing chart for explaining an operation when flashing / writing external logic “L” data to a memory cell on a word line WL2 in a conventional example.

FIG. 19 is a timing chart for explaining an operation when flashing / writing external logic “H” data to a memory cell on a word line WL1 in the conventional example.

FIG. 20 is a timing chart for explaining an operation when flashing / writing external logic “H” data to a memory cell on a word line WL2 in the conventional example.

[Explanation of symbols]

 WL1, WL2, WL3, WL4 Word line BL, NBL Bit line 11, 12 Memory cell C11, C12 Capacitor Q11, Q12 Transistor 13, 23, 33 Sense amplifier SAP1 First power supply side sense amplifier drive signal SAP2 Second power supply side Sense amplifier drive signal SAP Power supply side sense amplifier drive signal SAN1 First ground side sense amplifier drive signal SAN2 Second ground side sense amplifier drive signal SAN Ground side sense amplifier drive signal Q13, Q14, Q15, Q16 Transistor

Claims (5)

[Claims] 1. A semiconductor memory comprising: a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of bit line pairs; and a plurality of sense amplifiers respectively connected to the plurality of bit line pairs. In the apparatus, the sense amplifier receives at least one of a power supply side sense amplifier drive signal and a ground side sense amplifier drive signal as a two-system input, and connects a bit connected according to the power supply side sense amplifier drive signal and the ground side sense amplifier drive signal. A semiconductor memory device wherein a potential of a line pair can be set. 2. The semiconductor memory device according to claim 1, wherein the sense amplifier receives first and second power supply side sense amplifier drive signals and first and second ground side sense amplifier drive signals as inputs, When the first power supply side sense amplifier drive signal has a high potential and the first ground side sense amplifier drive signal has a low potential, one of the connected bit line pairs is set to the power supply potential. When the second power supply side sense amplifier drive signal goes high and the second ground side sense amplifier drive signal goes low while driving the other bit line to ground potential, Wherein the other bit line is driven to a ground potential and the other bit line is driven to a power supply potential. 3. The semiconductor memory device according to claim 1, wherein the sense amplifier receives first and second power-supply-side sense amplifier drive signals and a ground-side sense amplifier drive signal, and receives the first power supply side. When the sense amplifier drive signal becomes high potential and the ground side sense amplifier drive signal becomes low potential, one bit line of the connected bit line pair is driven to the power supply potential and the other bit line is grounded. Drive to the potential while the second
When the power supply side sense amplifier drive signal becomes high potential and the ground side sense amplifier drive signal becomes low potential, the one bit line is driven to the ground potential and the other bit line is driven to the power supply potential. A semiconductor memory device characterized by the above-mentioned. 4. The semiconductor memory device according to claim 1, wherein said sense amplifier receives first and second ground-side sense amplifier drive signals and a power-supply-side sense amplifier drive signal, and said first ground side. When the sense amplifier drive signal becomes low potential and the power supply side sense amplifier drive signal becomes high potential, one bit line of the connected bit line pair is driven to the power supply potential and the other bit line is grounded. Drive to the potential while the second
When the ground side sense amplifier drive signal goes low and the power supply side sense amplifier drive signal goes high, the one bit line is driven to the ground potential and the other bit line is driven to the power potential. A semiconductor memory device characterized by the above-mentioned. 5. The semiconductor memory device according to claim 1, wherein in a flash operation of writing data to a plurality of memory cells at a time, a sense amplifier operates in accordance with a power supply side sense amplifier drive signal and a ground side sense amplifier drive signal. A semiconductor memory device for setting a potential of a connected bit line pair.