JPH11134857A - Storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent DRAMs mounted on a memory board or memory module from going to a refresh mode all at once, resulting in the temporary flow of a high current causing overlapped power noises. SOLUTION: The storage has a decode chip 20 comprising a circuit 22 for judging a refresh mode, based on input control signals RE, CE and signal switching circuit 24 for generating control signals shifted in time to be fed to dynamic RAMs 11A-11D when the circuit 22 judges the mode to shift the dynamic RAMs 11A-11D to a self refreshing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage technology and a technology effective when applied to a refresh control method in a storage device using a dynamic semiconductor memory, for example, a plurality of dynamic RAMs (random access memories). The present invention relates to a technology that is effective when used in a memory board or a memory module equipped with a device.

[0002]

2. Description of the Related Art A plurality of dynamic RAMs (hereinafter referred to as DR)
There is provided a memory board or a memory module on which a semiconductor chip (hereinafter, referred to as a decode chip) including a decoder for generating a control signal for each DRAM and a control signal for each DRAM is mounted. Conventionally, in such a memory board or memory module, a decode chip generates a signal indicating which of the DRAMs is selectively operated based on an upper bit of an address signal supplied from the microprocessor, or receives a signal supplied from the microprocessor. A signal for providing a refresh timing is generated based on control signals such as a chip enable signal CE, a read enable signal RE, a row address strobe signal RAS, and a column address strobe signal CAS, and the DRA
M.

[0003]

In a conventional memory board or memory module on which the above-described decode chip is mounted, a control signal for shifting a plurality of DRAMs to the refresh mode when the refresh mode is entered. Was given at the same time. for that reason,
It has been clarified that a plurality of DRAMs enter the refresh mode at the same time, a large current flows temporarily, and there is a problem that the power supply noise is duplicated to deteriorate the characteristics. Such a problem becomes more remarkable as the number of DRAMs mounted on a memory board or a memory module increases.

An object of the present invention is to provide a memory board or a memory module having a plurality of DRAMs, in which the plurality of DRAMs simultaneously enter a refresh mode and a large current flows temporarily to cause power supply noise to overlap. In order to improve reliability.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a memory board or a memory module equipped with a plurality of dynamic RAMs and a decode chip for generating a control signal for each dynamic RAM, a circuit for determining a refresh mode based on an input control signal, R
When a mode for shifting the AM to the self-refresh operation is determined, a circuit that generates a control signal supplied to a plurality of dynamic RAMs with a time lag is provided in the decode chip. As a result, a plurality of dynamic RAMs simultaneously start a refresh operation and a large current temporarily flows, thereby preventing power supply noise from being generated repeatedly.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory module to which the present invention is applied. In this specification, a memory module is one in the same manner as a memory board.
This includes a printed circuit board on which a plurality of memory chips are mounted and which has a relatively small board, and a printed circuit board on which a plurality of memory chips are incorporated in one package.

In FIG. 1, reference numeral 10 denotes one printed circuit board; 11A, 11B, 11C and 11D each a DRAM having a storage capacity of, for example, 16 Mbits;
Generates a row address strobe signal RAS as a control signal for the DRAMs 11A to 11D based on control signals such as a chip enable signal CE and a read enable signal RE supplied from a microprocessor and upper two bits An and An-1 of an address. This is a decoding chip to be supplied. The chip enable signal CE supplied from the microprocessor is used as the column address strobe signal CAS as each of the DRAMs 11a to 11a.
It is configured to be commonly input to 1D.

For each of the DRAMs 11A to 11D, the row address strobe signal RAS and the column address strobe signal CAS are control signals for giving timings for fetching a row address and a column address supplied from the microprocessor in a time-division manner. Each D
Each of the RAMs 11A to 11D has a built-in refresh control circuit that determines a refresh mode based on the row address strobe signal RAS and the column address strobe signal CAS, and performs refresh by setting a word line to a selected level.

Each refresh control circuit has a built-in address counter, and each time the refresh mode is entered, one is set.
One is a sequential refresh mode in which one word line is selected and refreshed, and the other is a self-refresh mode in which a plurality of word lines are sequentially selected and refreshed.
It is configured to execute two modes. These two types of refresh modes are determined by the fall of the CAS signal (CE signal) and then the fall of the RAS signal (RE signal), as in the later-described decode chip, and The low level of the RAS signal is maintained for a predetermined time tRASS (for example, 10 to 100 μm).
S) It is configured to enter the self-refresh mode when it is held above.

Each of the DRAMs 11A to 11D is connected to a common address bus 31 and data bus 32, and is provided with an input / output terminal 1 provided on one side of the printed circuit board 10.
It can be connected to a microprocessor or the like (not shown) via the circuits 2 and 13.

The above-mentioned decode chip 20 stores the upper two bits of a row address signal supplied from a microprocessor (not shown).
Bits An and An-1 are decoded and DRAMs 11A-1
Row address strobe signals RAS0-R for 1D
An address decoder 21 that asserts one of AS3 to an effective level such as a low level, and a refresh mode is determined based on a chip enable signal CE and a read enable signal RE supplied from a microprocessor, and a corresponding control signal is determined. A refresh mode control circuit 22 to be generated; a counter 23 updated when a single refresh mode is entered; and a timing instead of the output of the decoder 21 when the refresh mode control circuit 22 determines that the refresh mode is the self-refresh mode. Row address strobe signal RA shifted
And a RAS signal switching circuit 24 for outputting S0 to RAS3. The counter 23 is a 2-bit counter corresponding to the number of DRAMs in the module (four in the embodiment). Therefore, when the number of DRAMs is 8, a 3-bit counter may be used, and when the number of DRAMs is 16, a 4-bit counter may be used.

Further, the refresh mode control circuit 22 detects that the chip enable signal CE supplied from the microprocessor has fallen earlier than the fall of the read enable signal RE, and determines the refresh mode. 41 and a timer for detecting whether or not the low level of the signal RE has continued for a predetermined period of time (for example, 40 μS) when the read enable signal RE has fallen after the chip enable signal CE has fallen. The circuit 42 and the signal RE
Is determined to be in the self-refresh mode when the low level of the signal has continued for a predetermined time or more, and the self-refresh start signal S
And a self-refresh determination circuit 43 for outputting RS.

As shown in FIG. 2, the RAS signal switching circuit 24 generates a signal obtained by sequentially delaying the self-refresh start signal SRS output from the self-refresh determination circuit 43 by a required time Tpd (for example, 40 nS). And a delay circuit DLY1, DLY2, DLY3, and a signal obtained by inverting each of these delay signals and a read enable signal RE by an inverter INV as input signals.
The clocked inverters CIVi (i.e., the gates G0, G1, G2, G3) and the output of the decoder 21 as input signals and controlled by the output signals RASSiB (i = 0, 1, 2, 3) of the NAND gates G0 to G3. i = 0,
1,2,3) and an output signal RASSiB (i = 0,1,2,3) of the NAND gates G0 to G3, the pull-up MOSFET Qpi being on / off controlled.
(I = 0, 1, 2, 3) and the pull-up MOSFET
It is composed of a latch circuit LTi (i = 0, 1, 2, 3) that holds the level set by Qpi, and an output inverter INVi (i = 0, 1, 2, 3).

The delay circuits DLY1, DLY
2 and DLY3, the delay time Tpd is the DRAM 11A
To 11D, the time required for charging / discharging the data lines (for example, 4
0 ns) or more.

Hereinafter, the operation of the memory module of the present embodiment will be described with reference to the timing charts of FIGS.

The memory module of this embodiment operates during a normal read / write operation, that is, a chip enable signal C.
In the case where the read enable signal RE is set to the low level before E, the decoder 21 decodes the upper two bits An and An-1 of the address, thereby
The row address strobe signal RAS for any one of the DRAMs 11A to 11D corresponding to the address is changed to a valid level (low level in the embodiment), and the DRAM to which the valid level RAS signal is input is on the address bus 31 at that time. The address signals A0 to An-2 supplied to the memory cells are taken in to perform a read / write operation. The designation of the read or write operation is performed based on a write enable signal (not shown) separately supplied from the microprocessor.

FIG. 3 shows the timing in the single refresh mode performed based on the read enable signal RE and the chip enable signal CE. As shown in the figure, when the read enable signal RE changes to low level (timing t1) following the change of the chip enable signal CE to low level, the CBR determination circuit 41 in the decode chip 20 determines that the mode is the refresh mode. Then, the counter 23 is reset or counted up (updated) in synchronization with the change of the read enable signal RE to the low level. Then, the decoder 21 decodes the value (for example, “0, 0”) of the counter 23 to change the row address strobe signal RAS0 for the DRAM 11A to a low level, for example. Further, the timer circuit 42 in the decode chip 20 starts counting time.

Subsequently, the read enable signal RE becomes 40
When the level is once changed to the high level within μS and then changed to the low level again (timing t2), the timer circuit 42 in the decode chip 20 is reset once, and the time measurement is started again from "0". Also, the CBR determination circuit 41
Supplies a count-up signal to the counter 23 to update the value of the counter 23 to, for example, “0, 1”.
The decoder 21 decodes this to obtain the DRA
Row address strobe signal RAS1 for M11B
Is changed to the low level.

Similarly, when the read enable signal RE is once changed to the high level and then changed to the low level again (timing t3), the value of the counter 23 is updated to, for example, "1, 0", and the decoder 21 operates. By decoding this, the row address strobe signal RAS2 for the DRAM 11C is changed to a low level.
Further, when the read enable signal RE is changed again to the high level and the low level (timing t4), the value of the counter 23 is updated to, for example, "1, 1" and the DRAM is updated.
Row address strobe signal RAS3 for 11D is changed to low level.

As described above, 4 in module 10
Row address strobe signals RAS0 to RAS3 for the DRAMs 11A to 11D are sequentially changed to low level according to read enable signal RE and chip enable signal CE. And each DR
Each of the AMs 11A to 11D has a built-in CBR determination circuit and a self-refresh determination circuit similar to the decode chip 20, and an address counter of a number of bits capable of selecting all word lines.
The address counter is updated by detecting the change of S0 to RAS3 to the low level, and the corresponding word line is changed to the selected level, whereby the memory cell is refreshed.

FIG. 4 shows the timing in the self-refresh mode performed based on the read enable signal RE and the chip enable signal CE. As shown in the figure, when the read enable signal RE changes to the low level following the change of the chip enable signal CE to the low level (timing t11), the CBR determination circuit 41 in the decode chip 20 determines the refresh mode. Then, the counter 23 is reset or counted up (updated) in synchronization with the change of the read enable signal RE to the low level. Then, the decoder 21 decodes the value (for example, “0, 0”) of the counter 23 to change the row address strobe signal RAS0 for the DRAM 11A to a low level, for example.
Further, the timer circuit 42 in the decode chip 20 starts counting time.

The operation up to this point is the same as the operation in the single refresh mode. Thus, in the case of self-refresh, it is defined that the read enable signal RE is kept at a low level for 100 μS or more. Therefore, the timer circuit 42 does not stop after the elapse of 40 μS, and the self-refresh determination circuit 43 monitors the time measured by the timer circuit 42, and changes the self-refresh start signal SRS to a high level when the elapse of 40 μS (timing t12). .

Then, N in the RAS signal switching circuit 24
The output RAS0B (see FIG. 2) of the AND gate G0 changes to low level, and the corresponding pull-up MOSFET
When Qpi (i = 0) is turned on and the clocked inverter CIVi transmitting the output of the decoder 21 is cut off, the state shifts to a state where the latch circuit LTi holds the high level, and the output inverter INVi (i = 0) goes low. And RASi (i = 0) goes low. However, RAS0 to RAS3 may have already been changed to the low level at the timing t11 due to the output of the decoder 21 that decodes the value of the counter 23. In this case, the low level is maintained.

Next, the self-refresh start signal SRS
At the time point (t13) at which the output signal of the delay circuit DLY1 delays the delay time Tpd after the rise of the SRS signal. Then, the output RAS1B of the NAND gate G1 in the RAS signal switching circuit 24 changes to low level, and the corresponding pull-up MOSFET Qp
When i (i = 1) is turned on, the clocked inverter CIVi (i = 1) transmitting the output of the decoder 21 is cut off, and the latch circuit LTi (i = 1) shifts to a state of holding the high level, The output inverter INVi (i =
1) outputs a low level, and RASi (i = 1) becomes a low level.

Similarly, at the time point (t14) after the elapse of the delay time Tpd, the NA in the RAS signal switching circuit 24 is
The output RAS2B of the ND gate G2 changes to low level, and the corresponding pull-up MOSFET Qpi (i =
2) is turned on and the clocked inverter CI
Vi (i = 2) is cut off and the latch circuit LTi (i = 2)
2) shifts to a state of holding the high level, the output inverter INVi (i = 2) outputs a low level,
(I = 2) is at the low level.

Thereafter, at the time point (t15) after the elapse of the delay time Tpd, the NAN in the RAS signal switching circuit 24
The output RAS3B of the D gate G3 changes to low level, and the corresponding pull-up MOSFET Qpi (i =
3) is turned on and the clocked inverter CI
Vi (i = 3) is cut off and the latch circuit LTi (i = 3)
3) shifts to a state in which the output inverter INVi (i = 3) outputs a low level and
(I = 3) becomes low level.

The row address strobe signals RAS0 to RAS3 changed to the low level are held at the low level for 100 μS or more in response to the read enable signal RE being held at the low level for 100 μS or more. Thereby, each of the DRAMs 11A to 11D
In the above, the self-refresh mode is determined by the internal self-refresh determination circuit, and the self-refresh operation for continuously updating the address counter and sequentially changing all word lines to the selected level is started.

In the above embodiment, as shown in FIG. 4, when the read enable signal RE supplied from the microprocessor or the like is changed from the low level to the high level (timing t16), the self-refresh start signal SRS is changed to the low level. Changed, and each DRAM 11A-1
Row address strobe signal RAS0 supplied to 1D
To RAS3 are simultaneously negated to a high level, but a delay circuit may be provided for the rising edge so as to be shifted.

However, in the DRAM used in the memory module of this embodiment, when the row address strobe signals RAS0 to RAS3 fall and start self-refresh, the data line is precharged to the Vcc level. If all four DRAMs are simultaneously changed to the low level, a relatively large current will flow and noise may overlap. Is simply short-circuited (equalized), so that a large current does not flow as much as when RAS falls. Therefore, there is no problem even if RAS0 to RAS3 are started at the same time as in the embodiment. Conversely, the rise of RAS1 to RAS3 is R
When delayed from AS0, the read enable signal RE falls immediately after the end of the self-refresh, and the read
When shifting to the write operation, erroneous row address strobe signals RAS1 to RAS3 may be formed, which is not desirable.

As described above, in the above-described embodiment, a memory board or a memory module equipped with a plurality of dynamic RAMs and a decode chip for generating control signals for the respective dynamic RAMs is refreshed based on an input control signal. A circuit for determining a mode and a RAS signal switching circuit for generating a control signal supplied to a plurality of dynamic RAMs with a time lag when determining a mode for shifting each dynamic RAM to a self-refresh operation. Since it is provided on the chip, a plurality of dynamic RAMs simultaneously start a refresh operation to temporarily cause a large current to flow, thereby preventing power noise from being generated repeatedly. is there.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the above embodiment, the RAS signal switching circuit 24 is provided after the decoder 21.
It is also possible to provide a circuit corresponding to the signal switching circuit 24.

In the embodiment, the memory module having four DRAMs has been described.
The present invention can be applied to a memory module or a memory board including six DRAMs.

In the above description, the invention made mainly by the present inventor is described in terms of the DRA which is the application field in which the invention is based.
Although the description has been given of the case where the present invention is applied to a memory board or a memory module equipped with M, the present invention is not limited to this, and may be applied to a PC board or a WS board equipped with a DRAM and other semiconductor chips such as a CPU. can do.

[0037]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a memory board or a memory module on which a plurality of DRAMs are mounted, a plurality of DRAMs
However, it is possible to prevent a large current from flowing into the refresh mode all at once and a large amount of current from flowing temporarily, thereby preventing power supply noise from being duplicated and improving reliability.

[Brief description of the drawings]

FIG. 1 shows a plurality of dynamic Rs suitable for applying the present invention.
FIG. 2 is a block diagram illustrating an embodiment of a memory module equipped with an AM.

FIG. 2 is a block diagram showing a specific example of a RAS signal switching circuit which is a main part of the present invention.

FIG. 3 is a timing chart showing a timing of a single refresh operation in the memory module of the embodiment.

FIG. 4 is a timing chart showing the timing of a self-refresh operation in the memory module of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Printed circuit board 11A-11D Memory array (bank) 12 Address input terminal 13 Data input / output terminal 20 Decode chip 21 Decoder 22 Refresh mode control circuit 23 Counter 24 RAS signal switching circuit 31 Address bus 32 Data bus 41 CBR determination circuit 42 Timer Circuit 43 Self-refresh determination circuit DLY1 to DLY3 Delay circuit CIVi Clocked inverter Qpi Pull-up MOSFET LTi Latch circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshihiko Inoue 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Nichicho Cho SSI Engineering Co., Ltd.

Claims (5)

[Claims] In a storage device including a plurality of dynamic semiconductor memories and a decode chip having an address decoder for generating a control signal for each dynamic semiconductor memory, a refresh mode is determined based on an input control signal. A refresh mode control circuit and, when the refresh mode control circuit determines a mode for shifting each of the dynamic semiconductor memories to a self-refresh operation, the plurality of dynamic semiconductor memories in place of the output of the address decoder; A storage device, wherein a signal switching circuit for generating a supplied control signal with a time lag is provided on the decode chip. 2. The decoding chip according to claim 1, wherein said decode chip includes a counter which is updated when said refresh mode control circuit determines a refresh mode based on said input control signal. A storage device as described. 3. The refresh mode control circuit includes a timer circuit for determining whether the input control signal has maintained a significant level for a predetermined time or more, and the significant level is maintained for a predetermined time or more. The signal switching circuit is configured to output a signal for starting a self-refresh mode when the self-refresh mode is started, and a plurality of delay circuits for delaying the self-refresh start signal for a predetermined time; A plurality of logic gate circuits that receive a common signal based on the input control signal as input, and output a signal of a predetermined level instead of interrupting the output of the address decoder based on output signals of these logic gate circuits The storage device according to claim 1, further comprising a circuit. 4. The dynamic semiconductor memory according to claim 1, wherein a row address signal and a column address signal are fetched from the same address terminal in a time-division manner based on a predetermined strobe signal. 4. The storage device according to claim 1, wherein the control signal supplied to the semiconductor memory is a strobe signal for giving a timing of capturing a row address signal. 5. The storage device according to claim 1, wherein said plurality of dynamic semiconductor memories and decode chips are mounted on a single printed circuit board.