JPH11134816A - Coding method, coding device, decoding method, decoding device and information recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable resynchronizing and enable realization of a synchronization code having small correlation with other data by causing a synchronization code to have a detection code part and a bit synchronizing part conforming to a predetermined rule for synchronization at the time of demodulation, and causing the detection code part to be a code arranged immediately before the bit synchronizing part and not satisfying a predetermined rule. SOLUTION: Modulation means 21 constituting a digital data coding device performs (1, 7) modulation on digital inputted thereto, and outputs the modulated data. Synchronization code generation means 22 generates a 24-bit synchronization code made up of an adjustment code part, a detection code part and a bit synchronizing part (code for synchronization). The modulated data and the generated synchronization code are switched by switching means 23. The switching means 23 replaces the output of the synchronization code generation means 22 by code data corresponding to the period of the synchronization code of the modulation means 21, and outputs the resultant data as coded data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording / reproducing apparatus for recording / reproducing digital signals, and more particularly to a digital data encoding / decoding apparatus such as an optical disk apparatus for performing PWM recording.

[0002]

2. Description of the Related Art In recent years, an optical disk device has been put to practical use as a digital information recording / reproducing device having a large capacity and capable of exchanging a medium. In an optical disc apparatus for recording and reproducing such digital data, various types of digital data encoding are performed to realize efficient signal recording and reproduction by realizing signal modulation suitable for the characteristics of a recording and reproducing channel by an optical head and an optical recording medium. / Decoding devices have been put to practical use. As a method of recording and reproducing data in a conventional optical disk device, position modulation (Pit) of a pit as a recording mark is performed.
Position modulation (PPM recording) has been used, but in order to further increase the recording density, the position and length of the recording mark are used for recording information in pit width modulation (Pit Width Modulation).
n, PWM recording). PP
As a modulation rule in the M recording method, (2,7) modulation is excellent, and the PPM recording method using this (2,7) modulation is a place that is also adopted in the international standard (ISO). As part of efforts to improve recording density, PW
In M recording, studies on modulation methods such as (1, 7) modulation have been conducted.

An example of the above-mentioned conventional digital data encoding / decoding device will be described below with reference to the drawings.

[0004] First, in a digital data encoding / decoding device, it is necessary to synchronize a code signal in order to properly demodulate the reproduced signal into binary data after clock reproduction and binarization of the reproduced signal. (Table 1) shows (1, 7)
Here is an example of a modulation rule.

[0005]

[Table 1]

As shown in Table 1, data 2 before modulation
A 3-bit code is assigned to each bit, and a 6-bit code is exceptionally assigned to a 4-bit data sequence. As a result, the number of 0s between 1 is 1 to 1 in the code list for any size data list.
It will be limited to seven. In a modulation method such as the (1, 7) modulation, two to four bits of data are allocated to three or six bits of a code in the reverse demodulation.
It is necessary to synchronize data in units of two bits with respect to bits.

FIG. 7 shows the configuration of a conventional digital data decoding device, and FIG. 8 is a diagram showing signal waveforms for explaining the operation. 7, 1 is a comparator, 2 is a phase locked circuit (Phase Locked L).
3 is a D-type flip-flop (D-FF), 4 is a preamble detector, 5 is a demodulator, and 6 and 7 are gates. The above-described preamble detector 4, demodulator 5, and gates 6 and 7 constitute a digital data decoding unit 8.

In FIG. 7, the input signal is subjected to PWM recording like the pre-modulation data (a) in FIG. 8, and (1, 7)
After modulation (modulation data (b)), NRZI (Non
It is a signal (reproduced signal (d)) in which the code data (modulated data (c)) modulated by Return to Zero-I is recorded and reproduced. Here, digital data is intermittently recorded and reproduced for each specific sector unit, and binarization and clock reproduction are performed as main signal processing during reproduction. This clock recovery is performed by the PLL2.
A preamble portion is provided at the head of the code data for L2 synchronization pull-in. As shown in FIG. 8, data in which 00 is consecutively used as preamble data in the preamble is used.
8-bit data of 100111 # is arranged as a data mark which is a synchronization code for bit synchronization at the time of demodulation. The encoded data actually recorded is modulated data (b)
And (1), (7), and then NRZI-modulated as modulated data (c).

The reproduced signal of the data recorded in this manner has a waveform (d). The comparator 1 binarizes the reproduced signal so as to represent the rising and falling edges of the reproduced signal and outputs binarized data (e). The PLL 2 extracts a clock component from the binary data and outputs a punched clock (f), and the D-type flip-flop 3 synchronizes the binary data with a reproduction clock and outputs the synchronized data. The preamble detector 4 performs a preamble detection operation by a gate signal (g) given according to the recording / reproduction timing of a sector when the reproduction signal is in a preamble period, and outputs {01, 01} modulation code data of (1, 7) modulation code of the preamble part.
The demodulator 5 is transmitted through the gate 6 so that the arrangement of 0 ° is continuous.
Is initialized, that is, the bit synchronization between the aforementioned 3-bit code and 2-bit data is obtained. The demodulated output (h) of the demodulator 5 thus bit-synchronized becomes {00} data as a demodulated output of the preamble portion. When the data mark starts to be demodulated following this preamble,
For the first time, data 01 is generated at the output of the demodulator 5, so that the gate 7 detects this and starts outputting demodulated data.

[0010]

However, in the above method, the data mark can be arranged only at the head of the sector data, and the number of sector data is increased as the recording capacity is increased. In this case, when a bit slip occurs in clock reproduction in the middle of sector data due to a defect of a medium or the like, there is a problem that bit synchronization of demodulation cannot be correctly restored. In addition, when trying to resynchronize bits by arranging data marks periodically in the middle of the sector data, erroneous detection is possible because the data marks described above have a strong correlation with other data. There is a problem that it is highly practical and not practical.

An object of the present invention is to provide a digital data encoding / decoding apparatus capable of resynchronizing and realizing a synchronization code having a small correlation with other data in consideration of the above conventional problems. Is what you do.

[0012]

Means for Solving the Problems The first invention (claim 1)
Is an encoding method for converting digital data into code data according to a predetermined rule and adding a synchronization code for synchronization at the time of demodulation of the code data, wherein the synchronization code includes a detection code part A bit synchronization unit that follows the predetermined rule for synchronization during demodulation, wherein the detection code unit is a code that is arranged immediately before the bit synchronization unit and does not satisfy the predetermined rule. Is an encoding method.

According to a second aspect of the present invention (corresponding to claim 2), the detection code section is a code constructed by breaking the predetermined rule so that the presence of the data can be detected by an array value of the data. This is the first encoding method of the present invention.

According to a third aspect of the present invention (corresponding to claim 3), the synchronization code is a code composed of a bit sequence according to the same clock as the code data. It is.

A fourth invention (corresponding to claim 4) is the encoding method according to the first invention, wherein the synchronization code is constituted by a bit sequence corresponding to two bytes of a digital data sequence. It is.

According to a fifth aspect of the present invention (corresponding to claim 5), a predetermined rule is to convert digital data into code data in which the number of 0s between 1s is changed from d to k (d, k). This is a rule, and 0 between 1 in the code data of the detection code section
Is a set of bit strings whose number is larger than k. The encoding method according to any one of the first to fourth aspects of the present invention.

A sixth aspect of the present invention (corresponding to claim 6) has an adjustment code section immediately before a detection code section, and the adjustment code section is a section where code data obtained by modulating digital data is switched to a synchronous code. Wherein the adjustment is made in accordance with the contents of the code data string in the switching section so that the (d, k) rule is satisfied.
5 is an encoding method according to the present invention.

According to a seventh aspect of the present invention (corresponding to claim 7), the present invention converts digital data into code data according to a predetermined rule, and generates a synchronization code according to the predetermined rule for synchronization at the time of demodulation of the code data. Encoding apparatus, wherein the synchronization code comprises a detection code part and a bit synchronization part for synchronization at the time of demodulation, wherein the detection code is arranged immediately before the bit synchronization part and the predetermined code is provided. Is an encoding device that is a code that does not satisfy the rule.

An eighth aspect of the present invention (corresponding to claim 8) is characterized in that the detection code section is a code constructed by breaking the predetermined rule so that the presence thereof can be detected by an array value of data. This is the seventh encoding device of the present invention.

According to a ninth aspect of the present invention (corresponding to claim 9), the synchronization code is a code composed of a bit sequence according to the same clock as the code data. It is.

A tenth aspect of the present invention (corresponding to claim 10) is:
A coding apparatus according to a seventh aspect of the present invention, wherein the synchronization code is constituted by a bit string corresponding to two bytes of the digital data string.

The eleventh invention (corresponding to claim 11) provides:
The predetermined rule is that the number of 0s between 1s is d.
An (d, k) rule from k to k, wherein the number of 0s between 1 in the code data of the detection code portion is one set of bit strings larger than k. 1 is an encoding device of the invention.

The twelfth invention (corresponding to claim 12) provides:
A first modulating means for converting and outputting digital data so as to become code data modulated according to a (d, k) rule in which the number of 0s between 1 is from d to k, and an adjustment code section;
And a synchronization code generating means for outputting a synchronization code having a bit synchronization unit satisfying the (d, k) rule, wherein the number of detection code units is greater than k.
Switching means for switching between the output of the modulation means and the output of the synchronization code generation means to output encoded data; and second modulation means for performing NRZI modulation on the output of the switching means, and the adjustment code section for the synchronization code. Is an encoding device having an adjustment bit set so that the code of the detection code section is always fixed to 0 or 1 after modulation by the second modulation means.

According to a thirteenth aspect of the present invention (corresponding to claim 13),
A first modulating means for converting and outputting digital data so as to become code data modulated according to a (d, k) rule in which the number of 0s between 1 is from d to k, and a first modulating means thereof A second modulating means whose output is changed by NRZI, an adjustment code section, a detection code section fixed to 0 or 1 and having a length greater than k + 1, and a synchronization code section having a bit synchronization section satisfying the above (d, k) rule And a switching means for switching between the second modulating means and the synchronizing code generating means to output coded data, wherein the adjustment code section comprises a code for an output of the second modulating means. When switching between the data and the synchronization code, the code data up to the detection code section is adjusted according to the output of the second modulation means so as to satisfy the (d, k) rule. An encoding device.

According to a fourteenth aspect of the present invention (corresponding to claim 14),
The length fixed to 0 or 1 of the detection code part is k + 4
The twelfth or first bit string is a set of
3 is an encoding device according to the present invention.

According to a fifteenth aspect of the present invention (corresponding to claim 15),
A decoding device for decoding data encoded by the encoding method according to any one of the first to sixth aspects of the present invention, wherein the decoding device detects a detection code portion that does not satisfy a predetermined rule in the encoded data. Means, when the detection means detects a detection code part, a bit synchronization part detection means for detecting a bit synchronization part following the predetermined code following the detection code part, and bit synchronization part detection of the bit synchronization part detection means And a decoding unit that is initialized in accordance with the following.

According to a sixteenth aspect of the present invention (corresponding to claim 16),
A decoding method for decoding data encoded by the encoding method according to any one of the first to sixth aspects of the present invention, wherein a detection code part that does not satisfy a predetermined rule in the encoded data is detected, A decoding method characterized by detecting a bit synchronization part following the detection code part when detecting the detection code part, and initializing decoding according to the detection of the bit synchronization part.

The seventeenth invention (corresponding to claim 17) provides:
An information recording medium on which a synchronization code for synchronization at the time of demodulation of the code data is recorded by NRZI modulation together with code data obtained by converting digital data according to a predetermined rule, wherein the synchronization code includes a detection code portion, A bit synchronization unit that follows the predetermined rule for synchronization at the time of demodulation, wherein the detection code unit is a code that is disposed immediately before the bit synchronization unit and does not satisfy the predetermined rule. is there.

The eighteenth invention (corresponding to claim 18) provides:
The predetermined rule is that the number of 0s between 1s is d.
An information recording medium according to a seventeenth aspect of the present invention, characterized in that the rule is a (d, k) rule for converting code data into k code data.

The nineteenth invention (corresponding to claim 19) is:
An eighteenth information recording medium according to the present invention, characterized in that the number of 0s between 1s in the code data of the detection code section is a set of k + 3 bit strings.

According to a twentieth aspect of the present invention (corresponding to claim 20),
An adjustment code part is provided immediately before the detection code part, and the adjustment code part is a code data string in the switching part such that a modulation rule is satisfied in a part where code data obtained by modulating digital data is switched to a synchronization code. The first is characterized by being adjusted according to the content of
7, 18 or 19 is the information recording medium of the present invention.

Next, the operation of the present invention will be briefly described.

According to the present invention, a detection code consisting of a code having an appearance frequency of a predetermined level or less in modulated data after modulation is added to a synchronization code of the modulation data to be encoded as a synchronization code.

The digital data is modulated according to the (d, k) rule in which the number of 0s between 1s is changed from d to k (d, k), and the number of synchronization detection codes in which the number of 0s between 1s is larger than k And a synchronization code having a bit synchronization section that satisfies the (d, k) rule adjacent thereto, and switches between modulation data and a synchronization code to output encoded data.

Further, according to the present invention, encoded data is input,
A code for synchronization is detected by detecting, as a detection code, a code whose appearance frequency in the modulation data is equal to or lower than a predetermined level, and the modulation data is demodulated according to the synchronization code.

Also, coded data is input, and 0 between 1
The synchronization code is detected by detecting that the number is larger than k. When the synchronization code is detected, a bit synchronization part adjacent to the synchronization code is detected and a demodulation initialization signal is output. Demodulation means initialized by the initialization signal demodulates the encoded data according to the (d, k) rule.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing an embodiment.

FIG. 1 is a block diagram of a digital data encoding apparatus according to a first embodiment of the present invention. That is,
A digital data encoding device that modulates (1, 7) the input digital data and outputs the result;
Synchronization code generation means 22 for generating a 24-bit synchronization code including an adjustment code part, a detection code part and a bit synchronization part (synchronization code), and switching means for switching between the modulated data and the generated synchronization code 2
3.

Next, the operation of the digital data encoding device according to the first embodiment will be described.

First, as an example of a recording / reproducing format, a digital data string of 384, which is 48 bytes before modulation, is used.
Each of the bits {D0, D1, D2,..., D383} is preceded by a 2-byte 16-bit synchronization code {S0, S1,..., S15}. Shall be located. At this time, the data string Sk [k = 0 to 15] of the part to be replaced with the synchronization code is all set to 0, and the digital data is input to the modulation unit 21. From Table 1, the code data corresponding to the 16 consecutive 0s in the output of the modulating means 21 is always 010010010010010010010010010 regardless of the data sequence before and after it.
010 °. On the other hand, the synchronizing code generation means 22 generates a synchronizing code consisting of the adjustment code part {Aa 0 Ab 0 0} Aa = 0,1, Ab = 0,1, the detection code part {100000000001}, and the bit synchronizing part {0010010}. ｛Aa0Ab00100000000000001001001
Output 0｝. Here, bits Aa and Ab of the adjustment code part
In response to the code data immediately before the synchronization code, code data from the code data to the detection code portion is (d,
k) Adjustment bits 0 or 1 are selected to satisfy the rule. The number of 0s existing from the modulation rule of (Table 1) to 1 of the immediately preceding code data is 0 to 5, and the setting method of the adjustment bits is shown in (Table 2).

[0041]

[Table 2]

Next, the switching means 23 replaces the output of the synchronization code generation means 22 with the code data corresponding to the synchronization code period of the output of the modulation means 21 and outputs it as encoded data.

FIG. 2 is a block diagram of a digital data decoding apparatus according to the first embodiment of the present invention corresponding to the above digital data encoding apparatus. That is, the digital data decoding apparatus includes: a synchronization code detection unit 31 for detecting a synchronization code from input encoded data; a bit synchronization unit 32 for detecting a bit synchronization unit when the synchronization code is detected; Demodulation means 33 for demodulating the coded data according to the (1, 7) rule.

Next, the operation of the digital data decoding apparatus according to the first embodiment will be described.

First, in the encoded data, the number of consecutive 0s between 1 is k +
2, k + 3 or k + 4 is detected and used as the output of the synchronization code detection means 31, and when the output of the synchronization code detection means 31 is obtained, the bit synchronization part following the detection code part is bit synchronized. The procedure of detecting by the means 32 and initializing the demodulation means 33 by the bit synchronization means 32 will be taken. Here, a pattern in which many zeros are continuous like a synchronization code is easily affected by a peak shift. Therefore, as in the present embodiment, the number of zeros in the detection code part recorded as k + 3 is k + 2 or k + 4. However, in this synchronous code detection method, there is no detection error even if such a peak shift occurs. Although the correlation between the synchronization code and the code data is important, the correlation with the code data is small because the detection code portion does not satisfy the (d, k) rule. Further, the number of 0s in the detection code portion is k + 3 = Since it is set to 10, even when k consecutive 0s existing in the code data become k + 1 due to an error such as a peak shift, this is not detected as a synchronization code.

FIG. 3 is a diagram showing a configuration of a digital data encoding device according to a second embodiment of the present invention. That is, the digital data encoding apparatus is provided with a data input terminal and a control input terminal, and the data input terminal is connected to the (1, 7) modulator 9 as the first modulation means, and the (1, 7) The modulator 9 has NRZI as a second modulating means.
The modulator 11 is connected. A gate 10 is connected to the other control input terminal, and NRZ
An I modulator 11 and a synchronization code generator 12 as a synchronization code generator are connected, and further connected so as to control a switch 13 as a switching means for switching between modulated data and a synchronization code. . Also, NR
The output of the ZI modulator 11 is connected to the switch 13 and the synchronization code generator 12, and the output of the synchronization code generator 12 is connected to the switch 13.

Next, the operation of the digital data encoding apparatus according to the second embodiment will be described.

First, the (1, 7) modulator 9 performs (1, 7) modulation on digital data in which all 16 bits corresponding to the synchronization code are given as 0, as described above, and outputs the result. N
The RZI modulator 11 converts the output of the (1, 7) modulator 9 into an NRZ
24 bits of data corresponding to the synchronization code by the gate 10 at the same time as the I-modulated output, # 01001001001001001001001
Initialization is performed so that the latter half of 0 常 に is always fixed as follows.

{XXXXXXXXXXXXXXXXXX00011100} X = 0,1 The gate 10 further activates the synchronous code generator 12, and the activated synchronous code generator 12 has an adjustment code part {AcAc000} Ac = 0,1 and a detection code part {11111111110} And a synchronization code {AcAc0001111111111100011100} consisting of｝ and a bit synchronization unit {0011100} Ac = 0,1 is output. Here, Ac is an adjustment bit, and 0 or 1 is set as shown in (Table 3) according to the data immediately before the synchronization code.

[0050]

[Table 3]

The switch 13 is controlled by the gate 10, and during the period when the synchronization code is generated, the synchronization code generator 1
2 and outputs the output of the NRZI modulator 11 during the other periods. When the digital data thus encoded is recorded on the optical disk device, the code data 1 is recorded so as to correspond to the recording mark and the code data 0 so as to correspond to the space.

As is easily understood, NRZI modulation is performed immediately after (1, 7) modulation, and the synchronization code is
There is no problem even if it is generated in a ZI-modulated form and switched by the switching means 13.

FIG. 4 is a block diagram of a digital data decoding apparatus according to a second embodiment of the present invention. That is,
The digital data decoding device is provided with an input terminal for encoded data. The input terminal is provided with a demodulator 16 as demodulation means for demodulating the encoded data, and a synchronization means as a synchronization code detection means for detecting a synchronization code. Code detector 14;
A bit synchronization detector 15, which is a bit synchronization means for detecting a bit synchronization section when a synchronization code is detected, is connected. The gate 17 that outputs a signal for initialization to the demodulator 16 is connected to the above-mentioned synchronization code detector 14 and bit synchronization detector 15. Further, the demodulator 16, the synchronization code detector 14, and the bit synchronization detector 15 include:
A clock signal is input, and a gate signal is input to the gate 17.

Next, the operation of the digital data decoding apparatus according to the second embodiment will be described.

First, the digital data encoding apparatus according to the second embodiment described above encodes and further records the data in FIG.
A reproduced signal (c) is obtained from the modulated data (b). This reproduced signal is binarized by taking its rising and falling edges and converted into binary data (d). next,
A clock component is extracted from the binary data, and a punched clock (e) is output by the PLL. The synchronization code detector 14 outputs 1 of the detection result (g) when the detection code part in the synchronization code is detected. The bit synchronization detector 15 detects three consecutive 0s or 1s in the bit synchronization portion of the synchronization code and outputs the detection result (h). On the other hand, when the detection code portion is detected during the period in which the control gate signal (f) indicating the vicinity of the synchronization code detected in the 50-byte cycle is at the H level, the gate 17 outputs the synchronization code. The demodulator 16 is initialized using the detection result of the bit synchronization section immediately after the detection. The demodulator 16 is controlled by the gate 17 every time a synchronization code is detected, and performs NRZI demodulation and (1, 7) demodulation while performing bit resynchronization.

In a phase change recording medium in which information is recorded / reproduced by using a change in reflectance among optical disk devices, when performing PWM recording, there is a so-called unerased residue when overwriting is performed. In addition, there is a high probability that a detection error occurs in long code data. Such unerased portions hardly occur for marks that are recording pits,
It is known that it occurs largely only in the space. FIG. 6 shows an example in which the output of the digital data encoding apparatus according to the first embodiment described above is directly used as N
When recording on an optical disk after RZI modulation, it is not determined whether the detection code portion is continuous 1 or continuous 0.
In particular, in the case where a space is continuously formed by 0s as in the case of the reproduction signal (a), erroneous detection is likely to occur, making it impossible to detect a synchronization code. However, as described in the second embodiment, it is possible to fix the detection code portion so as to be a recording mark, and in this case, detection failure due to remaining erase hardly occurs.

As described above, the synchronization code including the detection code section and the bit synchronization section is arranged in the modulated code data, the presence of the synchronization code is detected by the detection of the detection code section, and the detection of the bit synchronization section is further performed. An object of the present invention is to provide an excellent digital data encoding / decoding device capable of demodulation synchronization without erroneously detecting other code data as a synchronization code by synchronizing demodulation bits.
In particular, for the rules (1 and 7) in Table 1, the values of the digital data corresponding to the synchronization code are all modulated to 0 in advance,
Since the code data corresponding to the adjustment bits before replacement with the synchronization code can be made the same code data as that of the bit synchronization unit, the replacement can be performed by simple switching and the hardware is simplified. doing. Further, the demodulation of the code data portion following the synchronization code can be continuously performed without any trouble. This facilitates the initialization of the demodulator by detecting the bit synchronization portion. Also, an adjustment code section is provided in front of the detection code section so that the connection between the code data and the synchronization code can be smoothly performed.
The clock recovery of L is performed without any inconvenience. Further, by limiting the code detection unit to the recording mark, erroneous detection of the synchronization code due to unerased data can be reduced.

In the above-described embodiment, the modulation rule has been described for the example of (1, 7) modulation, but the present invention is not limited to this.

In the above-described embodiment, the number of 0s between 1s in the detection code portion is set to k + 3. However, the number is not limited to this and may be any number larger than k.

In the digital data encoding apparatus according to the second embodiment, the NRZI modulator 11
And the output of the synchronization code generation means are switched. Alternatively, the output of the first modulation means and the output of the synchronization code generation means are switched, and then the modulation is performed by the second modulation means. It may be.

Further, the disk according to the present invention is characterized in that digital data is modulated by a (d, k) rule in which the number of 0s between 1 is changed from d to k (d, k) and a synchronization code provided separately therefrom. Wherein the synchronization code has an adjustment code part, a detection code part, and a bit synchronization part, wherein the adjustment code part is a code data on the front side and a detection code part on the following side. Are arranged so as to satisfy the (d, k) rule, and the detection code section has data in which the number of 0s between 1 is greater than k, and An optical disc characterized by satisfying the rule (d, k) adjacent thereto, and wherein the data string is recorded directly or in a format further modulated by modulation such as NRZI modulation. It is.

The disc according to the present invention is also an optical disc characterized in that the number of 0s between 1s in the detection code section is k + 3.

In the above embodiment, each means or each element such as a modulator is constituted by dedicated hardware. Alternatively, similar functions may be realized by software using a computer. Of course.

[0064]

As is apparent from the above description, the present invention enables resynchronization in demodulation of digital data,
It has the advantage that a synchronous code having a small correlation with other data can be realized in encoding digital data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital data encoding device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a digital data decoding device according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a digital data encoding device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a digital data decoding device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a first signal waveform for explaining the operation of FIG. 4;

FIG. 6 is a diagram showing a second signal waveform for explaining the operation of FIG. 4;

FIG. 7 is a configuration diagram of a conventional digital data decoding device.

FIG. 8 is a diagram showing signal waveforms for explaining the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 comparator 2 PLL 4 preamble detector 5, 16 demodulator 6, 7, 10, 17 gate 9 (1, 7) modulator 11 NRZI modulator 12 synchronization code generator 13 switch 14 synchronization code detector 15 bit synchronization detection Device 21 modulation means 22 synchronization code generation means 23 switching means 31 synchronization code detection means 32 bit synchronization means 33 demodulation means

Claims (20)

[Claims] 1. An encoding method for converting digital data into code data according to a predetermined rule and adding a synchronization code for synchronization at the time of demodulation of the code data, wherein the synchronization code includes a detection code unit A bit synchronization unit that follows the predetermined rule for synchronization during demodulation, wherein the detection code unit is a code that is arranged immediately before the bit synchronization unit and does not satisfy the predetermined rule. Encoding method to be used. 2. The encoding method according to claim 1, wherein the detection code section is a code constructed by breaking the predetermined rule so that the presence of the data can be detected based on an array value of the data. 3. The encoding method according to claim 1, wherein the synchronization code is a code composed of a bit sequence according to the same clock as the code data. 4. The encoding method according to claim 1, wherein the synchronization code is constituted by a bit string corresponding to two bytes of the digital data string. 5. The predetermined rule is a (d, k) rule for converting digital data into code data in which the number of 0s between 1 is d to k, and 1 in the code data of the detection code section. The encoding method according to any one of claims 1 to 4, wherein a set of bit strings in which the number of 0s is greater than k is one set. 6. An adjustment code section immediately before the detection code section, wherein the adjustment code section satisfies the (d, k) rule at a portion where code data obtained by modulating digital data is switched to a synchronization code. The encoding method according to any one of claims 1 to 5, wherein adjustment is performed in accordance with the content of the code data string in the switching unit. 7. An encoding device for converting digital data into code data according to a predetermined rule and adding a synchronization code according to the predetermined rule for synchronization at the time of demodulation of the code data, wherein the synchronization code Comprises a detection code part and a bit synchronization part for synchronization at the time of demodulation, wherein the detection code is a code that is arranged immediately before the bit synchronization part and does not satisfy the predetermined rule. 8. The encoding apparatus according to claim 7, wherein the detection code section is a code constructed by breaking the predetermined rule so that the presence of the data can be detected by an array value of the data. 9. The encoding apparatus according to claim 7, wherein the synchronization code is a code composed of a bit sequence according to the same clock as the code data. 10. The synchronization code is a digital data sequence 2
8. The encoding apparatus according to claim 7, wherein the encoding apparatus is configured by a bit string corresponding to a byte. 11. The predetermined rule is a rule in which the number of 0s between 1s in digital data is changed from d to k (d, k), and the number of 0s between 1s in the code data of the detection code portion is set. 9. The encoding apparatus according to claim 8, wherein the number of bit strings whose number is larger than k is one set. 12. The method according to claim 11, wherein the number of 0s between 1s is d.
A first modulating means for converting and outputting code data modulated according to the (d, k) rule from k pieces to k pieces, and a number in which the number of 0s between the adjustment code part and 1 is larger than k And a synchronization code generating means for outputting a synchronization code having a bit synchronization section satisfying the (d, k) rule, and switching between the output of the first modulation means and the output of the synchronization code generation means. Switching means for outputting coded data; and second modulation means for performing NRZI modulation on the output of the switching means. The adjustment code part of the synchronization code is such that the code of the detection code part is determined by the second modulation means. An encoding device comprising an adjustment bit set to be always fixed to 0 or 1 after modulation. 13. The method according to claim 13, wherein the number of 0s between 1 is d.
A first modulating means for converting and outputting code data modulated according to the (d, k) rule from k to k, a second modulating means for NRZI-modulating the output of the first modulating means;
An adjustment code section, a detection code section fixed to 0 or 1 and having a length greater than k + 1, and a synchronization code generation section for generating a synchronization code having a bit synchronization section satisfying the (d, k) rule; (2) switching means for switching between the modulation means and the synchronization code generation means to output encoded data, wherein the adjustment code section switches between the code data output from the second modulation means and the synchronization code, An encoding apparatus, wherein code data reaching a detection code section is adjusted according to an output of the second modulation means so as to satisfy the (d, k) rule. 14. The encoding apparatus according to claim 12, wherein a bit string having a length of k + 4 fixed to 0 or 1 of the detection code section is one set. 15. A decoding device for decoding data encoded by the encoding method according to any one of claims 1 to 6, further comprising: detecting a detection code portion not satisfying a predetermined rule in the encoded data. Detecting means for detecting, when the detecting means detects a detection code part, a bit synchronization part detecting means for detecting a bit synchronization part following the predetermined rule following the detection code part, and a bit of the bit synchronization part detection means A decoding unit that is initialized in response to the detection of the synchronization unit. 16. A decoding method for decoding data encoded by the encoding method according to any one of claims 1 to 6, wherein a detection code part which does not satisfy a predetermined rule in the encoded data is deleted. A decoding method comprising: detecting, when detecting the detection code part, detecting a bit synchronization part following the detection code part, and initializing decoding according to the detection of the bit synchronization part. 17. An information recording medium in which a synchronization code for synchronization at the time of demodulation of the code data is recorded by NRZI modulation together with code data obtained by converting digital data according to a predetermined rule, wherein the synchronization code is A detection code section, and a bit synchronization section that follows the predetermined rule for synchronization at the time of demodulation. The detection code section is a code that is disposed immediately before the bit synchronization section and does not satisfy the predetermined rule. An information recording medium. 18. The method according to claim 17, wherein the predetermined rule is a (d, k) rule for converting digital data into code data in which the number of 0s between 1 is d to k.
Information recording medium as described. 19. The information recording medium according to claim 18, wherein the number of 0s between 1s in the code data of the detection code section is a set of k + 3 bit strings. 20. An adjustment code section immediately before the detection code section, wherein the adjustment code section satisfies a modulation rule at a portion where code data obtained by modulating digital data switches to a synchronous code. 20. The information recording medium according to claim 17, wherein the information recording medium is adjusted in accordance with the content of the code data string.