JPH11126879A - Semiconductor device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its production method by which an increase in production cost accompanied by an increase in the number of steps can be suppressed as mush as possible and abnormal etching of inter- layer insulating layer during special surface treatment of accumulation electrode as a typical defective etching of a BPSG film constituting the inter-layer insulation film during HSG pretreatment by a dilute hydrofluoric acid be prevented. SOLUTION: A sidewall 110 made of an insulator is formed continuously on the sidewall of a contact hole 105 which electrically connects the source drain area 101 of a cell Tr with an accumulation electrode 106, extending to the surface of an insulating film under the accumulation electrode 106 at the same time, when an inter-layer insulation film is formed, so that the sidewall 106 can be formed without increase in the number of production steps. The sidewall 110 functions as an etching stopper for preventing of abnormally etching an inter-layer insulating film 104 during special surface treatment of the accumulation electrode 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device forming a dynamic random access memory (DRAM) having a stacked capacitor structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art As the density of LSIs has increased, the area occupied by memory capacitors has been decreasing. For this reason, various measures have been taken to ensure the required capacitance.

In recent years, in a DRAM (Dynamic RAM) having a stacked capacitor structure, as one method of increasing the memory cell capacity per unit area by making the surface of a storage electrode uneven, a silicon film has recently been used. HSG (Hemisph)
A technique for making the area “electric grained” has been developed.

[0004] In the technology of converting the silicon film into an HSG, as disclosed in Japanese Patent Application Laid-Open No. Hei 7-221034, a step of removing a natural oxide film on the surface of the silicon film by some method immediately before the formation of the HSG. It is important to prevent the natural oxide film from being formed again after the removal. These two steps are referred to as pretreatment steps in HSG conversion.

[0005] In this pretreatment step, a surface treatment with dilute hydrofluoric acid is generally performed immediately before HSG so as to remove the natural oxide film on the silicon film surface and terminate the silicon surface with hydrogen atoms. I have.

As described above, technologies for increasing the cell capacity have been researched and developed in various fields, and the technology for specially treating the surface of the storage electrode is not limited to the HSG technology.
It is expected that it will be researched and developed in various forms in the future.

Next, an outline of a method for manufacturing a memory cell using the conventional HSG technology will be described with reference to the drawings. FIG.
FIG. 1 shows a schematic diagram of each step in a method of manufacturing a memory cell using an HSG technique, which is a first conventional technique.

First, FIG. 3A is a sectional structural view of a memory cell immediately before forming a contact for electrically connecting the storage electrode 306 and the source / drain region 301 of the cell Tr.

Here, 301 is a source / drain region,
302 is a silicon substrate, 303 is an element isolation region, 304
Is an interlayer insulating film. Word lines and digit lines are not shown for simplicity.

The interlayer insulating film 304 is made of Boron Phosphorus Sil for the purpose of improving flatness.
Generally, a multilayer film structure of an icate glass (hereinafter, referred to as BPSG) film and a silicon oxide film (SiO ₂ ) is adopted. Further, when the HSG technique is used, since the surface treatment is performed with the above-described diluted hydrofluoric acid, the uppermost layer film is formed of the silicon oxide film 304a as an etching stopper for the diluted hydrofluoric acid.

Next, as shown in FIG. 3B, a contact hole 305 for a storage electrode is opened, and after this, a pretreatment such as buffered hydrofluoric acid is performed, and then a phosphor layer having a desired thickness is formed. A storage silicon electrode 306 before HSG is formed by forming a doped silicon film and patterning the phosphorus-doped silicon film into a desired pattern.

Next, the natural oxide film on the surface of the storage electrode 306 made of a phosphorus-doped silicon film is removed so that the silicon surface is terminated with hydrogen atoms (this is for the purpose of suitably forming HSG. JP-A-7-221034
This is described in further detail in the official gazette. 3), after performing a surface treatment with dilute hydrofluoric acid, HSG (silane irradiation and annealing) is performed to make the surface of the storage electrode 306 uneven, as shown in FIG.

Next, a capacitance insulating film 307 and a plate electrode 308 made of a phosphorus-doped silicon film are formed and patterned into a desired pattern to obtain a semiconductor device shown in FIG. A memory cell having a structure is obtained.

As described above, according to the conventional HSG processing, the surface of the storage electrode can be provided with irregularities, so that the capacity per unit surface area can be improved.

However, according to the conventional HSG process, when the storage electrode contact hole 305 and the storage electrode 306 are misaligned (misalignment) during the patterning of the storage electrode 306. As shown in FIG. 3 (d) (a cross-sectional structural view after pretreatment with dilute hydrofluoric acid), the pretreatment with dilute hydrofluoric acid for HSG conversion
There is a problem that the PSG film is largely etched from a portion exposed by the patterning of the storage electrode, which significantly lowers the yield.

This is a problem that occurs because the etch rate of the dilute hydrofluoric acid BPSG film is about 10 times the etch rate of the silicon oxide film.

Next, a second prior art will be described with reference to FIG. However, the same members as those shown in FIG. 3 are denoted by the same reference numerals. According to the second prior art, a storage electrode contact hole 405 is opened from the semiconductor device in the state of FIG. 3A shown in FIG. 3 of the first prior art, and thereafter, the storage electrode contact hole 405 is formed. A silicon oxide film 409 is formed to such an extent that the hole 405 is not buried to obtain a semiconductor device in a state shown in FIG.

Next, as shown in FIG.
By etching back the silicon oxide film 409 by anisotropic etching, a storage electrode contact shape having the silicon oxide film sidewall 410 is obtained.

Next, as shown in FIG. 4C, after a pretreatment such as buffered hydrofluoric acid is performed, a phosphorus-doped silicon film having a desired thickness is formed. By patterning the film into a desired pattern, the storage electrode 406 before HSG conversion is formed.

Thereafter, similarly to the first conventional technique shown in FIG. 3, after performing a surface treatment with dilute hydrofluoric acid, HSG (silane irradiation and annealing) is performed, and a capacitance insulating film 407 and a phosphorus-doped silicon film are formed. Is formed and patterned into a desired pattern to obtain a semiconductor device in the state shown in FIG. 4D, thereby forming a stacked capacitor.

According to the second conventional technique shown in FIG. 4, even when the HSG technique is not used, a short circuit between a word line or a digit line of a memory cell and a storage electrode is prevented, and a lithography technique is used. There is an effect that a contact for a storage electrode smaller than the limit can be formed.

Further, as apparent from the cross-sectional structural view after the pretreatment with dilute hydrofluoric acid shown in FIG. 4E, when the HSG technique is used, the contact hole for the storage electrode is incidentally added. If the 405 and the storage electrode 406 made of a phosphorus-doped silicon film are misaligned, the BPSG film is not exposed, so that the BPSG film becomes abnormally different from the first prior art shown in FIG. It also has the effect of preventing etching.

In the case of the second prior art, since it is important for the silicon oxide film forming the sidewall 410 to insulate the word line or digit line from the storage electrode, coverage (coverage) in the storage contact hole is required. The film is formed under the favorable conditions of (1).

[0024]

However, in the second prior art, since the sidewalls are formed, the number of steps naturally increases, and the manufacturing cost increases accordingly. .

The present invention has been made in view of the above circumstances, and minimizes an increase in manufacturing cost due to an increase in the number of steps.
In addition, a semiconductor capable of preventing abnormal etching of an interlayer insulating film in a special surface treatment of a storage electrode, which is typified by abnormal etching of a BPSG film constituting an interlayer insulating film during HSG pretreatment with dilute hydrofluoric acid. It is an object to provide an apparatus and a method for manufacturing the same.

[0026]

According to the first aspect of the present invention,
A MOS transistor formed on a semiconductor substrate;
A storage electrode electrically connected to the source / drain region of the OS transistor; a contact hole for electrically connecting the source / drain region of the MOS transistor to the storage electrode; and a contact hole formed at a position facing the storage electrode. A stacked capacitor structure having a plate electrode to be formed, and a capacitive insulating film sandwiched between the plate electrode and the storage electrode, wherein a sidewall made of an insulator is provided on a side wall of the contact hole. The sidewall extends continuously to the surface of the insulating film below the storage electrode.

Therefore, according to the present invention, the insulator is provided on the side wall of the contact hole for forming the storage electrode for electrically connecting to the source / drain region of the MOS transistor formed on the semiconductor substrate. Since the sidewall is formed continuously extending to the surface of the insulating film below the storage electrode simultaneously with the formation of the interlayer film, an increase in manufacturing cost due to the insertion of the step of forming the sidewall can be suppressed. At the same time, it is possible to prevent a short circuit between the word line or digit line of the memory cell and the storage electrode, and to form a storage electrode contact smaller than the limit of the lithography technique.

According to a second aspect of the present invention, in the first aspect of the present invention, the thickness of the sidewall is reduced from the upper portion to the lower portion of the side wall of the contact hole.

Therefore, according to the present invention, the effect of the first aspect of the present invention can be obtained, and the thickness of the sidewall becomes thinner from the upper part to the lower part of the side wall of the contact hole. When Si is exposed, the insulating film forming the sidewall on the upper surface remains, and can be used as a stopper film in the HSG pretreatment, and the contact bottom can be easily exposed. In addition, although the thickness of the insulating film only at the bottom of the contact is reduced and the same thickness is obtained on the upper surface and the side wall of the contact, the same effect as above can be obtained.
Since it is impossible to represent such a film, the film can be easily formed by forming the film to be thinner from the upper part to the lower part of the side wall of the contact hole.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the side wall is formed of a normal pressure CV.
D silicon oxide film growth or plasma excitation CVD
It is characterized by being formed by growing a silicon oxide film.

Therefore, according to the present invention, the operation of the invention described in claim 1 or 2 is obtained, and the sidewall is grown by normal-pressure CVD silicon oxide film growth or plasma-excited CVD silicon oxide film growth. The sidewalls can be formed more reliably and easily.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the surface of the storage electrode has an HSG for increasing a capacitance per unit area.
It is characterized by having been made.

Therefore, according to the present invention, the effect of the invention according to any one of claims 1 to 3 can be obtained, and the surface of the storage electrode can be made HSG-based in order to increase the capacitance per unit area. Because of this, the memory cell capacity per unit area can be increased,
Since the interlayer insulating film is covered with the sidewall, abnormal etching of the interlayer insulating film in the HSG process can be prevented.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the storage electrode is formed of a phosphorus-doped silicon film after pretreatment with buffered hydrofluoric acid. It is characterized by having.

Therefore, according to the present invention, the operation of the invention according to any one of claims 1 to 4 is obtained, and the storage electrode is formed of phosphorus-doped silicon after pretreatment with buffered hydrofluoric acid. Since it is formed of a film, a more appropriate storage electrode can be formed.

According to a sixth aspect of the present invention, there is provided a MOS transistor forming step of forming a MOS transistor on a surface of a semiconductor substrate, a first insulating film forming step of forming a first insulating film on a surface of the semiconductor device, A contact hole opening step of opening a contact hole for exposing the source / drain region of the MOS transistor, and after opening the contact hole, a second insulating film is formed on the entire surface including the opening side wall of the contact hole. Forming a second insulating film, exposing a portion of the second insulating film to expose a source / drain region of the MOS transistor at a bottom of the contact hole, and forming a first electrode serving as a storage electrode A first semiconductor material forming step of forming a first semiconductor material, and a first semiconductor material forming step of patterning the first semiconductor material into a desired pattern. A turning step, a capacitive insulating film forming step of forming a capacitive insulating film under the first semiconductor material, and a second semiconductor forming a second semiconductor material to be a plate electrode on the capacitive insulating film The method includes a material forming step and a second patterning step of patterning the second semiconductor material into a desired pattern.

Therefore, according to the present invention, a contact hole is opened in the source / drain region of the MOS transistor,
After the opening of the contact hole, the second insulating film serving as a sidewall for covering the interlayer insulating film is formed on the entire surface including the opening side wall of the contact hole simultaneously with the formation of the interlayer film. Without increasing, it is possible to prevent a short circuit between the word line or digit line of the memory cell and the storage electrode, and to form a storage electrode smaller than the limit of the lithography technique.

According to a seventh aspect of the present invention, in the invention of the sixth aspect, the first insulating film formed in the first insulating film forming step is formed by stacking SiO ₂ and BPSG in this order. It is characterized by being formed of at least one or more layers.

Therefore, according to the present invention, the effect of the invention described in claim 6 is obtained, and the first insulating film formed in the first insulating film forming step is made of SiO ₂ and BPS.
Since G is formed by at least one or more layers stacked in this order, it is possible to perform more appropriate insulation and to cover the surface of the BPSG with the second insulating film. Can be reduced.

According to an eighth aspect of the present invention, in the invention of the sixth or seventh aspect, the surface of the first semiconductor material patterned by the first patterning step is
In order to increase the capacity per unit area, an HSG-forming step for making an HSG is provided.

Therefore, according to the present invention, the effect of the invention according to claim 6 or 7 is obtained, and the HSG processing is performed on the surface of the storage electrode, so that the memory cell capacity per unit area is obtained. Can be increased, and since the sidewall formed by the second insulating film covers the interlayer insulating film, abnormal etching of the interlayer insulating film in the HSG processing step can be prevented.

According to a ninth aspect of the present invention, in the first aspect of the present invention, the first semiconductor material is formed of a phosphorus-doped silicon film, and the first semiconductor material forming step includes: A pre-treatment step of pre-treating the phosphorus-doped silicon film with buffered hydrofluoric acid, and forming a first semiconductor material to be the storage electrode using the phosphorus-doped silicon film having undergone the pre-treatment step It is characterized by.

Therefore, according to the present invention, the operation of the invention according to any one of claims 6 to 8 can be obtained, and the first semiconductor material is formed of a phosphorus-doped silicon film. The step includes a pre-treatment step of pre-treating the phosphorus-doped silicon film with buffered hydrofluoric acid, and forming a first semiconductor material to be a storage electrode using the phosphorus-doped silicon film having undergone the pre-treatment step. Thereby, a more appropriate storage electrode can be formed.

The invention according to claim 10 is the invention according to claims 6 to 9
In the invention described in any one of the above, the second insulating film formed in the second insulating film forming step has poor coverage in the contact hole, and has a thickness greater than that of an upper portion of a side wall of the contact hole. Are also formed so as to be thin at the lower part.

Therefore, according to the present invention, the effect of the invention according to any one of claims 6 to 9 can be obtained, and the second insulating film formed in the second insulating film forming step has a contact hole. In the case where the insulating film is etched back to form the sidewall, the covering property is poor because the covering property is poor and the thickness is formed to be thinner in the lower part than the upper part of the side wall of the contact hole. If a good film is used, this insulating film will not remain on the upper surface when the Si substrate at the bottom of the contact is exposed, but if the film has poor coverage, it will remain on the upper surface, and this remaining film will be used later. It can be used as a stopper film in the HSG pretreatment in the process.

In order to obtain the above-mentioned effect, the thickness may be reduced by the thickness of the contact bottom, and the upper surface and the contact side wall may have the same thickness. However, it is impossible to realize such a film. However, when the etch back is performed by the isotropic etch back, the exposed area of Si at the bottom of the contact becomes large, so that the contact resistance can be reduced.

The eleventh aspect of the present invention relates to the sixth to the first aspects.
0, the second insulating film forming step is performed by an insulating film forming step by growing a normal pressure CVD silicon oxide film or an insulating film growing step by growing a plasma-excited CVD silicon oxide film. It is characterized by the following.

Therefore, according to the present invention, the effect of the invention according to any one of claims 6 to 10 can be obtained,
The second insulating film forming step is an insulating film forming step by growing a normal pressure CVD silicon oxide film or a plasma excitation CV.
The second insulating film can be formed more accurately and easily because the second insulating film is formed by the insulating film growing step of growing the D silicon oxide film.

[0049]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 shows each step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view of the semiconductor device manufactured in each step.

FIG. 1A shows a semiconductor device according to the first embodiment of the present invention immediately before forming a contact for electrically connecting the storage electrode and the source / drain region of the cell Tr. FIG. 3 is a sectional structural view of a memory cell.

Here, 101 is a source / drain region,
102 is a silicon substrate, 103 is an element isolation region, 104
Is an interlayer insulating film. Word lines and digit lines are not shown for simplicity.

The interlayer insulating film 104 has a multilayer structure of a BPSG film and a silicon oxide film (SiO ₂ ) for the purpose of improving the flatness.
The PSG film 104a is that the silicon oxide film is not formed on the uppermost layer before the contact for the storage electrode is opened.

Next, as shown in FIG. 1B, a storage electrode contact hole 105 is opened.

Next, as shown in FIG. 1C, a silicon oxide film 109 is formed to such an extent that the storage electrode contact hole 105 is not buried.

Here, the coverage (coverability) is such that the thickness of the silicon oxide film 109 at the bottom of the contact hole and the lower portion of the contact hole side wall is smaller than the thickness of the silicon oxide film on the upper surface and the upper portion of the contact hole side wall.
Is formed under poor conditions. For example, such a shape can be formed by using techniques such as normal pressure CVD silicon oxide film growth and plasma-excited CVD silicon oxide film growth.

As described above, the insulating film is etched back to form a side wall by forming the film under conditions of poor coverage so as to be thinner than the silicon oxide film on the upper surface and on the side wall of the contact hole. In this case, when the Si at the bottom of the contact is exposed, the insulating film does not remain on the upper surface. However, if the film has poor coverage, the insulating film remains on the upper surface. This remaining insulating film can be used as a stopper film in the HSG pretreatment in a later step.

The shape of the sidewall is formed so as to become thinner from the upper part to the lower part. The effect of such a shape is that only the contact bottom part is made thinner, and the upper part and the side wall part are made the same. Although it is possible to obtain such a film even when the film thickness is set as described above, it is almost impossible to realize such a film. Accordingly, since the thickness is reduced from the upper part to the lower part, such a sidewall can be easily formed.

Next, as shown in FIG. 1D, the source / drain region 101 at the bottom of the contact hole 105 is exposed by etching back the silicon oxide film 109 by anisotropic etching. A storage electrode contact shape having a silicon oxide film sidewall 110 is obtained.

Next, as shown in FIG. 1E, after a pretreatment such as buffered hydrofluoric acid is performed, a phosphorus-doped silicon film having a desired thickness is formed, and further a phosphorus-doped silicon film is formed. Is patterned into a desired pattern, thereby forming the storage electrode 106 before HSG conversion.

Thereafter, as shown in FIG.
After performing surface treatment with dilute hydrofluoric acid, HSG (silane irradiation and annealing) is performed to form a capacitor insulating film 107 and a plate electrode 108 made of a phosphorus-doped silicon film, and patterning into a desired pattern is performed. To obtain a memory cell having a capacitor structure.

In the first embodiment, a case where the storage electrode contact hole 105 and the storage electrode 106 are misaligned will be described with reference to FIG. As shown in FIG. 1G, the upper surface and the side wall of the contact hole for the storage electrode have a silicon oxide film having a thickness enough to function as an etching stopper in the HSG pretreatment with dilute hydrofluoric acid. , The BPSG film is not exposed, thereby preventing the BPSG film from being abnormally etched.

The silicon oxide film 10 functioning as an etching stopper at the time of HSG pretreatment with dilute hydrofluoric acid.
9 is formed in one film forming step after opening the contact for the storage electrode, the number of steps is reduced as compared with the second related art described in the above related art, and the manufacturing cost is increased. Can be suppressed.

Next, a second embodiment of the semiconductor device and the method of manufacturing the same according to the present invention will be described with reference to FIG.

The semiconductor device shown in FIG. 2A is a semiconductor device in exactly the same state as the semiconductor device shown in FIG. 1C after going through the same steps as in the first embodiment. is there.

Thereafter, the second prior art and the first
In the second embodiment, the silicon oxide film 209 is etched back by anisotropic etching, but in the second embodiment, a process in which the pretreatment such as buffered hydrofluoric acid is strengthened is used instead.

Here, according to the buffered hydrofluoric acid, since there is almost no difference in the etch rate between the silicon oxide film and the BPSG film, abnormal etching of the BPSG film is not induced. Therefore, as shown in FIG. 2B, a silicon oxide film is left on the upper surface of the storage electrode contact and the upper portion of the storage electrode contact sidewall, and the lower portion of the storage electrode contact bottom and the lower portion of the storage electrode contact sidewall are left. By etching the silicon oxide film, a contact hole for a storage electrode can be formed.

Thereafter, through the same steps as in the first embodiment, as shown in FIG. 2C, a memory cell having a stacked capacitor structure is obtained.

In the second embodiment, since the silicon oxide film is left on the upper surface of the storage electrode contact and the upper portion of the storage electrode contact side wall, the BPSG is formed in the same manner as in the first embodiment. It is not exposed on the upper part of the storage electrode contact side wall, and as shown in FIG. 2D, abnormal etching of the BPSG film can be prevented. Further, since the etch back of the silicon oxide film 209 by the anisotropic etching is performed by applying a stronger pretreatment such as buffered hydrofluoric acid, the number of steps is further reduced as compared with the first embodiment, Manufacturing costs can be reduced.

[0070]

As is apparent from the above description, according to the semiconductor device of the present invention, the MOS transistor formed on the semiconductor substrate and the storage electrode electrically connected to the source / drain region of the MOS transistor A contact hole for electrically connecting the source / drain region of the MOS transistor and the storage electrode; a plate electrode formed at a position facing the storage electrode; and a plate electrode sandwiched between the plate electrode and the storage electrode. In a semiconductor device having a stacked capacitor structure having a capacitive insulating film, a sidewall made of an insulator is provided on a side wall of a contact hole, and the sidewall continuously extends to a surface of the insulating film below the storage electrode. Therefore, even if misalignment occurs between the storage electrode contact hole and the storage electrode, continuous Since Doworu functions as an etching stopper for the surface treatment of the storage electrode can be an interlayer insulating film in a portion where the main is to provide a semiconductor device capable of preventing in advance from being abnormally etched.

Further, since the thickness of the sidewall becomes thinner from the upper portion to the lower portion of the side wall of the contact hole, when the Si at the bottom of the contact is exposed, the insulating film forming the sidewall on the upper surface remains. However, it can be used as a stopper film in the HSG pretreatment, and the contact bottom can be easily exposed. Only the thickness of the insulating film at the contact bottom is reduced, and the same thickness is formed on the upper surface and the contact side wall. Although the same effect as described above can be obtained, such a film cannot be expressed. Therefore, by forming the contact hole to be thinner from the upper part to the lower part of the side wall, the formation is reduced. A semiconductor device which can be easily manufactured can be provided.

Further, since the sidewalls are formed by growing a normal pressure CVD silicon oxide film or a plasma excitation CVD silicon oxide film,
Further, it is possible to provide a semiconductor device in which a sidewall can be formed more reliably and easily.

Since the surface of the storage electrode is made HSG in order to increase the memory cell capacity per unit surface area, the memory cell capacity per unit area can be increased and the interlayer insulating film can be formed. Since the side walls are covered with the semiconductor device, it is possible to provide a semiconductor device capable of preventing abnormal etching of the interlayer insulating film in the HSG processing step.

Furthermore, since the storage electrode is formed of a phosphorus-doped silicon film after pretreatment with buffered hydrofluoric acid, a semiconductor device capable of forming a more appropriate storage electrode is provided. can do.

Further, according to the method of manufacturing a semiconductor device of the present invention, a MOS transistor forming step of forming a MOS transistor on a surface of a semiconductor substrate, and a first insulating film forming a first insulating film on a surface of the semiconductor device are provided. Film formation process and MO
An opening step of opening a contact hole in the source / drain region of the S transistor; a second insulating film forming step of forming a second insulating film on the entire surface after opening the contact hole;
An exposing step of exposing a part of the second insulating film to expose a source / drain region of the MOS transistor at a bottom of the contact hole; and a first semiconductor material forming step of forming a first semiconductor material to be a storage electrode. A first patterning step of patterning a first semiconductor material into a desired pattern, a capacitance insulating film forming step of forming a capacitance insulating film, and a second semiconductor forming a second semiconductor material to be a plate electrode Since the method includes a material forming step and a second patterning step of patterning a second semiconductor material into a desired pattern, a sidewall as an etching stopper for a surface treatment of a storage electrode is conventionally provided. Compared with a method in which the contact holes are separately formed on the side wall of the contact hole and the surface of the interlayer insulating film, the number of steps is reduced, and the The method of manufacturing a semiconductor device capable of suppressing can be provided.

Since the first insulating film formed in the first insulating film forming step is formed by at least one layer in which SiO ₂ and BPSG are laminated in this order, it is more appropriate. And the second insulating film covers the surface of the BPSG simultaneously with the formation of the side wall.
A method for manufacturing a semiconductor device capable of reducing cost can be provided.

Further, since the surface of the storage electrode is subjected to the HSG process, the memory cell capacity per unit surface area can be increased, and the side wall formed by the second insulating film can be used as an interlayer insulating film. Since the film is covered, it is possible to provide a method for manufacturing a semiconductor device capable of preventing abnormal etching of an interlayer insulating film in an HSG processing step.

Also, the first semiconductor material is formed of a phosphorus-doped silicon film, and the first semiconductor material forming step includes a pre-processing step of pre-processing the phosphorus-doped silicon film with buffered hydrofluoric acid. A method for manufacturing a semiconductor device capable of forming a more appropriate storage electrode by forming a first semiconductor material serving as a storage electrode using a phosphorus-doped silicon film having undergone a pretreatment step is provided. it can.

Further, the insulating film formed in the second insulating film forming step has poor coverage in the contact hole,
And, since the thickness is formed so as to be thinner at the lower portion than at the upper portion of the side wall of the contact hole, when a film having good covering property is used in forming the sidewall by etching back the insulating film, Contact bottom Si
When the substrate is exposed, this insulating film does not remain on the upper surface, but if the film has poor coverage, it remains on the upper surface, and the remaining film is used as a stopper film in the HSG pretreatment in a later step. A method for manufacturing a semiconductor device that can be used for a semiconductor device can be provided.

Therefore, in order to obtain the above effect, the thickness may be reduced by the thickness of the contact bottom, and the upper surface and the contact side wall may have the same thickness. However, since it is impossible to represent such a film, the semiconductor device has a shape that becomes thinner from the upper part to the lower part. Therefore, a method for manufacturing a semiconductor device in which a sidewall can be easily formed is provided. can do. If the etch back is performed by isotropic etch back, the Si
Since the exposed area of the semiconductor device increases, it is possible to provide a method of manufacturing a semiconductor device capable of reducing the contact resistance.

Further, the second insulating film forming step is performed under the normal pressure C
The second insulating film can be formed more accurately and easily because the insulating film is formed by a VD silicon oxide film growth process or a plasma excitation CVD silicon oxide film growth process. A method for manufacturing a semiconductor device can be provided.

That is, according to the method of manufacturing a semiconductor device according to the present invention, the increase in the manufacturing cost due to the increase in the number of steps is suppressed as much as possible, and the abnormal etching of the interlayer insulating film in the special surface treatment of the storage electrode is prevented. It has the effect of.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional structural view of a second embodiment of the semiconductor device according to the present invention.

FIG. 3 is a sectional structural view of a semiconductor device according to a first conventional technique.

FIG. 4 is a sectional structural view of a semiconductor device according to a second conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Source / drain region 102 Silicon substrate 103 Element isolation region 104 Interlayer insulating film 105 Contact for storage electrode 106 Storage electrode 107 Capacitive insulating film 108 Plate electrode 109 Silicon oxide film 206 Storage electrode 207 Capacitive insulating film 208 Plate electrode 209 Silicon oxide film

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/41

Claims (11)

[Claims] A MOS transistor formed on a semiconductor substrate; a storage electrode electrically connected to a source / drain region of the MOS transistor; and a source / drain region of the MOS transistor and the storage electrode. A semiconductor device having a stacked capacitor structure, comprising: a contact hole for connection; a plate electrode formed at a position facing the storage electrode; and a capacitance insulating film sandwiched between the plate electrode and the storage electrode. In the above, a side wall made of an insulator is provided on a side wall of the contact hole, and the side wall extends to an insulating film surface below the storage electrode.
A semiconductor device which extends continuously. 2. The semiconductor device according to claim 1, wherein the thickness of the sidewall decreases from an upper portion to a lower portion of the side wall of the contact hole. 3. The semiconductor device according to claim 1, wherein the sidewall is formed by growing a normal pressure CVD silicon oxide film or a plasma excitation CVD silicon oxide film. 4. The semiconductor device according to claim 1, wherein the surface of the storage electrode is formed with HSG in order to increase the capacitance per unit area. 5. The semiconductor device according to claim 1, wherein said storage electrode is formed of a phosphorus-doped silicon film after pretreatment with buffered hydrofluoric acid. . 6. A MOS transistor forming step of forming a MOS transistor on a surface of a semiconductor substrate, a first insulating film forming step of forming a first insulating film on a surface of the semiconductor device, and a source / drain of the MOS transistor A contact hole opening step of opening a contact hole for exposing a region; and forming a second insulating film on the entire surface including the opening side wall of the contact hole after opening the contact hole. And etching a part of the second insulating film,
An exposing step of exposing a source / drain region of the MOS transistor at a bottom of the contact hole; a first semiconductor material forming step of forming a first semiconductor material to be a storage electrode; A first patterning step of patterning into a pattern, a capacitive insulating film forming step of forming a capacitive insulating film under the first semiconductor material, and a second semiconductor material serving as a plate electrode on the capacitive insulating film. Forming a second semiconductor material, and a second patterning step of patterning the second semiconductor material into a desired pattern. 7. The method according to claim 1, wherein the first insulating film formed in the first insulating film forming step is formed of at least one layer in which SiO ₂ and BPSG are stacked in this order. The method of manufacturing a semiconductor device according to claim 6. 8. The method according to claim 1, further comprising an HSG-forming step of converting the surface of the first semiconductor material patterned by the first patterning step into an HSG to increase a capacity per unit area. A method for manufacturing a semiconductor device according to claim 6. 9. The method according to claim 1, wherein the first semiconductor material is formed of a phosphorus-doped silicon film, and the first semiconductor material forming step includes a pre-processing step of pre-processing the phosphorus-doped silicon film with buffered hydrofluoric acid. And using the phosphorus-doped silicon film having passed through the pretreatment step,
9. The method of manufacturing a semiconductor device according to claim 6, wherein a first semiconductor material serving as the storage electrode is formed. 10. The second insulating film formed in the second insulating film forming step, wherein the second insulating film has poor coverage in the contact hole and is thinner in a lower portion than in an upper portion of a side wall of the contact hole. The method for manufacturing a semiconductor device according to claim 6, wherein: 11. The step of forming the second insulating film, the step of forming an insulating film by growing a normal pressure CVD silicon oxide film,
11. The method of manufacturing a semiconductor device according to claim 6, wherein the method is performed by an insulating film growth step by plasma-excited CVD silicon oxide film growth.