JPH11125802A - Scanning electrode driving ic of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify light shielding when the signal transmission by light is executed by decreasing the connection wiring to external circuits and parts. SOLUTION: A scanning electrode driving IC has a photodetecting part 11, a gate signal generating circuit 12 and a pulse discriminating circuit 13. An optical signal 101 multiplexed to one signal by making the signals used for clock, start control, scanning direction control, etc., impulsive passes through a glass substrate and arrives at the photodetecting part 11 formed on a terminal surface. The output signal 102 of the photodetecting part 11 inputs an impulse train to a gate signal generating circuit 12 and a pulse discriminating circuit 13. At the head of this impulse train gate signal 103 turns active for a specified period and the impulses inputted during this period are sequentially allocated to the clock 104, the start pulse 105 and the scanning direction control pulse 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning electrode driving IC for a liquid crystal display, and more particularly to a scanning electrode driving IC for a liquid crystal display which transmits a signal by light.

[0002]

2. Description of the Related Art In a matrix type liquid crystal display device, as the number of pixels increases, the number of electrodes driven by one electrode driving IC also increases. One electrode drive IC in such a situation
In order to enable connection to a large number of liquid crystal panel electrodes, a method has been put to practical use in which a connection portion of a mounting board and a terminal surface of an electrode driving IC are overlapped face to face to make an electrical connection. In this series of mounting technology fields, there is a method of simultaneously forming a connection portion of an electrode driving IC and a screen of a liquid crystal panel on one glass substrate, and this is called chip-on-glass (hereinafter referred to as COG). Some electrode drive ICs for COG use the property that the transparent electrode wiring on the glass substrate can be finely patterned, and arrange output terminals for electrode drive inside the terminal surface to enable high-density connection. I was However, since the COG requires a portion on which an electrode driving IC is mounted, an increase in the size of the glass outer shape has led to an increase in cost and a reduction in design flexibility.

Therefore, in order to reduce the size of the mounting portion of the electrode driving IC, the Company has developed a scanning electrode driving IC for inputting power and control signals from the short side of the scanning electrode driving IC (Japanese Utility Model Application No. Hei 5-23753). , Japanese Patent Application No. 6-52297
7). In this scan electrode driving IC, the number of wires connected to an external circuit has been reduced to only four power supplies, clock and start signal input terminals. Therefore, to control the function,
The setting by the ITO wiring in the liquid crystal display panel and the phase relationship between the two signals have been used. Further, since it is driven by an oscillating power source to be described later, a level shifter for transmitting the above two signals has been newly devised for the purpose of wiring reduction (Japanese Utility Model Laid-Open No. 7-26827).

FIG. 7 is a waveform diagram (A) of the swing power supply system and a circuit diagram (B) of the above-described level shifter. In (A), the power supply VDD on the high voltage side of the oscillating power supply sets the maximum value to the voltage V.
1. The minimum value is switched as the voltage VM. Similarly, the power supply VSS on the low voltage side of the oscillating power supply is switched in synchronization with the power supply VDD, with the highest value being the voltage VM and the lowest value being the voltage V2.
This switching is called rocking. When driving a liquid crystal panel, a power supply for supplying a voltage VM (hereinafter referred to as a power supply VM) is often added to three power supplies. In this method, (VDD-V
SS), the voltage VM is applied to the scan electrodes (TP1, TP2, etc.) at the time of non-selection, while the highest value is the voltage V1 and the lowest value is the voltage V2 at the time of selection. Can be output.

In order to transmit a signal from a display control circuit 71 operating on a normal fixed power supply system (hereinafter, referred to as a fixed power supply system) to a scanning power supply driving IC of an oscillating power supply system, FIG. The level shifter of B) was used.
As shown in (A), the display control circuit 71 outputs an impulse on the start signal S1 when the phase of the oscillating power supply is high, and outputs an impulse on the start signal S2 when the phase of the oscillating power supply is low. Is output. When an impulse is output on the signal S1, the transistor 72 conducts and the output OUT becomes the voltage VM. Similarly, when an impulse is output to the signal S2, the transistor 75 conducts and the output OUT becomes the voltage V2. The display control circuit 7
The circuit is not symmetrical because the ground level of 1 and the voltage VM are almost equal. The clock signal used the same level shifter.

The above-described level shifter shifts the level of a signal from the fixed power supply system to the oscillating power supply system. Two signals S1 and S2 are required for one function like control. Furthermore, the resistance 7
3 and transistors 72 and 75, in which a diode 74 is inserted into a wired-OR circuit, and a capacitor 76 and a resistor 77 for moving the signal S2 to the V2 level are mounted on an external circuit. There are many parts to perform.

Under these circumstances, a method (photocoupler) of shutting off two different power supply systems and transmitting a signal by light is generally well known. In liquid crystal display systems,
There is an example in which this is applied to a scan electrode drive circuit of a high voltage fixed power supply system (Japanese Patent Publication No. 9-634680). In this example, there is no specific description of the arrangement of elements and the connection status, but it is estimated that optical fibers and microlenses are required, and complicated structures such as light shielding to prevent leakage of multiple optical signals are assumed. Is done. Also, there is no description of an application example to a swing power supply.

[0008]

In order to further reduce the size of the mounting portion of the scan electrode driving IC and the FPC connection portion, it is necessary to reduce the number of wirings to external circuits. Also, many parts were used for the level shifter for transmitting the signal to the swing power supply system. For this reason, a method of transmitting a signal by light is considered to be effective. In particular, in the case of COG, a property that a light signal can be transmitted through a transparent glass substrate by providing a light receiving portion in the scan electrode driving IC can be used. However, when trying to apply the above-described example, it is difficult to completely shield the light in consideration of the small light-receiving area allowed for the scan electrode driving IC that is being miniaturized and the spread of light.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a scan electrode driving IC of a liquid crystal display device that can transmit an optical signal with simple light shielding.

If the scan electrode drive IC becomes smaller and extremely elongated, it becomes difficult to confirm the direction of the scan electrode drive IC during mounting. Also, we want to eliminate the need to check the direction to shorten the process. Therefore, the invention according to claim 3 is:
Another object of the present invention is to provide a scanning electrode driving IC for a liquid crystal display device, which does not require checking the direction during mounting.

[0010]

According to a first aspect of the present invention, a scan electrode driving IC includes a light receiving section, a gate signal generation circuit, and a pulse discrimination circuit. The optical signal path passes through the transparent mounting substrate and reaches the light receiving portion formed on the terminal surface, and the output signal of the light receiving portion is input to the gate signal generation circuit and the pulse discrimination circuit, and the gate signal generation circuit Outputs a gate signal to a pulse discrimination circuit.

According to a third aspect of the present invention, in the first aspect of the present invention, a light receiving portion is provided on each of the upper and lower short sides of the scan electrode driving IC, and an optical signal is input to one of the light receiving portions. The scanning direction is determined by the light receiving unit to which the optical signal is input.

(Operation) A signal used for clock, start control, scanning direction control and the like is converted into an impulse and multiplexed into one optical signal. As a result, one light receiving section (or 2
). When an optical signal is input, the gate signal is activated for a certain period of time, and discriminates impulses for clock, start control, and scanning direction control from the order of impulses input during this period.

[0013]

FIG. 1 is a block diagram of a scan electrode driving IC according to a first embodiment. The optical signal 101 is obtained by multiplexing a control signal into an impulse based on a clock by an external display control circuit. When an optical signal 101 is input to the light receiving unit 11, an output signal 102 of the light receiving unit 11 is converted into a gate signal generation circuit 12 and a pulse discrimination circuit 13.
To enter. The gate signal generation circuit 12 is a one-shot multivibrator, and outputs the output signal 102
, A gate signal 103 whose period is determined by an internal time constant circuit is output to the pulse discrimination circuit 13. The pulse discrimination circuit 13 outputs the output signal 102 of the light receiving unit 11 during the gate period given by the gate signal 103.
, And decompose each impulse into a clock 104, a start pulse 105, and a direction control pulse 10 in order.
Assign to 6. The control signal generation circuit 14 outputs the clock 10
4. Start signal 105 for bidirectional shift register 15 from start pulse 105, direction control pulse 106,
A direction control signal 108 is created. When the direction control signal 108 is at a high level, the bidirectional shift register 15 outputs a pulse 10 indicating the selection timing in the order of the output terminals Q1, Q2, and Q240 (hereinafter referred to as a forward mode).
9, output terminals TP1,..., TP2 for driving the scan electrodes.
The signal is output to the drive circuit 16 connected to 40. When the direction control signal is at a low level, a pulse 109 indicating a selection timing is sequentially output in a reverse direction (hereinafter, referred to as a reverse mode).

Referring to FIG. 2, the operation of FIG. 1 will be described more specifically. 2A and 2B are timing charts of the block diagram of FIG. 1 in the first embodiment, wherein FIG. 2A is a forward mode, and FIG. 2B is a reverse mode. When an optical signal is input in (A), a positive impulse appears in the output signal 102 of the light receiving unit 11. The first three impulses in the output signal 102 of the light receiving unit 11 are sequentially shifted by the clock 10.
4. Since the start pulse 105 and the direction control pulse 106 correspond to the start pulse 105 and the direction control pulse 106, and the other impulses correspond to the clock 104, the optical signal 101 can be said to be obtained by multiplexing the start pulse 105 and the direction control pulse 106 based on the clock 104. The gate signal 103 is the gate signal 10
When the signal 3 is at a low level, the output signal 102 of the light receiving unit 11 to be inputted becomes high level at the leading edge of the impulse train of the output signal 102 and maintains the high level for a certain period. When there are a plurality of impulses in this high level period, the respective pulses are sequentially clock 104, start pulse 105,
Assigned to direction control pulse 106. When one impulse is generated during the gate period, this is used as the clock 104. The start signal 107 goes high when the start pulse 105 is input, and returns to the low level at the fall of the next clock. The direction control signal 108 is reset once by the start pulse 105 and is set by the direction control pulse. Even if the polarity of the direction control signal 108 changes during the clock 104, there is no effect on the bidirectional shift register 15 if it returns to the original state. Since the direction control signal 108 is at a high level, the output terminals Q1 and Q2 sequentially go to a high level to provide a selection timing.

In FIG. 2B, gate signals 103,
The clock 104, the start pulse 105, and the start signal 107 are the same as those in FIG. Since the first pulse train of the output signal 102 of the light receiving unit 11 is two, the direction control pulse 104 is not output. For this reason, the direction control signal 107 is kept reset, and the mode becomes the reverse direction mode. From this, the output terminals Q240 and Q239 sequentially become high level in synchronization with the next clock, giving a selection timing.

FIG. 3 shows the scan electrode drive I of the first embodiment.
C light receiving section 11 (A), gate signal generating circuit 12
FIG. 3B is a circuit diagram of the pulse discriminating circuit 13 (C) and the control signal generating circuits 14 (D) and (E). In (A), when the optical signal 101 is not input, the photodiode 30
2 and the resistor 301, no current flows, and the gate terminal of the P-channel transistor 303 is in a cut-off state because the gate terminal is at a high level, and no current flows through the resistor 304. Therefore, the output signal 102 of the light receiving unit 11 is at a low level (voltage VSS). Becomes When the optical signal 101 is input, a current flows through the photodiode 302, the P-channel transistor 303 is turned on, and the output signal 102 of the light receiving unit 11 becomes high level (voltage VDD). In (B), Noahs 305 and 306
When the output signal 102 of the light receiving section 11 is input to the set terminal of the RS flip-flop configured as described above, the gate signal 103 goes high. Then, charging of the capacitor 308 is started via the resistor 307, and when the charging voltage exceeds the threshold value of the NOR 306, the gate signal 103 goes low again. 3C, the data type flip-flop 30 synchronized with the fall of the output signal 102 of the light receiving section 11
9 and 310 constitute a sequential circuit, and 311 and 31
The clock 104, the start pulse 105,
The direction control pulse 106 is discriminated. Note that a circle in the figure indicates negative logic. In (D), Noah 3
When the start pulse 105 is input to the set terminal of the RS flip-flop composed of the RS flip-flops 14 and 315, the start signal 107 goes high, and when the Q output of the data type flip-flop goes high at the next fall of the clock 104, the start signal 107 goes high. Returns to low level again. In (E), when the start pulse 105 is input to the reset terminal of the RS flip-flop constituted by the NORs 317 and 318, the direction control signal 108 once becomes low level, and when the direction control pulse 106 is input to the set terminal, the direction control signal 108 becomes High level. In the reverse mode, since the direction control pulse 106 is not input, the direction control signal 108 becomes low level.

FIG. 4A is a plan view of a terminal surface of the scan electrode driving IC 41 according to the first embodiment, and FIG.
FIG. 41B is a plan view showing the mounting state of the device 41; In (A), power supply terminals VDD, VSS, and VM are arranged on the upper short side. There is a light receiving section 11 below it,
The light-shielding band 42 (oblique line) created in the G bump process is surrounded. The output terminals TP1 to 240 for driving the scanning electrodes are arranged in a line at the center. In (B), the scanning electrode driving IC 41 and the LE are placed on a glass substrate 408 as a lower glass.
D406 is mounted, and a reflection plate 407 (dotted line) is attached to the back surface. The LED wiring 402 and the power supply wiring 405 are connected to the wiring 403 on the upper glass 409 side by a silver dot 404, and this wiring 403 is connected to the FPC4 on the back surface of the upper glass 409.
01 (partially dotted line).

FIG. 5 shows the scanning electrode drive I of the first embodiment.
It is a wave form diagram in C forward mode. The optical signal 101 is input to the scan electrode driving IC at the timing indicated by the arrow.
The power supply VDD fluctuates every three clocks with the highest value being the voltage V1 and the lowest value being the voltage VM. The power supply VSS swings with the highest value being the voltage VM and the lowest value being the voltage V2. At the beginning, the optical signal 101 is input continuously for a short period of time.
When the optical signal 101 is input, a positive selection pulse is output from the output terminal TP1 for driving the scan electrode. Similarly, when the fifth and sixth optical signals 101 are input, positive polarity selection pulses are output from the scan electrode driving output terminals TP2 and TP3. When the seventh, eighth, and ninth optical signals 101 are input, a negative selection pulse is output from the scan electrode driving output terminals TP4, TP5, and TP6 in response to the low phase of the oscillating power supply. You. Similarly, the scan electrode driving output terminal TP7 outputs a positive polarity selection pulse.

FIG. 6 shows a scan electrode drive I according to the second embodiment.
It is the block diagram (A) of C60, and the top view (B) of a terminal surface. In FIG. 1A, the same numbers as those in FIG. 1 correspond to equivalent circuits, signals, and terminals. The light signal 601 is transmitted to the light receiving section 61 on the left side.
, An impulse is generated in the output signal 603 of the light receiving unit 61 through the OR 68, and the gate signal generation circuit 12
Is output to the control signal generation circuit 64. Optical signal 602
Is input to the right light receiving section 67, an impulse is output to the gate signal generating circuit 12 and the control signal generating circuit 64 via the OR 68 in the output signal 604 of the light receiving section 62. Gate signal generation circuit 1 based on output signals 603 and 604 of light receiving sections 61 and 67 output from OR circuit 68.
2 sets the gate signal 103 to the high level, and the pulse discriminating circuit 63 discriminates the clock 104 and the start pulse 105 during the gate period. The control signal generation circuit 64 outputs the start signal 107 to the bidirectional shift register 15, while the impulse is input from the light receiving unit 61, the direction control signal 108 is set to high level, and when the impulse is input from the light receiving unit 67, the direction control signal 108 is output. Set to low level.
Connect the terminal 606 or 607 to the power supply terminal VSS and
When 5 is set to low level, the output of the exclusive OR 69 becomes equal to the direction control signal 108. Therefore, when the optical signal 601 is input from the left in FIG.
When 02 is input, the mode becomes the reverse direction mode. Conversely, terminal 60
When 6 or 607 is connected to the power supply terminal VDD and the wiring 605 is set to the high level, the output of the exclusive OR 69 becomes the direction control signal 1
08, the optical signal 601 from the left.
Is input, a reverse mode is entered, and when an optical signal 602 is input from the right, a forward mode is entered.

In FIG. 6B, power supply terminals VDD and V
M and VSS are arranged on the upper and lower short sides, and the same terminals are rotationally symmetric with respect to the center of the scan electrode driving IC 60 as an axis. Similarly, the light receiving portions 61 and 67, the light shielding bands 608 and 609 (hatched portions), and the terminals 606 and 607 formed in the COG bump process are also rotationally symmetrically arranged. Further, the scanning electrode driving output terminals TP1 to TP240 are also rotationally symmetrically arranged. Thus, the terminal VDD,
Since the VM, VSS, 608, 609, TP1 to 240, and the light receiving units 61, 67 are arranged rotationally symmetrically, the scan electrode driving IC 60 can be mounted in either vertical direction when mounted on a glass substrate. Becomes Further, since the function of (A) is provided, if the position of the light emitting element and the set voltage of the terminal 606 (or 607) are determined, the vertical scanning direction of the screen has no relation to the vertical direction of the scanning electrode driving IC 60. For example, assuming that a light emitting element is arranged at the bottom of the screen when vertical scanning is to be performed from the top of the screen, the terminal 606 (or 607) and the power supply terminal VDD may be connected by ITO wiring on the panel. Although this does not conform to the gist of the present invention in which the number of wirings to the external circuit is reduced, the terminal 606 (607) can be pulled out to the external circuit and the scanning direction can be set by a switch or the like.

[0021]

As described above, in the scan electrode driving IC of the present invention, the control signal is multiplexed as an impulse train on the basis of the clock and integrated into one signal, and this signal is scanned with a pair of light emitting elements. It can be transmitted by the light receiving part of the electrode. In addition, the impulse train was discriminated into a clock and a control signal by a simple method using a time constant. As described above, in the scan electrode driving IC of the present invention, since all functions are controlled by a single optical signal, there is no problem of light leakage and a complicated structure expected in a system using a plurality of optical signals. There is an effect that the scan electrode driving IC can be driven by transmitting an optical signal with a simple light shielding such that external light is prevented by a simple light shielding band that can be created in the bump process.

According to the second aspect of the present invention, in addition to the above-described effects, the terminal and the light receiving portion are rotationally symmetrically arranged, and the scanning direction of the screen is determined by the direction in which the optical signal is inputted with reference to the screen. There is an effect that it is not necessary to check the vertical direction of the scan electrode driving IC when mounting the IC.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart according to the first embodiment of the present invention.

FIG. 3 is a scan electrode driving IC according to a first embodiment of the present invention;
Light receiving section 11 (A), gate signal generating circuit 12 (B),
Pulse discrimination circuit 13 (C), control signal generation circuit 14
The circuit diagram of (D), (E).

FIG. 4 is a scan electrode driving IC according to the first embodiment of the present invention;
41A is a plan view of the terminal surface of the scan electrode driving IC 41. FIG.
FIG.

FIG. 5 is a scan electrode driving IC according to the first embodiment of the present invention;
FIG. 4 is a waveform diagram in a forward mode.

FIG. 6 illustrates a scan electrode driving IC according to a second embodiment of the present invention.
60 is a block diagram (A) of FIG. 60 and a plan view of a terminal surface (B).

FIG. 7 is a waveform diagram (A) of a conventional swing power supply and a circuit diagram (B) of a level shifter.

[Explanation of symbols]

 101, 601, 602 Optical signal 11, 61, 67 Light receiving section 12 Gate signal generating circuit 13, 63 Signal discriminating circuit 14, 64 Control signal generating circuit 15 Bidirectional shift register 16 Drive circuit 102, 603, 604 Output signal of light receiving section 104 clock 105 start pulse 106 direction control pulse 107 start signal 108 direction control signal VDD, VSS, VM power supply and power supply terminals 42, 608, 609 light-shielding bands 606, 607 terminals TP1,..., TP240 output terminals for driving scanning electrodes

Claims (3)

[Claims] 1. A scanning electrode driving IC of a liquid crystal display device for electrically connecting a connection portion of a transparent mounting substrate and a terminal surface thereof so as to face each other, wherein the scanning electrode driving IC includes a light receiving portion and a gate signal generator. Having a circuit and a pulse discriminating circuit, wherein a path of an optical signal passes through the transparent mounting substrate and reaches a light receiving section formed on the terminal surface, and an output signal of the light receiving section is provided by the gate signal generating circuit and the gate signal generating circuit. A scan electrode driving IC for a liquid crystal display device, wherein the scan signal is inputted to a pulse discrimination circuit, and the gate signal generation circuit outputs a gate signal to the pulse discrimination circuit. 2. The scanning electrode driving IC for a liquid crystal display device according to claim 1, wherein said scanning electrode driving IC is driven by a swing power supply. 3. The scanning electrode driving IC has first and second light receiving portions on upper and lower short sides, respectively, and an optical signal is received by one of the first and second light receiving portions. 2. The scanning electrode driving IC of a liquid crystal display device according to claim 1, wherein a scanning direction is determined by a light receiving unit which is input to the unit and to which the optical signal is input.