JPH11122116A - Device and method for compression - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time needed for operation and to improve the performance of DCT(discrete cosine transformation) or reverse DCT by equipping a DCT device with a transposed matrix storage means and an arithmetic circuit consisting of a combinational circuit for performing DCT operation without using any clocked storage means. SOLUTION: The substitute memory 1118 of the DCT transformation part transform column type data into row type data so as to implement 2nd pass of two-dimensional discrete cosine transformation. Data from an input circuit 1126 and the substitute memory 1118 are multiplexed by a multiplexer 1124 and sent to a mathematical circuit 1122. The result of the mathematical circuit 1122 is sent to an output circuit 1120 after the 2nd pass ends. A control circuit 1116 controls a stream of data in the DCT transforming device. The mathematical circuit 1122 is the combinational circuit which does not have a storage location where an intermediate result is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder for decoding a variable length code into which zero or more variable length bit fields which are not encoded are inserted, and a decoder which does not change some of the codes. About. The present invention also provides a discrete cosine transform (DC) that operates at high speed using a data path without a pipeline or storage means.
T) Related to the device.

[0002]

BACKGROUND OF THE INVENTION In general, large amounts of data are compressed and decompressed for a variety of reasons, including transmission, storage, retrieval, and use in several stage means of variable length coding such as Huffman coding. Huffman coding is based on D. A. Huffman's dissertation, "A Method for Constructing Minimum Redundant Code (" A Method for the Cons
fraction of Minimun Redun
dancy Codes "Proc. IRE, 40: 1
098,1952) ". In many cases, variable-length codes in a coded bit stream are discontinuous,
Another uncoded bit field has been inserted. This bit field represents control and / or format information and / or supplies additional information to the encoded data, including marker headers, marker codes, stuff bytes, padding bits and included additional bits, such as JPEG encoded data. I do.

In variable length coding, different lengths are assigned to different input data based on the likelihood of occurrence of the input data so that statistically frequent input codes are assigned shorter codes than less frequent data. Assign the sign of Infrequent input codes are assigned long codes. Code allocation is done either statistically or adaptively. In the case of statistical assignment, certain data is given the same output code regardless of which data block is processed. For adaptive assignment,
Output codes are assigned based on statistical analysis of a particular set of input blocks or data blocks and expected changes between blocks (or between sets of blocks).

When high speed variable length decoding is required,
Serious problems arise. The problem arises especially when the encoded data stream includes an uncoded variable length bit field into which the encoded data has been inserted (interleaved), as in the JPEG standard. A major difficulty in the fast decoding of such variable-length encoded data is that the decoding of (encoded) data following the length of a particular uncoded bit field, such as the JPEG standard, is complete. Occurs when it cannot be determined otherwise. Since the start position of the next encoded data cannot be known until the decoding of the subsequent code is completely completed, direct pipeline processing cannot be generally used together with the decoder.

[0005] Existing solutions are too slow for many applications, but require several steps (clock cycles) to decode one input data, or one using iterative units. This is whether more than one symbol is pseudo-simultaneously decoded in one stage (clock cycle). However, the addition of additional decoding blocks often makes such decoders economically unbalanced and does not provide the necessary and sufficient speed. This is because multiple decoders do not operate completely in parallel because the start of the next decoder still depends on the processing result of the preceding decoder, which determines the beginning of the next input data. It is. As a result, even if a plurality of symbols are decoded in one stage (clock cycle),
The stage (clock period) is relatively long and would be too slow for many applications as a whole decoder.

[0006] Thus, there is clearly a need for a decoder for variable length codes interleaved with variable length uncoded bit fields that overcomes one or more of the problems of conventional decoders. More specifically, the discrete cosine transform (DCT) device shown in FIG. 77 first performs 1-DDCT on a row of 8 × 8 pixel blocks by performing a complete two-dimensional (2-D) transformation of an 8 × 8 pixel block. It is realized by. Then, another 1-DDCT is performed on the columns of the 8 × 8 pixel block. Such a device is specifically the input circuit 109
6, an arithmetic circuit 1104, a control circuit 1098, a transposed matrix memory circuit 1090, and an output circuit 1092.

[0007] The input circuit 1096 converts the 8 × 8 block into 8
Accept bit pixels. The input circuit 1096 is connected to the arithmetic circuit 1104 by the intermediate multiplexers 1100 and 1102. Arithmetic circuit 1104 performs arithmetic operations on either rows or entire columns of 8 × 8 blocks. Control circuit 10
98 controls all other circuits and implements the DCT algorithm. The output of the arithmetic circuit is the transposed matrix memory 109
0, connected to the register 1095 and the output circuit 1092. The transposed matrix memory is connected to a multiplexer 1100 that provides an output to the next multiplexer 1102. Multiplexer 1102 also receives input from register 1094. The transposed matrix memory 1090 receives 8 × 8 block data in rows and generates data in columns. Output circuit 10
Reference numeral 92 supplies coefficients of DCT performed on an 8 × 8 pixel data block.

In a typical DCT device, since the arithmetic circuit is the most complicated, basically, the arithmetic circuit 1104
Speed determines the overall speed. The arithmetic circuit 1104 in FIG. 77 is configured by dividing the arithmetic processing into several stages described below with reference to FIG. These stages 1114, 1148, 1152,
1156 can be realized by one circuit by a group of commonly used components such as an adder and a multiplier. However, such a circuit 1104 has a drawback that it is slower than an optimized one because a plurality of stages are constituted by one commonly used circuit. This includes storage means used to store intermediate results. The time allocated for the clock cycle of such a circuit must be equal to or greater than the time of the slowest stage in the circuit, and the overall time can be longer than the sum of all stages. Because there is.

FIG. 78 shows an example of the device 4 shown in FIG.
Fig. 3 shows a typical computational data path as part of a stage DCT. The figure does not reflect the actual configuration, but does reflect the function. Four stages 114
Each of 4, 1148, 1152, and 1156 is composed of one reconfigurable circuit. Each of four arithmetic stages 1144 that are 1-DDCT per cycle,
1148, 1152, 1156 are reconfigured. In this circuit, four stages 1144, 1148, 11
Each of 52 and 1156 uses a collection of commonly used ones (adders and multipliers) to minimize hardware.

However, a disadvantage of this circuit is that it is slower than the optimized one. Each of the four stages 1144, 1148, 1152, 1156 is composed of the same group of adders and multipliers. The clock period is determined by the slowest stage, which in this example is 20 ns in block 1144. The delay of the input and output multiplexers 1146 and 1154 (2n each)
s) and the delay of the flip-flop 1150 (3 ns)
Add, the total time is 27 ns. Thus, this DCT element can operate in 27 ns.

[0011] Pipelined DCT elements are also well known. The problem with this configuration is that it requires a lot of hardware. The present invention does not provide the same performance or processing speed, but offers a very good performance versus size compromise. In addition, it offers better speed advantages than most of the current DCT components. Thus, there is a clear need for an improved DCT / inverse DCT method and apparatus that can solve one or more of the problems of the prior art. In particular, there is a clear need for a method and apparatus that can reduce the time required for a central operation circuit for calculating the required result in a DCT / inverse DCT apparatus and improve the performance of the entire DCT or inverse DCT.

[0012]

SUMMARY OF THE INVENTION A first aspect of the present invention is to provide data encoded by a plurality of variable-length codes interleaved with variable-length uncoded bit fields and fixed-length uncoded non-coded bits. A decoding device for a plurality of data blocks having fields, wherein a plurality of variable-length uncoded bit fields and a plurality of variable-length uncoded bit fields are interleaved by removing a plurality of fixed-length uncoded bit fields. A preprocessor for outputting a long code and a plurality of position signals indicating positions of a plurality of fixed-length uncoded fields in a plurality of data blocks; and a variable-length code input between the fixed-length uncoded fields. The position signal is decoded such that the decoded data of the encoded data is output from the decoding device during the position signal corresponding to the fixed-length uncoded field. A decoding apparatus comprising a transfer means for to pass data and synchronized with the output of the decoding device.

Preferably, a first processing unit which has a first barrel shifter set and a first register and processes a plurality of variable length codes interleaved with variable length uncoded bit fields, A second processing unit that has a barrel shifter set and a second register and that processes a plurality of position signals indicating positions of a plurality of fixed-length uncoded fields in the plurality of data blocks; The decoding unit has the same processing unit, and the output of the first and second barrel shifter sets and the first and second processing units receive the same control signal.

According to another preferred configuration, the output of the second processing unit for processing the position signal indicating the position of the fixed-length unencoded field is such that the output from the data stored in the data register is removed during decoding. This is a decoding device used for determining the size of a variable length field. Further, as another preferred configuration, the pre-processing unit removes a plurality of fixed-length uncoded fields, and interleaves a plurality of variable-length uncoded bit fields and a plurality of variable-length uncoded bit fields. The code is defined as a plurality of fixed-length codes consisting of a plurality of fixed-length bit fields, and one of the fixed-length bit fields is either passed or removed in the pre-processing field or passed in the pre-processing field. A decoding device that has a tag indicating the tag, and outputs the tag so that the tag exists before or after the marker indicating the fixed-length uncoded field.

[0015] More preferably, the data block is Huffman coded. Also, a second aspect of the present invention is that a plurality of data blocks each having data encoded by a plurality of variable length codes interleaved with variable length uncoded bit fields and a plurality of data blocks having fixed length uncoded fields which are not coded. A plurality of fixed length uncoded fields, a plurality of variable length codes interleaved with a variable length uncoded bit field and a variable length uncoded bit field, and a plurality of data A preprocessing step of outputting a plurality of position signals indicating the positions of the plurality of fixed-length uncoded fields in the block; and decoding of variable-length coded data input between the fixed-length uncoded fields. As output from the decoding device during the position signal corresponding to the fixed length uncoded field,
And delivering the position signal to the output of the decoding device in synchronization with the data to be decoded.

Preferably, using a first processing unit having a first barrel shifter set and a first register, processing a plurality of variable length codes interleaved with variable length uncoded bit fields; Using a barrel shifter set and a second processing unit having a second register,
Processing a plurality of position signals indicating positions of a plurality of fixed-length uncoded fields in the plurality of data blocks, wherein the first and second processing units are the same;
This is a decoding method in which the output of the second barrel shifter set and the first and second processing units receive the same control signal.

Further, in accordance with the output of the second processing section which processes the position signal indicating the position of the fixed-length uncoded field, the uncoded variable-length data to be removed from the data stored in the data register at the time of decoding. A decoding method further comprising determining a size of a field. Preferably, in the preprocessing unit step, a plurality of fixed-length uncoded fields are removed, and a plurality of variable-length codes interleaved with a variable-length uncoded bit field and a variable-length uncoded bit field are replaced with a plurality of variable-length codes. As a plurality of fixed-length codes consisting of fixed-length bit fields, and having a tag indicating that one fixed-length bit field has been passed or removed in the preprocessing field, or passed in the preprocessing field. , And a tag is a decoding method in which a tag is output so as to exist before or after a marker indicating a fixed-length uncoded field.

Preferably, the data block is Huffman coded. In the following detailed description, attention should be paid especially to FIGS. 82 to 91 and the description related thereto, as well as other descriptions. A third aspect of the present invention is a discrete cosine transform (DCT) device, wherein the transposed matrix storage means is interconnected with the transposed matrix storage means, and
This is a DCT device having an arithmetic circuit composed of a combinational circuit for performing a DCT operation without using d storage means.

Preferably, the combination circuit has a predetermined number of stages for performing a DCT operation, and the stages are sequentially arranged DCT devices. Also preferably, DC
This is a DCT device having multiplexing means for multiplexing data input to the T device and output of the transposed matrix storage means.
A DCT having control means for controlling the operation of the DCT device;
T device.

The fourth aspect of the present invention is the inverse discrete cosine transform (D
CT) apparatus, comprising: a transposed matrix storage means; and a clocked storage interconnected with the transposed matrix storage means.
This is an inverse DCT apparatus having an arithmetic circuit mainly including a combinational circuit for performing a DCT operation without using the e-means.

A fifth aspect of the present invention is a discrete cosine transform (DCT) method for data, in which a DCT operation is performed using a clock.
a step of performing a DCT operation on input data in a first direction using an operation circuit mainly including a combination circuit performed without d storage means; and a step of performing a DCT operation on the input data subjected to DCT in a first direction. Storing the data in the transposed matrix storage means using the arithmetic circuit and performing DCT operation on the data stored in the transposed matrix storage means in accordance with the second direction to obtain transformed data. Is the way.

Preferably, the DCT method is a DCT method in which the DCT is calculated in a predetermined number of stages arranged sequentially, and the method may further include a step of multiplexing the input data and the output of the transposed matrix storage means. . Sixth Embodiment
Is the inverse discrete cosine transform (DCT) method, and the inverse D
A step of performing a DCT operation by adjusting an input coefficient in a first direction using an operation circuit mainly including a combination circuit that performs a CT operation without clocked storage means; and adjusting an input coefficient subjected to DCT in a first direction. Storing the coefficients in the transposed matrix storage means interconnected with the combinational circuit, and performing an inverse DCT operation on the coefficients stored in the transposed matrix storage means in accordance with the second direction using an arithmetic circuit to obtain inverse transformed data. And a step of obtaining.

In the following detailed description, particular attention should be paid to FIGS. 79, 80 and 81 and the related description, as well as other descriptions.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

Table of Contents 1.0 Brief Description of the Drawings 2.0 Table List 3.0 Preferred and Alternative Embodiments 3.1 Overview of Multiple Stream Architectures 3.2 Host / Coprocessor Queuing 3.3 Coprocessor 3.4 Format of multiple streams 3.5 Judgment of current active stream 3.6 Fetch instruction of current active stream 3.7 Decode and execute instruction 3.8 Update register of instruction controller 3.9 Register access Semaphore semantics 3.10 Instruction controller 3.11 Description of local register file module 3.12 Register read / write processing 3.13 Memory area read / write processing 3.14 C bus structure 3.15 Coprocessor data Type and data operation 3.16 Data normalization processing 3.17 image processing accelerator card 3.17.1 Synthesis 3.17.2 color space conversion instruction a. Single output color space (SOGCS) conversion mode b. From multiple outputs-spatial mode 3.17.3 LPEG encoding / decoding a. Encoding b. Decoding 3.17.4 Table index 3.17.5 Data encoding instruction 3.17.6 High-speed DCT device 3.17.7 Huffman decoding 3.17.8 Image conversion instruction 3.17.9 Convolution instruction 3 .17.10 Matrix multiplication 3.17.11 Gray scale (halftone) 3.17.12 Hierarchical image format decompression 3.17.13 Memory copy instruction a. General-purpose data move instruction b. Local DMA instruction 3.17.14 Flow control instruction 3.18 Accelerator card module 3.18.1 Pixel organizer 3.18.2 MUV buffer 3.18.3 Result organizer 3.18.4 Operand organizer B, C 3 .18.5 Main data path unit 3.18.6 Data cache controller and cache a. Normal cache mode b. Single output general color space conversion mode c. Multiple output general color space conversion mode d. JPEG encoding mode e. Low speed JPEG decoding mode f. Matrix multiplication mode g. Disable mode h. Invalidation mode 3.18.7 Input interface switch 3.18.8 Local memory controller 3.18.9 Other modes 3.18.10 External interface controller 3.18.11 Peripheral interface controller Table index Table 1: Register Description Table 2: Opcode Description Table 3: Operand Type Table 4: Operand Description Table 5: Module Setup Order Table 6: C Bus Signal Definitions Table 7: C Bus Transaction Types Table 8: Data Manipulation Register Format Table 9: Desired Data type Table 10: Explanation of symbols Table 11: Combination processing Table 12: Address combination for SOGCS mode Table 12A: Instruction encoding for color space conversion Table 13: Huffman and quantization table stored in data cache Table 15: Fetch address Table 16: Huffman coding table Table 17: Huffman and quantization table bank address Table 18: Instruction Word-Minor Opcode Field Table 19: Instruction Word-Minor Opcode Field Table 20: Instruction Operand-Result Word Table 21: Instruction Word Table 22: Instruction Operand-Result Word Table 23: Instruction Word Table 24: Instruction Operand- Result Word Table 25: Instruction Word-Minor Opcode Field Table 26: Instruction Word-Minor Opcode Field Table 27: Fractional Table Description of preferred and other embodiments "In a preferred embodiment,
Significant advantages have been obtained by performing hardware rastering through the use of two independent instruction streams by a hardware accelerator. Thus, while the first instruction stream is preparing to print the current page, the next instruction stream can prepare to print the next page. Hardware resources can be used particularly efficiently when the hardware accelerator can operate at a speed higher than the output device.

The preferred embodiment shows a configuration using two instruction streams. However, a configuration using two or more instruction streams is also possible, and the advantage of using more streams can be obtained in view of hardware trade-off. By using two streams, the hardware resources of the raster image coprocessor can be used to transfer the current page, band, strip, etc., to the printing device, depending on the output device, and to transfer subsequent pages, bands, strips, etc. Always be involved in preparation. 3.1 General Configuration of Multiple Stream Architecture FIG. 1 is a diagram schematically illustrating a computer hardware configuration 201 including a preferred embodiment. The configuration 201 includes a standard host computer system comprising a host CPU 202 connected to a host storage memory 203 via a bridge 204. The host computer system contains operating system programs,
General computer system functions such as applications and information displays are provided, and the host computer system is connected to the standard PCI bus 206 via the PCI bus interface 207. In addition, PC
The I standard is a well-known industry standard, and most computer systems on the market, especially those with the Microsoft Windows ™ operating system, have a PCI bus 206. PC
By using the I bus 206, the PCI bus interface 210, other devices 211, and the local memory 2
One or a plurality of PCI cards (for example, 209) further including the T.12 or the like can be easily used by being added to the configuration 201.

In a preferred embodiment, a raster image accelerator card 220 is provided to speed up graphics processing expressed in a page description language. Raster image accelerator card (PCI bus interface 22
1) is designed to operate in the form of a shared memory loosely coupled to the host CPU 202 like other PCI cards 209 and the like. If necessary, the image accelerator card 220 can be further added to the host computer system. The raster image accelerator card is for accelerating complicated and large amount of operation processing in the raster image processing operation. These operations include (a) synthesis (b) generalized color space conversion (c) JPEG code (D) Huffman, run-length, predictive encoding / decoding (e) Hierarchical image (trademark) decoding (f) Generalized affine image transformation (g) Small kernel convolution operation (convolution) (h) Matrix Operation (i) Halftone processing (j) Batch arithmetic / memory copy operation The raster image accelerator card 220 further includes a local memory 22 connected to a raster image coprocessor 224.
3 and the raster image coprocessor 224
The raster image accelerator card 220 is activated based on a command from U202. Here, the coprocessor 22
4 is desirably an application specific LSI (ASIC). Also, the raster image coprocessor 224 has the ability to control at least one required printer device 226 via the peripheral interface 225. Further, the image accelerator card 220 can control input / output devices such as a scanner. In addition, the accelerator card 220 includes a general external interface 227 connected to the raster image coprocessor 224, and can perform monitoring and testing. .

In the execution mode, the host CPU 202
A series of commands and data are transmitted via the CI bus 206,
The raster image coprocessor 224 performs an image generation process. The transmitted data is stored not only in the local memory 223 but also in the cache 23 in the raster image coprocessor 224.
0 or stored in a register 229 in the coprocessor 224.

FIG. 2 shows the raster image coprocessor 224 in more detail. The coprocessor 224 is for accelerating the above-described processing, and includes an instruction control unit 2
It consists of a plurality of sites under the control of 35. The coprocessor includes a local memory controller 236 for communicating with the local memory 223 of FIG. 1 for communicating with the outside world. The peripheral interface control unit 237 is used for communication with the printer device, and uses a standard format such as a Centronics interface standard format or another video interface format. The peripheral interface controller 237 is internally connected to the local memory controller 236. The local memory control unit 236 and the external interface control unit 238 are connected via an input interface switch 252, and the input interface switch 252 is connected to the command control unit 235. Input interface switch 252 is also connected to pixel organizer 246 and data cache control 240. The input interface switch 252 is connected to the external interface control unit 23
7 and the data from the local memory control unit 236 are switched and transferred to the instruction control unit 235, the data cache control unit 240, and the pixel organizer 246.

The external interface control unit 238 operates as shown in FIG.
A command control unit 235 is provided in the raster image coprocessor 224 for communicating with the PCI bus 206 therein.
Is connected to Further, another module 239 connected to the instruction control unit 239 and operating in cooperation with the coprocessor 224 is provided for performing test diagnosis and inputting a clock signal and a global signal.

The data cache 230 operates under the control of the connected data cache control unit 240.
The data cache 230 is used in various applications, but is primarily used to store recently used values that are likely to be subsequently used in the coprocessor 224. In the above-described high-speed processing, processing of a plurality of data streams is mainly performed by the JPEG encoder / decoder 241 and the main data path unit 242. Part 241,
242 is connected in parallel to a pixel organizer 246 and two operand organizers 247,248. The processed streams from the parts 241 and 242 are transferred to the result organizer 249, where processing and reformatting are performed if necessary. Since it is often desired to record an intermediate result, in addition to the data cache 230, a multi-value (MUV) value is provided between the pixel organizer 246 and the result organizer 249.
A buffer 250 is provided. Result Organizer 249
Are output to the external interface control unit 238, the local memory control unit 236, and the peripheral interface control unit 237 if necessary.

As shown by the dotted line in FIG. 2, a further (third) data path section 243 is divided into two other data paths such as a JPEG encoder / decoder 241 and a main data path section 242 by " A "parallel" connection is also possible. It is equally possible to configure four or more data paths. Note that the paths are connected "in parallel," but do not operate in parallel, only one path operates at a time.

The overall design of the ASIC shown in FIG. 2 is based on the following concept. First, it is essential that the print page does not cause small or temporary image quality deterioration. In a video signal, even if such a small image quality deterioration exists, it is not perceived by human eyes, but in a printed matter, a small image quality deterioration is permanently left on a printed page and may become conspicuous. Because. Further, if a delay occurs before reaching the printer, a white unprinted portion may be formed on the page while the page is moving inside the printer, which is unsightly. For this reason, it is essential to provide high-quality and high-speed results, and an approach relying on high-speed hardware is preferable to an approach using software.

Second, all the various operation steps (algorithms) necessary for executing the printing process are listed, and the hardware corresponding to each step is arranged. And it is very expensive. Also, the operation speed of hardware is essentially limited by the rate at which data required for processing is fetched or data generated by processing is transferred. That is, the operation speed is restricted by the bandwidth of the interface.

On the other hand, in the overall ASIC design, when the total amount of hardware is schematically represented, (a) various parts of necessary hardware overlap,
(B) It is based on the surprising fact that they are not performed simultaneously. In particular, this point is conspicuous in the overhead when transferring data before processing the data.

From this point of view, after several steps, it was decided to reduce the amount of hardware while keeping all parts of the hardware as active as possible. In the first step, it was recognized that image manipulation often required the same basic type of repetitive operation. Therefore, when data is input in the form of a stream, the processing unit is configured to perform a specific process, processes a long data stream, and then reconfigures the processing unit to match the next required processing type. If the data stream is fairly long, the time required for reconstruction is negligibly short compared to the overall processing time, thus improving throughput.

When a plurality of data processing paths are provided,
By reconfiguring one path while using another path, waste of time required for reconfiguration can be eliminated.
In other words, while the main data path unit 242 is executing more general-purpose processing, the other data path
If there is a JPEG encoding / decoding such as 41, or an additional portion 243, more specialized processing such as entropy encoding or Huffman encoding can be performed.

Further, while the processing is in progress, data can be fetched or transferred to the processing part. Also,
By standardizing and unifying various types of data, the speed can be further increased, and hardware resources can be used effectively. Therefore, the overall overhead related to data fetch and transfer can be reduced.

What is important here is that the coprocessor 224
Is executed under the control of the host CPU 202 (FIG. 1). At this point, the instruction control unit 235 supervises control of the entire coprocessor 224. Command control unit 235
Operate the coprocessor 224 by a control bus 231 called CBus (C bus). CBus231
Is a set register (2 in FIG. 1) in each module.
31) is connected to each of the modules 236-250, and enables the entire operation of the coprocessor 224. In order to make FIG. 2 easier to see, FIG.
The connections from 1 to the respective modules 236-250 are not shown.

FIG. 3 is a diagram showing a schematic layout 260 of available module registers. The layout 260 includes a register 261 for overall control of the coprocessor 224 and an instruction control unit 235. Coprocessor modules 236-260 include a similar register 262. 3.2 Host / Coprocessor Queuing According to the architecture described above, the host processor 20
It can be seen that sufficient coordination between the image coprocessor 2 and the image coprocessor 204 is required. However, the solution to this is general and not specific to the above-described architecture, and will be described below assuming a more general computing hardware environment.

Modern computer systems require some form of memory management to perform dynamic memory allocation. Systems having one or more coprocessors require a technique for synchronizing dynamic memory allocation and memory usage by the coprocessors. A general computer hardware configuration includes a CPU and a special coprocessor, each of which shares a series of memory groups. In such a system, only the CPU is the only part in the system to which the memory can be dynamically allocated. Once the CPU allocates the memory for use by the coprocessor, the coprocessor is free to use the memory until the memory is no longer needed and is released by the CPU. That is, some kind of synchronization is required between the CPU and the coprocessor to ensure that the memory is released after the coprocessor has finished using the memory. Although various solutions have been suggested for this synchronization, it is not always preferable in terms of performance.

Using a statically allocated memory,
Although synchronization problems can be avoided, it is not possible to dynamically adapt memory resource utilization. Similarly, it is possible to block the CPU and wait until the coprocessor completes execution of the processing, but it loses parallelism and sacrifices overall system performance. Although it is possible to use an interrupt signal for notifying the end of the processing from the coprocessor, if the throughput of the coprocessor is extremely high, a large processing overhead is required.

In addition to high performance requirements, such systems must flexibly address dynamic memory starvation. While many computer systems allow various memory size configurations, it is important to maximize available resources and maximize performance in systems with many memories. Similarly, a system with a minimum memory size configuration should be able to operate satisfactorily with a small amount of memory, and its performance should be degraded gently at least in the case of memory shortage.

To solve these problems, there is a need for a synchronization mechanism that maximizes system performance and dynamically adapts coprocessor memory usage to system capacity and the complexity of the processing performed. FIG. 4 shows a (host) CPU.
A preferred configuration for synchronizing with the coprocessor is shown. The reference numbers in the figure are the same as those used in the description of FIG.

Referring to FIG. 4, a CPU 202 controls all memory management in the system. CPU 202
Allocates the memory 203 for use by itself or by the coprocessor 224. The coprocessor 224 has a graphics-specific instruction set, and can execute the instruction 1022 from the memory 203 shared with the host processor 202. Each of these instructions can write the result 1024 to the shared memory 203, and can also read operands from the memory 203. Where operand 10 of the coprocessor instruction
The amount of the memory 203 required to store 23 and the result 1024 depends on the complexity and type of the processing.

CPU 202 also performs a process of generating instruction 1022 to be executed by coprocessor 224.
To maximize the parallelism between CPU 202 and coprocessor 224, the instructions generated by CPU 202 are queued as shown at 1022 and then executed on coprocessor 224. Queue 1022
Each instruction in the host CP
The operand 1023 and the result 1024 in the shared memory 203 allocated by the U 202 can be referred to.

As shown in FIG. 5, an instruction generation unit 1030, a memory management unit 1031, and a queue management unit 1032 are connected to perform these processes. All of these modules execute on host CPU 202 as a single process. The execution instruction in the coprocessor 224 is generated in the instruction generation unit 1030, and the memory management unit 1
The area for the operand 1023 and the result 1024 of the instruction generated using the service 031 is allocated.
The instruction generation unit 1030 uses the service of the queue management unit 1032 to queue instructions to be executed by the coprocessor 224.

When each instruction is executed by the coprocessor 224, the CPU 202 can release the memory allocated by the memory management unit 1031 for the operand of the instruction. The result of one instruction can be the operand of the next instruction, after which the memory is released by the CPU. Rather than sending an interrupt signal and releasing memory at the same time as the coprocessor 224 finishes the instruction, at some point after the coprocessor 224 finishes the instruction, the cleanup mechanism is activated to save the resources required for processing the instruction. System frees. The point at which the cleanup mechanism is activated depends on the relationship between the memory management unit 1031 and the queue management unit 1032, and is dynamically determined according to the amount of available system memory and the amount of memory required for each coprocessor instruction. Can be adapted.

FIG. 6 shows the coprocessor instruction queue 1022.
FIG. 3 is a diagram schematically showing the configuration of FIG. Instruction group is host CP
It is inserted into pending instruction queue 1040 by U202 and read and executed by coprocessor 224. When the execution process in the coprocessor 224 is completed, the instruction is transferred to the cleanup queue 1041, and after the coprocessor 224 completes processing, the resources required by the instruction are released.

The instruction queue 1022 itself is configured as a fixed or dynamically variable size circular buffer. The instruction queue 1022 separates the generation of the instruction by the CPU 202 and the execution of the instruction in the coprocessor 224.
The operand and the result memory of each instruction are stored in the memory management unit 103 according to a request from the instruction generation unit 1030 when the instruction is generated.
1 (FIG. 5). The memory allocation for newly generated instructions triggers the cooperative operation of memory manager 1031 and queue manager 1032, described below, and the system automatically adapts to the amount of available memory and the complexity of the instructions. I can do it.

The instruction queue management unit 102 can wait until the coprocessor 224 finishes executing the instruction generated by the instruction generation unit 1030. However, if the instruction queue 1022 and the memory 203 allocated by the memory management unit 1031 are large enough, it is not necessary to wait for the coprocessor 224 at all, or at least not until all the instruction sequences are completed. In a large job, these waiting times extend for several minutes, so that the effect is large. However, peak memory usage can easily exceed available memory. At this point, a cooperative operation is started between the queue management unit 1032 and the memory management unit 1031.

The instruction queue management unit 1032 may be appropriately instructed to “clean up” the completed instruction and release the dynamically allocated memory. When the memory management unit 1031 detects that the available memory is decreasing or runs out, it instructs the queue management unit 1032 to perform a cleanup process, and releases the memory that is no longer used by the coprocessor 224. Take measures to make it happen. Accordingly, the memory management unit 1031 can satisfy a memory request required for a newly generated instruction from the instruction generation unit 1030 without the CPU 202 waiting for the coprocessor 224 or synchronizing with the coprocessor 224.

From the memory management unit 1031 to the queue management unit 1
If the request to clean up the end instruction is issued in 032 and the memory sufficient to satisfy the new request of the instruction generation unit is not released, the memory management unit 1031 sends the pending instruction queue 104 to the queue management unit 1032.
Requests to wait until some, for example half, of the in-flight instructions in 0 are completed. Thereby, the coprocessor 224
CPU 202 processing will be blocked until some of the instructions are completed. Upon completion of some of the coprocessor 224 instructions, the operands of those instructions are freed, leaving enough memory to satisfy the request. By waiting for only a portion of the instructions being processed, at least some of the instructions are in the pending instruction queue 1040 and the coprocessor 224 is always running. In many cases, by cleaning up a part of the pending instruction queue 1040 in which the CPU 202 waits, sufficient memory is released for the memory management unit 1031 and the request of the instruction generation unit 1030 can be satisfied.

In a special case in which the memory sufficient to satisfy the request is not released even if the coprocessor 224 waits until, for example, half of the pending instructions have been executed, the memory management unit 1031 will execute all pending commands. One last resort is to wait for the processor instruction to finish. Except for very large and complex jobs that would exceed the current memory capacity of the system, this frees up enough resources to satisfy the requirements of the instruction generator 1030.

By the cooperative operation of the memory management unit 1031 and the queue management unit 1032, the throughput can be efficiently maximized in the memory amount 203 given to the system. With more memory, the need for synchronization is reduced and greater throughput can be obtained. Conversely, for less memory,
The coprocessor 224 often waits until the processing using the scarce memory 203 is completed, and even if the available memory is small, the coprocessor 224 operates but the performance deteriorates.

The processing steps performed by the memory management unit 1031 when satisfying the request from the instruction generation unit 1030 are summarized below. Each step is executed sequentially, and after the step, the memory management unit 1031 has sufficient memory 20 to satisfy the request.
Check if 3 is obtained. If sufficient memory is available, the request is satisfied and the step ends.
If not, it proceeds to the next step and proceeds to more radical processing to satisfy the request. 1. 1. Attempt to satisfy the request with available memory 203 2. Clean up all completed instructions. 3. Wait for part of the pending instruction to end. Wait for all pending instructions to finish Note that it turns out to wait for a different part of the pending instructions (eg, 1/3 or 2/3) or use a lot of memory to satisfy the request. Other options may be used, such as waiting for a particular instruction being performed.

In FIG. 7, in addition to the cooperative operation between the memory management unit 1031 and the queue management unit 1032, when the fixed-length instruction queue buffer 1050 overflows, the queue management unit 1032 synchronizes with the coprocessor 224. Can also be taken. Such a situation is shown in FIG. 7, where the pending instruction queue 1040 is a queue of ten instructions long. When the area overflows, the newest instruction is stored at location 9 because the newest instruction to be added has the largest number. The next instruction to be input to coprocessor 224 is waiting at location 0.

When the area overflows, the queue management unit 10
32 waits until the coprocessor 224 completes processing, for example, half of the pending instruction. This waiting frees enough space for new instructions that would normally be inserted by the queue manager 1032. The operation of the queue management unit 1032 when scheduling a new instruction is as follows. 1. 1. Test if enough space remains in instruction queue 1040 If there is not enough space left, the coprocessor waits for a given number of instructions to complete. Inserting a New Instruction in Queue The operation of the queue management unit 1032 instructed to wait for an instruction to end is as follows. 1. 1. Wait until instructed by coprocessor 224 that the instruction has been completed. If there is a completed instruction that has not been cleaned up, the next completed instruction is deleted from the queue. The operation of the instruction generation unit 1030 when generating a new instruction is as follows. 1. 1. Request memory required for the instruction operand 1023 from the memory management unit 1031. 2. Generate instructions to transfer A coprocessor instruction is transferred to the queue management unit 1032 and executed. An example of the above operation process in the form of pseudo code is shown below.

If there is not enough memory available to satisfy the ALLOCATE_MEMORY BEGIN IF request, then THEN clean up all instructions that have completed THEN If there is not enough memory available to satisfy the ENDIF IF request Then, it calls THEN WAIT_FOR_INSTRUCTION and waits for the completion of half of the pending instruction. If there is not enough memory available to satisfy the ENDIF IF request, it outputs a THEN error and returns. ENDIF returns the allocated memory. Queue management SCHEDULE_INSTRUCTION BEGINIF If there is not enough space in the instruction queue, THEN waits for a certain number of instructions until the coprocessor finishes. ENDIF queues new instructions END WAIT_FOR_INSTRUCTION (i) BEGIN Wait until the coprocessor indicates that the instruction i has finished WHILE There are instructions that have been finished but not cleaned up DO IF The next finished instruction has a cleanup function Call the THEN clean-up function ENDIF Delete the finished instruction from the queue DONE END Instruction generation unit GENERATE_INSTRUCTIONS BEGIN ALLOCATE_MEMORY is called, and the memory required for the instruction operand is allocated in the memory management unit. The transfer instruction is generated. SCHEDULE_INSTRU Coprocessor END 3.3 Coprocessor transfers instructions to queue management unit for execution Description of the registers of the coprocessor 224 as described in FIGS.
Comprises a plurality of registers for executing each instruction stream.

For the modules in FIG. 2, Table 1 shows the names, types, and descriptions of registers used in the coprocessor 224, and Appendix B describes each field of each register. Register description

[0060]

[Table 1A]

[0061]

[Table 1B]

[0062]

[Table 1C]

[0063]

[Table 1D]

[0064]

[Table 1E]

[0065]

[Table 1F]

[0066]

[Table 1G]

The following should be noted in these registers. (A) Instruction pointer registers (ic_ipa and ic_i
pb). These register pairs store the virtual address of the currently executing instruction. Instructions are fetched and executed in ascending virtual address order. When control transfers to a discontinuous virtual address, a jump instruction is used. Each instruction is assigned a 32-bit sequence number, and the sequence number increases by one for each instruction. The sequence number is used by both the coprocessor 224 and the host CPU 202 to synchronize the generation and execution of instructions. (B) End registers (ic_fna and ic_fnb).
These register pairs store the sequence numbers of completed instructions. (C) ToDo registers (ic_tda and ic_td
b). These register pairs store the sequence numbers of the queued instructions. (D) Interrupt registers (ic_inta and ic_
intb). These register pairs store a sequence number to be interrupted. (E) Interrupt status register (ic_stat.a)
_Primed and ic_stat. b_prime
d). These register pairs store a prime bit which is a flag for activating the interrupt when the interrupt and end registers match. This bit is stored in the same manner as other interrupt enable bits and other status / configuration information in the interrupt status (ic_stat) register. (F) Register access semaphores (ic_sema and ic_semb). The host CPU 202 must obtain a semaphore prior to high-speed access to the coprocessor 224, that is, register access that requires one or more register writes. On the other hand, a register access that does not require high speed can be executed at any time. A disadvantage associated with host CPU 202 obtaining the semaphore is that coprocessor execution is suspended until the currently executing instruction has completed. The register access semaphore is
4 as one bit of the configuration / status register.
These registers exist in the register area of the instruction control. As described above, each sub-module of the coprocessor has a configuration / status register, and the register is set during normal instruction execution. All these registers are represented on a register map, many of which are modified implicitly in instruction execution. The host can know the contents of these registers via the register map. 3.4 Multiple Stream Format As described above, for maximum resource utilization and high speed output to external peripherals, coprocessor 224 executes one of two independent instruction streams. . Normally, one instruction stream corresponds to the current output page needed by the output device at the right time, and 2
The first instruction stream utilizes the modules of coprocessor 224 when other instruction streams are idle. Here, the most important point is to output necessary output data at an appropriate time, and to make maximum use of resources for preparing subsequent pages and bands. Accordingly, coprocessor 224 is designed to execute two instruction streams (hereinafter referred to as A and B) that are completely independent but are executed in a similar manner. The instructions are generated by software running on the host CPU 202, and are executed by the raster image accelerator card 22.
0 and is preferably executed by coprocessor 224. In normal operation, one of the instruction streams (stream A) operates at a higher priority than the other instruction stream (stream B). The instruction stream or queue is written to one or more buffers in host RAM 203 (FIG. 1). The buffer is allocated at the start and is fixed in the physical memory of the host 203 during the execution of the application. Each instruction is the host RA
It is preferably stored in the virtual memory environment of M203, and the raster image coprocessor 224 performs the conversion from the virtual address to the physical address and determines the corresponding physical address in the host RAM 203 as the position of the next instruction. These instructions are stored sequentially in the local memory of the coprocessor 224.

FIG. 8 is a diagram showing the format of two streams A and B stored in the host RAM 203. The format of each of streams A and B is essentially the same. A simple execution model in the coprocessor 224 consists of: * Two instruction virtual streams, A stream and B stream * Normally only one instruction is executed at a time * Either stream can have priority or "round robin" priority * Can be "locked" on either stream, regardless of stream priority or the ability of other streams to execute instructions.
Can be executed reliably * Either stream may be empty * Either stream may not be available * Either stream must have subsequent instructions "overlapping" For example, instructions may include instructions that "overlap" the execution of the next instruction. * Each instruction has a "unique" sequence number that increments by 32 bits. * Each instruction The instruction control unit 235 may have a code for stopping an interrupt or the execution of an instruction. An instruction execution model of the coprocessor is implemented to control execution and fetch instructions from the host RAM 203 when necessary. Instruction control unit 2 for each instruction
35 decodes the instruction, configures various registers in the module via the CBus 231 and performs processing for causing the module to execute the instruction.

FIG. 9 is a diagram schematically showing an instruction execution cycle executed by the instruction control unit 235. The instruction execution cycle consists of four main stages 276-279.
The first stage 276 checks whether the instruction is pending in the instruction stream. If so, fetch the instruction and 277;
Decrypt and execute 278, update register 27
9. 3.5 Determining the current active stream In the first stage, two steps must be performed. 1. 1. Determine if the instruction is pending Determining Which Instruction Stream to Fetch Next To determine which instruction is pending, look at the following possibilities: 1. 1. Whether the instruction control unit is enabled 2. Whether the instruction control unit is paused due to an internal error or interrupt. 3. Whether any external error conditions are pending. 4. Whether the A or B stream is locked 5. Whether either stream sequence number is enabled Whether Either Stream Has Pending Instructions The following pseudo code illustrates an algorithm that determines whether an instruction is pending based on the above rules. This algorithm can be implemented as hardware in the instruction controller 235 via a state transition machine using known techniques.

If not in error mode, is in operation mode, is not in bypass mode, and is in self-diagnosis mode. IfA stream is locked and not paused. IfA stream is in operation mode, and “sequence of A stream The instruction number is paused or there is an instruction in stream A. The instruction is pending else The instruction is not pending end if else if B stream is locked and not paused if B stream is in active mode And "the sequence number of the B stream is paused, or there is an instruction in the B stream." The instruction is pending else The instruction is not pending end if else / * The stream is not locked * / if A Stream running mode Is not paused, and "the sequence number of the A stream is paused, or there is an instruction in the A stream" The instruction is pending else The instruction is not pending end if end if else / * Interface control unit Is not running * / instruction is not pending end if If no instruction is pending, instruction controller 235 goes into a "spin" or idle state until a pending instruction is found.

The next state is examined to determine which stream is active and which stream to execute next. 1. 1. Which stream is locked? 2. Which priority is given to the streams A and B, and which instruction stream was executed last? 3. Which stream is running? Which Stream Has Pending Instructions The following shows the pseudo code implemented by the instruction controller, and shows how to determine the next active stream.

If stream A is locked Next stream is A else if B stream is locked Next stream is Belse / * Neither stream is locked * / if A stream is in operation mode And "the sequence number of stream A is paused or there is an instruction in stream A", and "the stream B is in operation mode and the sequence number of stream B is paused or there is an instruction in stream B" Otherwise, the next stream is Aelise if the B stream is in operation mode, "the sequence number of B stream is paused, or there is a pending command in B stream", and "the A stream is in operation mode. "The sequence number of stream A is paused, If there is no instruction in the stream, then the next stream is Belse / * neither stream has instructions * / if pri = 0 / * A high, B low * / the next stream is A else if pri = 1 / * A low, B high * / The next stream is Belse if pri = 2or3 / * Round robin * / if The last stream is A next, the next stream is Belse, and the next stream is A end if end if end if Since the end if condition is constantly changing, it is necessary to check all conditions in a short time. 3.6 Fetch Instruction of Current Active Stream When the next active instruction stream is determined, the instruction control unit 235 causes the corresponding instruction pointer register (ic_ip
Fetch an instruction using the address in a and ic_ipb). However, the valid instruction is already
If it exists in the prefetch buffer in 35,
The instruction control unit 235 does not fetch an instruction.

An instruction in the prefetch buffer becomes valid when the following conditions are satisfied. 1. 1. Prefetch buffer is valid The instructions in the prefetch buffer are from the same stream as the current active stream. The validity of the contents of the prefetch buffer is ic_sta
Represented by a prefetch bit in the t register, which is set when the instruction prefetch is successful. Note that external writing to any register of the instruction control unit 235 invalidates the contents of the prefetch buffer. 3.7 Decryption and Execution Instructions When an instruction is fetched and accepted, the instruction control unit 235
Coprocessor 2 decodes the instruction and executes the instruction.
24 registers 229 are configured.

The command format used in the raster image coprocessor 224 is such that the command is generated by the host CP.
It differs from the conventional processor instruction set in that it is executed by an instruction from U202 and has direct overhead to the host. The instruction is the host RAM
The instructions should be as small as possible because they are stored in 203 and transferred to the coprocessor 224 via the PCI bus 206 of FIG. Preferably, coprocessor 224
Is desirably started by a single instruction.
It is also desirable to maintain the flexibility of the instruction set as much as possible in order to be able to cope with future changes. Further, the instructions executed in coprocessor 224 are also applicable to long streams of operand data, preferably for optimal performance. In addition,
As instruction decoding "philosophy" used by the coprocessor 224,
Decoding of “general instructions” is performed simply and at high speed, and coprocessor 22 is used for “uncommon” processing.
The design is adopted so that the host system can perform fine control for the operation of No. 4.

FIG. 10 shows a single instruction 280 format, each consisting of 8 words of 32 bits.
Each instruction includes an instruction word (opcode) 281 and an operand or result type data word 282 indicating the type of the operand. Addresses 283-285 for the three operands A, B, C are also included along with the result address 286. Further, an area 287 is also included for storing information related to an instruction used by the host CPU 202.

FIG. 11 is a diagram showing the structure 290 of the instruction opcode 281 of the instruction. The instruction opcode is 32 bits long and includes a main opcode 291, a complementary opcode 292,
Includes interrupt (I) bit 293, partially decoded (Pd) bit 294, register length (R) bit 295, lock (L) bit 296, and length 297. Instruction word 2
A description of each of the 90 fields is provided in the table below.

Description of Opcode

[0078]

[Table 2A]

[0079]

[Table 2B]

By setting the I bit field 293, the instruction can be coded so that execution of the instruction is interrupted and paused when the instruction is completed. This interrupt is called an "instruction end interrupt". The partially decoded bit 294 is such that when the bits of the partially decoded bit 294 are set and the operating mode is set in the ic_cfg register, various modules are microcoded prior to execution of the instruction as described below. Provides a partial decoding function. The lock bit 296 is used for processing that requires one or more instructions to start. At this time, various registers are set prior to the instruction, and the current instruction stream is "locked" for the next instruction. When the L bit 296 is set, the next instruction is fetched from the same stream when the instruction is completed. Length field 297 is a general definition of each instruction, defined as the number of "input data items" or "output data items" required,
It is 16 bits long. In the case of processing for a stream of 64,000 or more input data items, the R bit 295 is set and the pixel organizer 24 of FIG.
6 is obtained from the po_len register. The register is set immediately before such an instruction.

In FIG. 10, the number of operands 283 to 286 required for an instruction is variable depending on the instruction type used. The following table shows the number of operands and the definition of the length for each instruction type. Operand type

[0082]

[Table 3]

FIG. 12 is a diagram of FIG. 1 for a three-operand instruction.
0 shows a data word of 0, a data word format 300 of an operand descriptor 282, and a data word format 301 for a two-operand instruction. The following table details the encoding of the operand descriptor. Operand descriptor

[0084]

[Table 4]

In the above table, in the case of the fixed data address mode, the coprocessor 224 fetches or calculates one internal data item, and uses this item as the instruction length of the operand. In the case of the tile address mode, the coprocessor 224 cycles some data to obtain a “tile effect”. If the L bit of the operand descriptor is zero, the data is short, meaning that the data item is present in the operand word.

In FIG. 10, each operand /
Result words 283-286 include a 32-bit virtual address that indicates the value of the operand itself or the start position of the operand / result where the data is stored. The instruction control unit 235 in FIG. 2 decodes the instruction in two stages. First, it checks whether the main opcode of the instruction is valid, and generates an error if the main opcode (FIG. 11) is invalid. Next, by setting various registers via the CBus 231, the instruction control unit 235 executes the instruction and performs the operation specified by the instruction. Note that there are instructions for which there is no register to be set.

The registers of each module are classified into several types according to the operation. First, there is a status register type, which is "only read" from other modules
Some are "read / written" by a module including a register. Next, the first type of configuration register (hereinafter config1) is externally "read / write" from the module and "read only" from the module containing the register. These registers are generally used when storing large type configuration information such as address values. The second type of configuration register (hereinafter config2) can be read and written from all modules, but can only be read from modules containing registers. This register type is used when addressing for each bit of the register is required.

There are various types of control type registers. The first type (hereinafter, control1 register) can be read / written by all modules (including modules including registers). The Control1 register is used when storing large control information such as an address value. Similarly, a second type of control register (hereinafter, control2)
Is set for each bit.

The last register type (interrupt register) is set to 1 by the module including the register, and a bit in the register which can be reset to zero by externally writing “1” to the set bit is set. Included. This type of register is used to handle interrupt / error signals from each module.

Each module of the coprocessor 224 sets the c_active line on the CBus 231 when the module is busy executing an instruction. For this reason, the instruction control unit 235 can take the “OR” of the c_active line from each module on the CBus 231 and know the time when the instruction is completed. The local memory control module 236 and the peripheral interface control module 237 can execute an overlap instruction, and c_ba is activated when the overlap instruction is executed.
CKround line is provided. The overlap command is a “local DMA” command that transfers data between the local memory interface and the peripheral interface.

The execution cycle of the overlap local DMA instruction is different from the execution cycles of other instructions. Before the execution of the overlap instruction, the instruction control unit 235 checks whether the overlap instruction has already been executed. If an overlap instruction already exists, or if the overlap instruction is in inactive mode,
The instruction control unit 235 waits for the end of the instruction, and then shifts to execution of the instruction. If there is no overlap instruction and the operation mode is set, the instruction control unit 235 immediately decodes the overlap instruction, configures the peripheral interface control unit 237 and the local memory control unit 236, and executes the instruction. After configuring the registers, the instruction control unit 235 updates the registers (end registers, status registers, instruction pointers, etc.) without waiting for the instruction to end in the conventional sense. At this time, if the end sequence number is the same as the interrupt sequence number, the signal is simply prepared instead of outputting the “end of overlap instruction” interrupt signal. The "overlap instruction end" interrupt signal is output when the overlap instruction is completely completed.

When an instruction is decoded, the instruction control unit prefetches the next instruction while executing the current instruction. For most instructions, the time it takes to execute the instruction is significantly longer than the time it takes to fetch and decode the instruction. Command control unit 235
Prefetches instructions when the following conditions are met: 1. 1. The currently executing instruction is not interrupted or paused. 2. The currently executing instruction is not a jump instruction. 3. The next instruction stream can be prefetched. If there is another pending instruction, the instruction control unit 235 determines that prefetching is possible, issues a request for the next instruction, and places it in the prefetch buffer.
Enable the buffer. When the processing is performed so far, the instruction control unit 235 does nothing until the currently executed instruction ends, and only checks the c_active and c_background lines on the CBus 231 for the end of the instruction. 3.8 Updating Register of Instruction Control Unit When the instruction ends, the instruction control unit 235 updates the register to reflect a new state. This process must be performed at high speed to avoid synchronization problems with external access. This high-speed update process is performed in the following procedure. 1. Obtain the appropriate register access semaphore. If the semaphore is occupied by an agent outside the instruction control unit 235, the instruction execution cycle waits until the semaphore is released, and the processing proceeds after the semaphore is released. 2. Update appropriate registers. If the instruction is not a proper jump instruction, the instruction pointers (ic_ipa and ic_ipa)
ipb) is increased by the size of the instruction. In the case of a jump instruction, the value of the jump destination is loaded into the instruction pointer. Therefore, if the sequence number is the operation mode, the end registers (ic_fna and ic_fnb) increase.

The status register (ic_stat) is also appropriately updated to reflect the new status. If necessary, a pause bit may be set. When an interrupt occurs and the pause for the interrupt is activated or an error occurs, the instruction control unit 235 pauses. Pause is activated by setting the instruction stream pause bits (a_pause and b_pause) in the status register. When resuming instruction execution,
These bits must be reset to zero. 3.1 clock cycle time, c_ on CBus 231
An end signal is sent to notify the other modules in the coprocessor 224 that the instruction has been completed. 4. Send an interrupt if necessary. An interrupt is sent in the following situations. a. When the "sequence number end" interrupt occurs. That is, the end registers (ic_fna and ic_f
nb) When the sequence number matches the interrupt sequence number. At this time, an interrupt is prepared, the sequence number is set to the operation mode, and an interrupt occurs. Or b. When the completed instruction is coded to interrupt at the end. In this case, the interrupt mechanism is activated. 3.9 Semantics of Register Access Semaphore The register access semaphore is a mechanism that provides high-speed access to a plurality of instruction control registers. The registers that require high-speed access include the following. 1. Instruction pointer registers (ic_ipa and ic_ip
b) 2. 2. ToDo registers (ic_tda and ic_tdb) 3. End registers (ic_fna and ic_fnb) Interrupt registers (ic_inta and ic_i
ntb) 5. Pause bit in configuration register (ic_cfg) The external agent can safely read all registers at any time. Also, the external agent can write to all registers at any time, but the external agent must first obtain a register access semaphore so that the instruction controller 235 does not update the values in these registers. . The instruction control unit cannot update the value in the above-mentioned register while the register access semaphore is declared externally. Further, the instruction control unit 235 updates all the registers during one clock cycle in order to maintain high speed.

As described above, when the sequence mechanism is in the operation mode, a 32-bit "sequence number" is assigned to each instruction. The instruction sequence number increases sequentially, from 0xFFFFFFFF to 0x00000.
Wrapped to 000. Write from outside is interrupt register (ic_inta and ic_intb)
, The instruction control unit 235 immediately performs the following comparison and update. 1. If the interrupt sequence number (the value in the interrupt register) is larger than the end sequence number (the value in the end register) of the same stream (modulo operation), the instruction control unit sets the "sequence number end" preparation bit in the status register. (A_prime in ic_stat
By setting the d and b_primed bits), a "sequence number end" interrupt mechanism is prepared. 2. The interrupt sequence number is “smaller” than the end sequence number, an overlap instruction is being executed in the stream, and the interrupt sequence number is the last overlap instruction sequence number (ic_loa).
Or the value in the ic_lob register), the instruction control unit a
Set the _primed or b_ol_primed bit to set up the “End Overlap Instruction Sequence Number” interrupt mechanism. 3. If the interrupt sequence number is "smaller" than the end sequence number, an overlap instruction is being executed in the stream, and the interrupt sequence number is not the same as the last overlap instruction sequence number, the interrupt sequence number indicates the end instruction. That is, no interrupt mechanism is prepared. 4. If the interrupt sequence number is "smaller" than the end sequence number and no overlap instruction is being executed in the stream, the interrupt sequence number will indicate the end instruction, and no interrupt mechanism is prepared.

The external agent sends an interrupt preparation bit (a_primed, a_ol) in the status register.
_Primed, b_primed, b_ol_pri
(med bit) can be set, and the interrupt mechanism can be independently activated and released. 3.10 Command Control Unit FIG. 13 is a diagram showing the command control unit 235 in more detail. The instruction control unit 235 includes an execution control unit 305 that processes an instruction execution cycle and manages overall execution control of the coprocessor 224. The execution control unit 305 includes the instruction control unit 23
5 to manage the overall execution control, determine an instruction sequence, fetch and prefetch instructions, decode instructions, and update the instruction control register. The instruction control unit further includes an instruction decoder 306. The instruction decoder 306 receives the instruction from the prefetch buffer 307 and decodes the instruction as described above. The instruction decoder 306 also performs a process of configuring a register in another coprocessor module to execute an instruction. The prefetch buffer control unit 307 manages reading and writing from the prefetch buffer in the prefetch buffer control unit, and controls the instruction decoder 306.
And the input interface switch 252 (FIG. 2). The prefetch buffer control unit 307 has two instruction pointer registers (ic
_Ipa and ic_ipb) are also managed. CBus 23 from the instruction control unit 235, various modules 239 (FIG. 2), and the external interface control unit 238 (FIG. 2).
1 (FIG. 2) is performed by a “CBus” arbitration unit 308 that arbitrates between access requests of three modules. The request is transferred by the CBus 231 to the registers of various modules.

FIG. 14 is a diagram showing the execution control unit 305 of FIG. 13 in more detail. As described above, the execution control unit manages the processing of the instruction execution cycle 275 of FIG. 9, and particularly performs the following processing. 1. 1. Determine from which instruction stream to fetch the next instruction; 2. Start fetching the instruction; 3. Instruct the instruction decoder to decode the instruction stored in the prefetch buffer; 4. Determine and start prefetching the next instruction; 5. determine the end of the instruction; When the instruction is completed, update the register.

The execution control unit has a large core state machine 310 (hereinafter referred to as a central unit) that manages the entire instruction execution cycle. FIG. 15 is a diagram showing a state transition diagram of the central unit 310 for managing the above-mentioned instruction execution cycle. FIG.
In 4, the execution control unit includes the instruction prefetch logic unit 31.
1 is provided. This section performs processing for determining whether an instruction to be executed exists and to which instruction stream the instruction belongs. In the transition diagram of FIG. 15, the start 312 and prefetch 313 states use this information to obtain an instruction. The register management unit 317 of FIG. 14 monitors the register access semaphores of both instruction streams and performs a process of updating all necessary registers in each module. Also, the end registers (ic_fna and i
c_fnb) and an interrupt register (ic_inta)
And ic_intb), and the register management unit 317 also performs a process of determining whether or not to execute a “sequence number end” interrupt. Further, the register management unit 317 also performs an interrupt preparation process. The overlap instruction unit 318 manages the end processing of the overlap instruction through management of appropriate status bits in the ic_stat register. The execution control unit further includes the central unit 310 and FIG.
And a decoding interface unit 319 for interfacing with the third instruction decoder 306.

FIG. 16 is a diagram showing the instruction decoding unit 306 in more detail. The instruction decoder performs a process of configuring a coprocessor to execute an instruction in the prefetch buffer.
The instruction decoder 306 comprises an instruction decoding sequencer 321 consisting of a large state machine, which is a combination of many small state machines. The instruction sequencer 321 communicates with a CBus dispatcher 312 that sets registers in each module. Instruction decoding sequencer 3
21 informs the execution control unit of relevant information such as the validity of the instruction and the overlap state of the instruction. Here, the instruction validity check checks whether the instruction opcode is a reserved opcode.

FIG. 17 is a diagram showing the instruction dispatcher sequencer 321 of FIG. 16 in more detail. The instruction dispatcher sequencer 321 comprises an overall sequence control state machine 324 and a contiguous per-module sequencer state machine (eg, 325 or 326). A per-module configuration sequencer state machine is provided for each module to be configured. The state machine as a whole defines the coprocessor microprogramming of the module.
The state machine (eg, 325) instructs the CBus dispatcher to use the entire CBus to set various registers, and configures various modules for processing. To write to a particular register, execution of the instruction must begin. Generally, the execution of an instruction requires more time than the sequencer 321 configures the coprocessor register for processing. In Appendix A, the microprogramming process performed by the instruction sequencer of the coprocessor and the instruction sequencer 321 are described.
Indicates the format set up by.

Actually, the instruction decoding sequencer 321 does not configure all the modules in the coprocessor for each instruction. In the following table, the module configuration order for the instruction class is indicated by the pixel organizer 246 (P
O), data cache control unit 240 (DCC), operand organizer B247 (OOB), operand organizer C248 (OOC), main data path 242
(MDP), Result Organizer 249 (RO), JPE
It is shown together with a module such as a G encoder 241 (JC). The external interface control unit 238 (EIC) and the local memory control unit 236 (L
MC), the instruction control unit 235 itself (IC), the input interface switch 252 (IIS), the miscellaneous module (M
Modules such as M) are not configured during the instruction decoding process.

Module startup order

[0102]

[Table 5]

In FIG. 17, each module configuration sequencer (for example, 325) performs necessary register access processing and manages to configure a specific module. The overall sequence control state machine 324 manages the overall operation of the module sequencer in the order described above. FIG. 18 is a state transition diagram 330 illustrating the overall sequence control for activating the related module configuration sequencer according to the above table. Each module configuration sequencer controls the CBus dispatcher and performs a process of changing register contents in order to set various registers during execution of the module.

FIG. 19 is a diagram showing the prefetch buffer control unit 307 of FIG. 13 in more detail. The prefetch buffer controller controls a single coprocessor instruction (6 × 32
A pre-fetch buffer 335 for storing a bit word). And the prefetch buffer is IB
us sequencer 336, one write port, an instruction decoder, an execution control unit, and an instruction control unit CB.
One read port for sending data to the us interface. The IBus sequencer 336 monitors the bus protocol at the connection of the prefetch buffer 335 to the input interface switch. Further, an address management unit 337 for generating an address for fetching an instruction is provided. The address management unit 337
function of selecting one of ipa or ic_ipb and connecting to the bus to the input interface switch, and i based on which stream the last instruction was fetched from.
It has a function of increasing one of c_ipa or ic_ipb, and a function of storing a jump destination address in the ic_ipa and ic_ipb registers. The PBC control unit 339 controls the entire prefetch buffer control unit 307. 3.11 Description of Module Local Register File As shown in FIG. 13, each module including the instruction control module itself has an internal set of the register 304 described above together with the CBus interface control unit 303 shown in FIG. A request is received and a process of updating an internal register according to the request is performed.
Control of the module is performed by writing to a register 304 in the module via the CBus interface 302. The CBus adjustment unit 308 (FIG. 13)
Which of the instruction control unit 235, the external interface control unit, and the miscellaneous module controls the CBus,
It operates as the master of s, and determines whether to write / read the register.

FIG. 20 is a diagram showing a standard configuration of the CBus interface 303 used in each module. The standard CBus interface 303 is CBus
It has a register file 304 that receives read requests and write requests from 302 and is updated via 341 by various sub-modules within the module. In addition, a control line 344 is provided for updating the memory area of the sub-module, including reading the memory area. The standard CBus interface 303 is CBus
And accepts a read request or a write request for the memory object of the register 304 or another submodule.

The "c_reset" signal 345 is a standard CB
Set all registers in the us interface 103 to the default state. However, "c_reset"
Does not reset the state machine that controls the exchange of signals between itself and the CBus master. Therefore, "c_
reset is sent during CBus processing,
The process will end in some way. "C_
int "347," c_exp "348," c_er "
r "349 signal is calculated using the following equation:
It is generated from the contents of the r_int and err_int_en registers.

[0107]

(Equation 1)

[0108]

(Equation 2)

[0109]

(Equation 3)

The signals "c_sdata_in" and "c_s
"valid_in" 345 is a data / valid signal from the previous module in the module row, and the signal "c
_Sdata_out ”and“ c_svalid_ou ”
“t” 350 is a data / valid signal to the next module in the module train. The functions of the standard CBus interface 303 include the following. 1. 1. Register read / write management 2. Read / write management of memory area 3. Read / write management in test mode Submodule monitoring / update management 3.12 Register read / write management The standard CBus interface 303 receives register read / write requests and bit set requests flowing on the CBus. The following two types of CBus commands are managed by the standard CBus interface. 1. Type A Type A operates to read / write 1, 2, 3, 4 bytes from / to a register in the standard CBus interface 303 by another module. In a write operation, a data cycle occurs in a clock cycle immediately after an instruction cycle. The type fields for register write / read are “1000” and “1001”, respectively. The standard CBus interface 303 decodes the instruction and checks whether the instruction is pointing to a module address or a read / write operation. In the read operation, the standard CBus interface 303
Selects which register output to connect the "c_sdata" bus 350 to using the "reg" field of the CBus process. For a write operation, the standard CBus interface 303 uses a “reg” field and a “byte”
Write data to the register selected using the "e" field. When the read operation is completed, the standard CBus interface returns the data and simultaneously reads “c_svali”.
d "350 is transmitted. When the write operation is completed, the standard CBus interface 303 displays “c_svali”.
d "350 and respond. 2. Type C Type C is an operation in which another module writes one or more bits to one of the bytes in one register. Instructions and data are combined into one word.

The standard CBus interface 303 checks the instruction to see if it points to a module address. "Reg", "byte", "en"
Decode the "able" field to generate the required enable signal. It also fetches the data field of the instruction and transfers the fetched data to all four bytes of the word. As a result, the necessary bits are written to the enable bits in all the enable bytes. No response is required in this operation. 3.13 Memory Area Read / Write Management The standard CBus interface 303 receives a memory read / write request on the CBus. Upon accepting a memory read / write request, the standard CBus interface 303 checks whether the request points to a module address. Then, by decoding the address field of the instruction, the standard CBus interface generates an appropriate address and an address strobe signal 344 to the sub-module that performs the memory read / write. For a write operation, the standard CBus interface transfers the byte enable signal from the instruction to the sub-module.

The operation of the standard CBus interface 303 decodes the type field of the CBus instruction on the CBus 302 so that in the next cycle the data is taken into the register file 304 or transferred to another sub-module 344. For this purpose, the read / write control unit 35 generates an appropriate enable signal to the register file 304 and the output selector 353.
2 is controlled. If the CBus instruction is a register read operation, the read / write control unit 352 enables the output selector 353 and “c_sdata
Select the correct register output to "bus" 345. If the instruction is a register write operation, read / write controller 352 enables register file 304 and then selects data in a cycle. If the instruction is a read / write of a memory area, the read / write control unit 352 generates an appropriate signal 344 to control the memory area managed by the module. The register file 304 includes a register selection decoding unit 355, an output selector 353, an interrupt 356, an error 357, and an exception 3.
58, an unmask error generator 359, and a register 360 that constitutes a register of a certain module. The register selection decoding unit 355 outputs the signal “ref_e” from the read / write control unit 352.
n "(register file enable)" write "
Decode "reg" and generate a register enable signal to enable a certain register. The output selector 353 selects correct register data for register read processing according to the signal “reg” output from the read / write control unit 352, and selects c_sdate_o.
Output to ut line.

When an error is detected during the input, the exception generators 356 to 359 output an output error signal (for example, 347 to 347).
49, 362). The method of calculating each output error is as described above. The register section 360 can be of various types as required, as discussed when describing the configuration of the register set in Table 5. 3.14 CBus Configuration As described above, the CBus (control bus) controls each module as a whole by transferring information for setting a register in the standard CBus interface of each module. As is apparent from the description of the standard CBus interface, CBus has the following two purposes. 1. 1. Control bus for driving each module RAM, FIFO, access bus for status information in each module The CBus controls the modules by setting configuration registers in the modules using an instruction-address-data protocol. Generally, registers are set for each instruction, but modifications can be made at any time. The CBus collects status and other information and requests data from various modules to RAM or F
Access IFO data.

The CBus is driven for each process by one of the following three methods. 1. 1. Instruction control unit 235 (FIG. 2) during instruction execution 2. External interface control unit 238 (FIG. 2) when executing target (slave) mode bus operation When the external CBus interface is configured, in any case of the external device, the drive module becomes a CBus source module and all other modules become possible destination modules. The bus control process is performed by the instruction control unit.

The following table shows one definition of a CBus signal that is suitable for use in the preferred embodiment. CBus signal definition

[0116]

[Table 6]

The cBus c_iad signal contains address data and is driven by the controller in two different cycles. 1. 1. Instruction cycle in which a CBus instruction or address is driven on c_iad (c_valid high) Data cycle (c_valid low) in which data is driven on c_iad (write operation) or c_sdata (read operation) In the case of a write operation, data relating to an instruction is placed on the c_iad bus immediately after the instruction cycle. In the case of a read operation, the target module of the read operation drives the c_sdata signal until the data cycle ends.

In FIG. 21, the bus includes a 32-bit instruction-address-data field. This field has the following three types (370 to 372). 1. The type A operation (370) is used to read / write a register in the coprocessor and a data area of each module. These operations are generated by the external interface control unit 238 executing the target mode PCI cycle, the instruction control unit 231 configuring the coprocessor for instructions, and the external CBus interface.

In these operations, the clock cycle immediately after the instruction cycle is the data cycle. 2. Type B operation (371) is used in diagnostic mode,
Access local memory or generate cycles on general interface. These operations are generated by an external interface control unit or an external CBus interface executing a target mode PCI cycle. The data cycle can be at any time after the instruction cycle, and the data cycle is returned from the destination module using the c_svalid signal. 3. Type C operation (372) is used to set each bit in the module's register. These operations are generated by the instruction control unit 231 and an external CBus interface that constitute a coprocessor for instructions. There is no data cycle in Type C operation, and data is included in the instruction cycle.

The type field of each instruction encodes the associated CBus operation according to the following table. CBus processing type

[0121]

[Table 7]

The byte field is used to set a bit in a register. The module field is a field for designating the address destination module of the instruction on the CBus. The register field is a field for specifying which register in the module is to be updated. The address field specifies an address of a RAM, a FIFO, or the like, which is a field for specifying a memory portion where an operation is performed. The enable field is
A field that enables selected bits in a selected byte when a set bit instruction is used. The data field contains the bit data written to the byte to be updated.

As described above, the CBus is transmitted for each module when the module is executing an instruction.
active line. The command control unit can know the end time of the command based on this signal. Also, CBus
Includes a c_background line that operates in the background mode for each module, along with reset, error, and interrupt lines for performing reset, error detection, and interrupt. 3.15 Coprocessor Data Type and Data Manipulation In FIG. 2, the operation of the coprocessor unit 224, particularly JP
To simplify the main computational operations in the EG encoder 241 and the main datapath coprocessor, the coprocessor uses a data model that differentiates between the external and internal formats. The external data format is a data format that appears on an external interface of the coprocessor such as a local memory interface or a PCI bus. Conversely, the internal data format is the format that appears between the main function modules of coprocessor 224. FIG. 22 is a diagram schematically showing various input / output formats. Input external format 381
Is an input format to the pixel organizer 246, the operand organizer B247, and the operand organizer C248. These organizers convert the input external format into the input internal format 38 input to the JPEG encoder 241 and the main data path unit 242.
Reformat to 2. In addition, these two functional units output the output data in an output internal format, and the result organizer 249 converts the output internal format into a desired output format 304.

In the embodiment, the external data format is 3
Divided into two types. The first type has up to four channels per data, where each channel is 1,2,
A "packed stream" of data consisting of a continuous stream, such as consisting of 4, 8, or 16 bit samples. The pack stream is used to represent a pixel, data to be converted into a pixel, a group of bits, and the like. The coprocessor also uses little endian byte addressing and big endian bit addressing in bytes. FIG. 23 shows a first example of the pack stream format. Here, each object 387 includes three channels of channel 0, channel 1, and channel 2 of 2 bits for each channel. The data arrangement of this format is 388. In the next example 390 of FIG.
4-channel object 39 with each data object having 32 bit words and 8 bits per channel
5 is shown. In the third example 395 of FIG. 25, a channel object 396 having 8 bits for each channel starting from the bit address 397 is shown. Of course, depending on the application, the actual width and number of data channels will vary.

The second type of external data format is an "unpacked byte stream", a sequence of 32-bit words in which only one byte of each word is valid. An example of this format is 39 in FIG.
9, a single byte 400 in each word
Only used. Additional external data formats are represented by objects that are classified as "other" formats. Generally, these data objects are large tabular data such as a color space conversion table and a Huffman coding table.

The coprocessor uses four internal data types. The first type is a "packed byte" format, which is a format consisting of four active byte 32-bit words except for the last 32-bit word. FIG. 27 shows an example 402 of a packed byte format in which a word is 4 bytes. The next data type shown in FIG. 28 is the "pixel" format, which is a format consisting of 32-bit words 403 in a 4 active byte channel. This pixel format is interpreted as four channel data.

The next internal data type shown in FIG. 29 is in "unpacked byte" format, where each word is in a format consisting of one active byte channel 405 and three inactive byte channels. At this time, the active byte channel occupies the minimum byte.
Other internal data objects are classified as "other" data formats. External format input data is converted to the appropriate internal format. FIG. 30 shows an external format 4 executed by various organizers.
10 shows a form of conversion from 10 to an input format 411. FIG. 31 shows an internal format 412 to an external format 4 executed by the result organizer 249.
13 is shown.

Hereinafter, the processing for executing the conversion will be described in more detail. First, the conversion of the input data from the external format to the internal format is shown in FIG. 32. FIG. 32 shows a method used by various organizers in the conversion process. Initially, the external other format 416, which simply passes without going through various organizers. Next, the external unpacked byte format 417 performs unpack normalization 418 to generate a format 419 called an internal unpacked byte. Unpack Normalization 41
The process 8 removes three inactive bytes from the external unpacked byte stream. FIG. 33 shows the unpack normalization process, but only one byte channel among the inputs having a 4-byte channel has a valid result in the output format 419,
This shows a state where a simple byte is output.

In FIG. 32, a pack normalization 421 process is a process of converting an element object in the external pack stream 422 into a byte stream 423. If the size of each element of the channel is less than or equal to bytes, the samples are interpolated to 8-bit values. For example, when converting a 4-bit unit into a byte unit, a 4-bit value 0xN is converted into a byte value 0xNN. If the object is longer than 1 byte, truncation is performed. The input object sizes supported by stream 422 are 1, 2,
4, 8, and 16 bit sizes. Note that these depend on the total width of data objects and words in the system to which the present invention is applied.

FIG. 34 shows three bits having two bits per channel (as per the data format 386 in FIG. 23).
The state of pack normalization 421 when input data 422 in the channel object format is input is shown. The output data is in the byte channel format 423. At this time, if necessary, "interpolation processing"
To generate an 8-bit sample.

In FIG. 32, the pixel stream is then sent to one of a pack process 425, an unpack process 426, and an element selection process 427. FIG. 35 shows an example of the packing process 425, in which the inactive byte channel is simply removed and a byte stream packed into 4 active bytes per word is generated. That is, a single valid byte stream 43
Zeros are compressed into format 431 with four active bytes per word. The unpack operation 426 is almost the opposite operation of the pack operation, and the unpack byte is the minimum byte of the word. FIG. 36 shows how the packed byte stream 433 is unpacked and the result 434 is obtained.

FIG. 37 shows the element selection 427 processing, where N is the number of input channels per unit, and is the processing for selecting N elements from the input stream. The unpacking process is used when generating “prototype pixels”, for example, 437. Note that the pixel channel is filled from the minimum byte. FIG. 38 shows how the input data of the format 436 is converted by the element selection unit 427 and the prototype pixel format 437 is generated.

When an element is selected, an element replacement process 44 is performed.
0 (FIG. 32). FIG. 38 shows a state of the element replacement processing. The selection elements are replaced with a fixed value stored in the internal data register 441, and the output element 2 is output as shown in the example.
42 is generated. In FIG. 32, the outputs of processing stages 425, 526, 440 are sent to lane swap processing 444. As shown in FIG. 39, the lane swap process is a process of multiplexing a certain lane with another lane on a byte basis, and also includes a process of duplicating a certain lane with another lane. In the example of FIG. 38, a state is shown in which channel 3 and channel 1 are exchanged, and channel 3 is copied to channel 2 and channel 1.

In FIG. 32, lane swap processing 44
4 is completed, the data stream is reread and before the copy process 446 is performed, the multicast value RAM 25 is read.
It may be stored in 0. The copy process 446 is a process of simply copying a data object. FIG. 40 shows a state where the duplication process 446 is applied to the pixel data, and the duplication factor is one.

FIG. 41 shows a state where the duplication processing is applied to pack byte data. FIG. 42 shows the processing of the result organizer 249 for converting data from the output internal format 383 to the output external format 384. This processing includes the same processing 424, 425, 426, and 440 as the conversion processing shown in FIG.
In the case of 0, processing of element non-selection 451, denormalization 452, byte addressing 453, and write masking 454 is further included. Element non-selection processing 451 shown in FIG.
Is a reverse process of the element selection process of FIG. 37, and unnecessary data is deleted. For example, in FIG. 43, only the three valid channels being input are retrieved and packed into data item 456.

The denormalization processing shown in FIG. 44 operates almost in the opposite manner to the pack normalization processing 421 shown in FIG. In the denormalization process, a process of converting each object or data item handled in a byte unit into a non-byte value is performed. Byte addressing processing 45 in FIG.
No. 3 performs a reconstruction process for each byte necessary for byte addressing. In an external unpacked byte output stream, at least two bits of the stream address correspond to the active stream. In the byte addressing process 453, when an external unpacked byte is used (FIG. 4)
5) The output stream is remapped from one byte channel to another channel byte. When an external packed stream is used (FIG. 46), the byte addressing module 453 remaps the starting address of the output stream as shown.

The write mask processing 454 of FIG.
FIG. This is a process of masking a certain channel (eg, 460) of a pack stream that is not written. The input / output data type conversion to be applied is determined based on the contents of the following data operation registers. * Pixel organizer data operation register (po_d
mr) * Operand organizer B and operand organizer C data operation registers (oor_dmr, ooc_dm
r) * Result organizer data operation register (ro_dm
r) The setting of each data operation register for an instruction is as follows.
Done in one of two ways. 1. 1. Set using standard techniques to write to coprocessor registers just before instruction execution In the instruction decoding process, which is set by the coprocessor itself based on the current instruction, the coprocessor examines the contents of the data instruction word and data word and determines how to set various data operation registers. Perform with other processing. Note that not all combinations of instructions and operands are valid. Some instructions specify an operand format. Instructions with incorrect operands will produce an "undefined" result, but may also exit without error. If the "S" bit of the corresponding data descriptor is 0, the coprocessor sets the data manipulation register to reflect the current instruction.

FIG. 48 shows the format of the data operation register. The following table shows the various bit formats in the registers shown in FIG. Data operation register format

[0139]

[Table 8A]

[0140]

[Table 8B]

A single instruction may use a plurality of internal / external data types. All combinations of operands, results, and instruction types are valid,
Only some of these combinations produce meaningful results. Table 9 shows specific combinations of operands and result data types expected for each instruction. Table 9 shows
It summarizes the expected data types in the external / internal format.

Expected data type

[0143]

[Table 9]

Note that the symbols used in Table 9 are as follows. Explanation of the symbol

[0145]

[Table 10]

3.16 Data Normalization Circuit FIG. 49 shows a computer graphics processor including three main function blocks. The three main functional blocks are the data normalizer 1 in the pixel organizer 246 and the operand organizers B, C247, 248.
062, main data path 242 or JPEG section 241
And a programming agent 1064 in the instruction control unit 235. The operation of the data normalizer 1062 and the central graphics engine is determined by the instruction stream 1064 to the programming agent 1064. For each instruction, the programming agent 1064 performs a decryption process,
Outputs internal control signals 1067 and 1068 to other blocks in the system. For each input data word 1069, normalizer 1062 formats the data based on the current instruction and sends the processing result to central graphics engine 1063 where further processing is performed.

The data normalizing unit simply means a pixel organizer and operand organizers B and C.
These organizers include a data normalization circuit which, after appropriately normalizing the input data, sends the result to the central graphics engine in a JPEG encoded or main data path. The central graphics engine 1063 has 3
Operates on standard format data that is a 2-bit pixel. Therefore, the normalizing unit performs a process of converting the input data into a 32-bit pixel format. The input data word 1069 to the normalizer also has a 32-bit width, but may be in either packed element or unpacked byte format. The packed element input stream has data objects of 1, 2, 4, 8, 16
Consists of contiguous objects in a data word that is byte wide. An unpacked byte input stream, on the other hand, has 32 bits, where only 8-bit bytes are valid.
Consists of a word of bits. Further, the pixel data 11 generated by the normalization unit includes 1, 2, 3, and 4 effective channels whose channels are defined by an 8-bit width.

FIG. 50 is a diagram showing a specific hardware configuration of the data normalization unit 1062. The data normalization unit 1062 includes a FIFO buffer (FIFO) 107
3, 32-bit input register (REG1), 32-bit output register (REG2), normalizing multiplexer 10
75, and a control unit 1076. Input data word 10
69 is stored in the FIFO 1073, and then (REG1)
At 1074, all input bits are latched until converted to the desired output format. The normalization multiplexer 1075 calculates the value in (REG1) 1074 and (FIF
O) There is a 32 combination switch that selects a bit from the current output of 1073 to generate a pixel that is latched into REG2. That is, the normalization multiplexer 1075 outputs x [63. . 32] and x [31. .
0] and two 32-bit input words 107
7, 1078 are input.

By using such a technique, the overall throughput of the device can be improved, especially when the FIFO has at least two valid data words in the instruction processing. This is due to the technique of fetching data words from memory. Although the desired data word or object may be spread or "wrapped" in adjacent input data words in the FIFO buffer, using the input register 1074,
The complete input data can be reconstructed using elements from adjacent data words in the FIFO buffer, eliminating the need for additional storage and bit strip processing required prior to the main data manipulation processing stage. Such a configuration is a great advantage when multiple data words of a similar type are input to the normalization unit.

The control unit controls REG1 1074 and REG2
Enable signal REG1_EN1 for updating 1076
080 or REG2_EN [3. . 0] 1081 and a signal for controlling the FIFO 1073 and the normalizing multiplexer 1075. The programming agent 1064 in FIG.
The following configuration signal is sent to the control unit 62. FIFO
_WR4 signal, normalization factor n [2. . 0], bit offset b [2. . 0], channel count c
[1. . 0], an external format (E). The input data is written to the FIFO 1073 by sending out the FIFO_WR signal 1085 every clock cycle in which valid data exists. When no area is available, the FIFO sends out a fifo_full status flag 1086. Given 32 bit input data, it is checked using an external format signal whether the input is in packed stream format (E = 1) or unpacked byte (E = 0). When E = 1, the normalization factor is the size of each element of the pack stream. That is, n = 0 is a 1-bit element, n
= 1 is a 2-bit width element, n = 2 is a 4-bit width element, n =
3 indicates an 8-bit width element, and n> 3 indicates a 16-bit width element. Also, the channel count is the maximum number of consecutive input objects that will be formatted every clock cycle to produce a pixel with the desired number of significant bytes.
Specifically, c = 1 is a pixel for which only the minimum byte is valid, c = 2 is a pixel for which at least 2 bytes are valid, c
= 3 is a pixel for which at least 3 bytes are valid, and c = 0 is a pixel for which all 4 bytes are valid.

If the pack stream is composed of elements having a width of 8 bits or less, the bit offset is x [31. . 0] is determined. If the bit offset is a deviation from the largest bit of the first input byte, the output data byte y [7. . 0] is given by the following equation. When n = 0, y [i] = x [7-b] When 0 ≦ i ≦ 7 When n = 1, y [i] = x [7-b] i = 1, 3, 5, 7 When y [i] = x [6-b] When i = 0,2,4,6 When n = 2, y [3] = x [7-b] y [2] = x [6- b] y [1] = x [5-b] y [0] = x [4-b] y [7] = y [3] y [6] = y [2] y [5] = y [1 Y [4] = y [0] When n = 3, y [i] = x [i] When 0 ≦ i ≦ 7 When n> 3, y [7. . . 0] = x [15. . . 8] Output data byte y [15. . 8], y [23. . 1
6], y [31. . 24] is the same.

In the above method, an output array of any length can be generated by inputting elements of an input stream and performing a necessary number of duplication processes to generate an output object having a standard width. Can be extended as follows. The processing order of the input elements may be little endian or big endian. In the above example, since the processing always starts from the maximum bit of the input byte, the big endian element order is used. If little endian order is used, the bit offset must be redefined as the value for the least significant bit of the input byte. Also, if the input element width is greater than or equal to the standard output width, the output element is generated by truncating the input element, typically removing an appropriate number of the least significant bits. In the above formula, 16
By selecting the largest byte of the bit data object, the 16-bit input element is truncated to produce an 8-bit wide standard output.

The control unit shown in FIG. . 0] and c
[1. . 0], and these and b [2. . 0] and the selection signal for the normalization multiplexer or RE
Generate enable signals for G1 and REG2. In addition, since the FIFO may be empty during the instruction, the control unit determines the current bit position in_bit [4. . 0] and the current byte position out_byte at which to start writing output data
[4. . 0] is stored. The control unit is
When the processing is completed, in_bit [4. . 0] and the position of the last object of REG1 to detect the input word, and start the FIFO read operation by sending the FIFO_RD signal in one clock cycle when the FIFO is not empty. Signal fifo_em
pty and fifo_full are FIFO status flags, which are used when the FIFO has no valid data.
fo_empty = 1, fif when FIFO is full
o_full = 1. In the clock cycle in which FIFO_RD is transmitted, REG1_EN is transmitted, and new data is taken into REG1. REG2
There are four enable signals corresponding to each byte of the output register. The control unit determines the decrypted c
[1. . 0], the number of active elements in REG1 waiting for processing,
By taking the minimum value among the three values of the number of unused channels in REG2, REG2_EN [3. . 0]. If E = 0, there is only one valid element in REG1. The number of channels occupying REG2 is decoded c [3. . 0], a complete output word is obtained.

In the preferred embodiment of the present invention, the function occupied by the apparatus of FIG. 50 is added by adding a function of limiting the bit offset parameter, such as using only a part of the offset used in the control unit and the normalizing multiplexer. The area can be significantly reduced. This offset limit function depends on the normalization factor,
It operates according to the following equation.

B_trunc [2. . . 0] = 0 When n ≧ 3 = b [2. . . 0] When n = 0 = b [2. . . 1] In the case of n = 1 = b [2] & “00” In the case of n = 2 (“&” indicates a combining process for each bit) By such a process, MUX0 and MU in FIG.
X1. . . The size of each normalization multiplexer indicated by MUX31 is 32-1 when the limiting function is not used.
Maximum size when bit offset restriction is performed from 2
0-1. This size reduction can also improve the circuit speed.

As described above, the preferred embodiment comprises an efficient circuit for converting data into several normalized forms. 3.17 Image Processing Operation of Accelerator Card In FIG. 2 and Table 2, the instruction control unit 235 “executes” an instruction resulting in an operation executed in the coprocessor 224. The executed instructions include various instructions that cause useful functions to be performed in main data path unit 242. One of these useful instructions is the composition process.

3.17.1 Synthesis FIG. 51 is a diagram showing a synthesis model implemented in the main data path unit 242. The composite model 462 generally has three data input sources and output data (sink) 46.
3 inclusive. One input source is output 463 and pixel data 464 from the same destination in memory. It also includes an instruction operand 465 used as a data source such as color and opacity. Here, the color and opacity may be any of flat, blend, pixel, and tile. It should be noted that the flat and the blend are generated by the blend generation unit 467 because the speed of the internal generation is faster than that of the fetch via the input / output.
Further, the input data also includes attenuation data 466 that attenuates the operand data 465.

As mentioned above, pixel data usually consists of four channels, each channel being one byte wide. Here, one byte of the highest address is an opaque channel. The operation and usefulness of the synthesis process are described in the commentary “Thomas Porter and Tom D.
uff "Compositing Digital I
images "in Computer Graphic
s, volume 18, number 3, July
1984 ".

The coprocessor can also use premultiplied data. Pre-multiplication is the process of multiplying each color channel and the opaque channel in advance. Therefore, two optional pre-multipliers 468, 469 can be provided to pre-multiply the opaque channels 470, 471 and the color data, if necessary, to obtain pre-multiplied outputs 472, 473. The combining unit 475 combines the two inputs based on the current instruction data. Table 11 below shows the composition operators.

Synthetic operation

[0161]

[Table 11]

Here, (aco, ao) represents a pre-multiplied pixel of the color ac and the opacity ao. R is an offset value, and “wc” is a wrapping / clamping operator described below. It should be noted that the synthesizing unit 475 includes the reverse operation of each operator in the above table. The clamp / lapping unit 476 has a limit value of 0 to 25.
5 is a processing unit for clamping or wrapping data. If desired, the data can also be subjected to optional "ample multiplication" 477 processing to restore the original pixel values. Finally, the output data 46
3 is generated and returned to memory.

FIG. 52 shows an instruction format sent to the main data path unit when performing the synthesizing process. If the X field in the main opcode is 1, the addition operator is applied according to the above table. If this field is 0,
Other instructions other than the addition operator apply. The Pa field is a field indicating whether to premultiply the first data stream 464 (FIG. 51). Also,
The Pb field indicates whether to pre-multiply the second data stream 465 and the Pr field is the part 477
Is used to indicate whether the result is to be "ample-multiplied."
The C field indicates whether to wrap or clamp, overflow or underflow within the range 0-255, and the "com-code" field indicates which operator to apply. The addition operator can also use the offset register (mdp_por).
This offset is subtracted from the result of the addition operation before the wrapping / clamping process is performed. In the addition operator, the com-code field is a field indicating whether to enable each channel of the offset register.

The previously described standard instruction word encoding 280 of FIG. 10 is modified for composite operands. Since the destination of the output data is the same as the original source, operand A is always the same as the result word. for that reason,
Operand A can describe operand B together with operand B longer. As with the other instructions, the A descriptor in the instruction describes the input format, and the R descriptor specifies the output format.

FIG. 53 shows the instruction word format of the blend instruction as a first example 470. The blending process is defined by a start value 471 and an end value 472 for each channel. Similarly, FIG.
6, a starting offset 477, and a tile instruction format defined by a length 478. All tile addresses and sizes are specified on a byte-by-byte basis. Tile processing is performed in a modular manner, and FIG. 55 is a view for explaining fields 476 to 478 in FIG. The tile address 476 specifies the start address of the tile memory, the tile start offset 477 specifies the first byte used at the start of the tile, and the tile length 478 specifies the total tile length to be wrapped.

In FIG. 51, color elements and opacity may be attenuated by the attenuation value 466. The attenuation value is obtained by the following three methods. 1. By including an attenuation factor in the instruction's operand C word, software can specify flat attenuation. The bitmap attenuation with 2.1 on and 0 off is:
It can be used with software that specifies the address of a bitmap in the operand C word of the instruction. 3. Byte map attenuation may be provided at the byte map address of the operand C word of the instruction. 4. ON when the value is 1, using the software
Bitmap attenuation can be performed, which is turned off when.

Since the attenuation value is an unsigned integer from 0 to 255, the pre-multiplied color channel is multiplied by the attenuation factor by calculating Coa = Coa × A / 255. Where A is the attenuation factor and Co is the pre-multiplied color channel.

3.17.2 Color Space Conversion Instruction In FIG. 2 and Table 2, the main data path unit 242 and the data cache 230 mainly perform color conversion processing. The color space conversion performs a conversion process from a first color space format (for example, a format suitable for RGB color display) to a second color space format (for example, a format suitable for CYM or CYMK printing). The color space conversion process is designed to support all color spaces, and the instruction control unit 235 that can be used in any function from one-dimensional to multi-dimensional uses a main bus 242, a data Cache controller 240, input interface switch 252, pixel organizer 246, MUV buffer 250, operand organizer B247, operand organizer C2
48, configure the result organizer 249, and control it to operate in the color conversion mode. In this mode, an input image composed of a plurality of lines of pixels is sent to the main data path unit 242 as a pixel stream for each pixel line. The main data path unit 242 (FIG. 2) switches the input interface switch 252 to the pixel organizer 24.
6 and performs a color space conversion process for each pixel. Further, the interval table and the fraction table are loaded in the MUV buffer 250 in advance, and the color conversion table is loaded in the data cache 230. Main data path 242 accesses these tables via operand organizers B and C, for example, converts pixels from RGB color space to CYM or CYMK color space, and sends the converted pixels to result organizer 249. Main data path unit 242, data cache 230,
The data control unit 240 and the other aforementioned devices are controlled by the command control unit 235 to control a single output general color space (SOG).
CS) conversion mode or multiple output general color space (MOG
CS) operates in one of the conversion modes. For details of the data cache control unit 240 and the data cache 230, refer to the item of “Data cache control unit and cache” 240, 230 (FIG. 2).

An accurate color space conversion process is a complicated nonlinear process. For example, the color space conversion process from RGB pixels to a single primary color component (ie, cyan) in the CYMK color space is linear in theory, but is actually non-linear in an output device that outputs mainly color components of pixels. Nature will arise. The same applies to color space conversion processing from RGB pixels to other main color elements (yellow, magenta, black) in the CYMK color space. That is, nonlinear color space conversion is generally used to compensate for the nonlinearity that occurs in each color element. Due to such complicated nonlinearity of the color conversion processing, a complicated transfer function is incorporated or a look-up table is used. For example, given an input color space of 24-bit RGB pixels, these pixels are
A lookup table that maps to an 8-bit primary color element (cyan) in the YMK color space requires 16 megabytes or more. Similarly, a 24-bit RGB pixel is converted to CYM
The look-up table that maps to the four 8-bit primary color elements of the K color space is 64 megabytes or more, requiring a huge capacity. On the other hand, the main data path 242
(FIG. 2) uses a lookup table stored in the data cache 230 to associate a coarse output color value with a point in the input color space and interpolate the output color value to obtain an intermediate output. a. Single Output General Color Space (SOGCS) Conversion Mode In both single and multiple output color conversion modes (SOGCS) and (MOGCS), the RGB color space consists of 24-bit pixels with 8 bits of red, green, and blue components. Each of the RGB dimensions of the RGB color space is divided into 15 sections, and the length of each section is calculated from the printer's RGB to CY.
It is set to be an inverse function of the nonlinearity to the MK color space. That is, if the transfer function shows strong nonlinearity, the length of the section is shortened, and if the transfer function is nearly linear, the length of the section is lengthened. In order to know such a nonlinear portion of the transfer function, it is desirable to accurately check the color space of each output printer. However, it is also possible to approximate or model the transfer function based on know-how and measured characteristics of the printer type (eg, inkjet).
For each color channel of the input pixel, the position of the color element value in 15 sections is determined. Two tables are used in the main data path unit 242 to determine in which section the input color element value exists and to determine the position in the section where the input color element value exists. Of course, different tables may be used for output printers having different transfer functions.

As described above, each dimension of RGB is divided into 15 sections. That is, the RGB color space has a three-dimensional lattice structure divided into sections, and input pixels at both ends of the section are coarsely arranged in the input color space. Furthermore,
Only the output color values of the output color space corresponding to both ends of the section are stored in the lookup table. Therefore, the output color value of the input color pixel is determined by determining output color values corresponding to both ends of the section where the input pixel exists, and interpolating the output color value based on the position in the section. This approach can reduce the need to use large memories.

FIG. 56 shows an example 480 for determining a corresponding section or a position in the section for an input RGB color pixel. The conversion process is performed on 8 bits of a 24-bit input pixel.
This is executed using the section table 482 and the section position table 483 for each bit input color channel. In FIG. 56, an 8-bit input color element 481 displays a decimal number 4 in a binary format, and this 8-bit input color element 481 is used as a lookup in a section table or a section position table. Section table 482
Outputs one of the sections from 0 to 14 in which the input color element value 481 exists in 4 bits. Similarly, the section table 482 indicates the position in the section where the input color value element 481 exists. The intra-section table stores an 8-bit value ranging from 0 to 255, and this value is interpreted as a 256 fraction. Therefore, in the case of the input color value element 481 that represents the decimal number 4 in binary, the output value 0 is generated by looking up the section table 482. Further, by looking up the input value 4 in the section position table 483, an output value 160 representing the fraction 160/256 is generated. As can be seen from the section table 482 and the section position table 483, the section lengths are not uniform. As described above, the section length is determined by the nonlinearity of the transfer function.

As described above, by using the section table and the intra-section position table for each RGB color element, three section outputs and three intra-section position outputs can be obtained. The section / in-section position table for each color element is loaded into the MUV buffer (FIG. 2), and the main data path 24
2 accessed. MUV in color conversion processing
FIG. 57 shows the configuration of the buffer 250. The MUV buffer 250 (FIG. 57) has 3
Area 488, 489, 490. Each area (for example, 488) further includes a 4-bit section table and 8 sections.
It is divided into a bit position table within the section. The 12-bit output 492 is extracted from the MUV buffer 250 by the main data path unit 242 for each input color channel. In the above example of a single input color element of decimal four, the 12-bit output would be 000001010000.

FIG. 58 is a diagram showing an example of the interpolation processing. The interpolation process is performed in one three-dimensional space 500 (for example, RG
B color space) to another color space (for example, CMY or CM
YK) is the main processing. Pixels P0 to P
7 exist roughly in the RGB input color space, and the corresponding output color values CV (P0) to CV (P
7). The output color element value of the input pixel Pi located between the pixels P0 and P7 is determined as follows. First, both ends P0, P1,... Of the section surrounding the input pixel Pi. . . , P7 are determined. Next, the intra-section position elements frac_r, frac_g, and frac_b are determined. Finally, the output color values CV (P0) to CV (P7) corresponding to both ends of P0 to P7 are interpolated using the intra-section position elements. I do.

In the interpolation processing, first, one-dimensional interpolation in the red (R) direction is performed, and temp11, temp12, temp1
3, The value of temp14 is determined from the following equation. temp11 = CV (P0) + frac_r (CV (P1) -CV (P0)) temp12 = CV (P2) + frac_r (CV (P3) -CV (P2)) temp13 = CV (P4) + frac_r (CV (P5) -CV) (P4)) temp14 = CV (P6) + frac_r (CV (P7) -CV (P6)) Next, the interpolation process is performed by using the following equations as temp21, t
emp22 is obtained, and one-dimensional interpolation in the green (G) direction is calculated.

Temp21 = temp11 + frac_g (temp12−temp11) temp22 = temp13 + frac_g (temp14−temp13) Finally, the final color output value is obtained based on the following equation, and the final dimension interpolation in the blue (B) direction is performed. final = temp21 + flag_b (temp22-temp21) There is often a possibility that the range between the input and the output does not match. Here, if the output range is smaller than the input range, it is often necessary to clamp the range at both ends. That is,
Undesirable distortion often occurs when converting colors near the edges of a range. FIG. 59 illustrates an example in which this problem occurs, and shows how input range values are one-dimensionally mapped to output range values. Here, it is assumed that the output value with respect to the input value is determined by points 510 and 511. Assuming that the maximum output value is clamped at point 512, point 511 must be an output of this magnitude.
Therefore, when two points 510 and 511 are interpolated, the line 515 becomes an interpolation line, and the output value 517 corresponds to the input point 516. However, if the output value is point 518 when there is no range constraint, this technique is not always the optimal color mapping. 5
The interpolation line between 10 and 518 produces an output value 519 for the input point 516. Such a difference between the two output values 517 and 519 often results in noticeable distortion, especially when printing colors near the end of the range. To avoid this problem, the main data path section uses the extended output color It can also be calculated in space and scaled or clamped to an appropriate range using the following formula:

[0176] In FIG. 58, the interpolation processing is executed in either the SOCGS conversion mode for converting RGB pixels to a single output color element (for example, cyan) or the MOGCS mode for simultaneously converting RGB pixels to all output color elements.
When color conversion is performed on each pixel in an image, several million pixels are color-converted independently. Therefore, in order to operate at high speed, it is desirable to quickly find eight values (P0-P7) around the input value.

As described with reference to FIG. 57, main data path section 242 extracts a 12-bit output consisting of a 4-bit section and a position in an 8-bit section for each color input channel. The main data path unit 242 connects the 4-bit sections of the red, green, and blue channels, and forms a single 12-bit address (IR, IG, IB) as indicated by 520 in FIG.
Generate FIG. 60 shows a single 12-bit address 520
FIG. 10 is a data flow diagram showing a state in which a single output color element 563 is obtained from. The 12-bit address 520 is first sent to the address generation unit of the data cache control unit 240, such as the generation unit 1881 (FIG. 141), and the eight 9-bit lines for the memory banks (B0, B1,. / Byte address 521 is generated. The data cache (FIG. 2) is divided into eight independent memory banks 522, each independently addressed by eight line / byte addresses. The conversion from the 12-bit address 520 to the 8-line / byte address in the address generation unit is performed according to the following table.

Address synthesis in SOGCS mode

[0179]

[Table 12A]

Here, BIT [8: 6], BIT [5:
3] and BIT [2: 0] indicate 6 to 8 bits, 3 to 5 bits, and 0 to 2 bits of a 9-bit bank address, respectively. Also, R [3: 1], G [3: 1], B
[3: 1] indicates the first to third bits of the 4-bit section IR, IG, IB of the 12-bit address 520. For the memory bank 5 in Table 12, the mapping from 12 bits to 9 bits will be described in detail. 1 to 3 bits of the 4-bit red section Ir in the 12-bit address 520 are mapped to 6 to 8 bits of the 9-bit address B5,
The 1 to 3 bits of the bit green section Ig are added and mapped to 3 to 5 bits of the 9-bit address B5, and the 1 to 3 bits of the 4-bit blue section Ib are mapped to 0 to 2 bits of the 9-bit address B5. .

The eight line / byte addresses 521 are
Corresponding memory bank 522 consisting of 512 × 8 bits
And the corresponding 8-bit output color element 523 is latched from each memory bank 522.
According to this addressing process, the output color values CV (P0) to CV (P7) corresponding to the end points P0 to P7 may be different addresses in the memory bank. For example, 1
The 2-bit address 0000 0000 0000 gives the same bank address of 0000 000 000 in all banks, but the 12-bit address 000
In the case of 000000001, banks 7, 5, 3,
1, bank address 0000000000, and banks 6, 4, 2, 0, bank address 0000 000
A different bank address is obtained so as to be 001. In this way, eight single output color values CV (P0) to CV (P7) surrounding an input pixel value are simultaneously obtained from each memory bank, and the output color values in the memory banks are prevented from being duplicated. Can be.

FIG. 61 shows a configuration of a memory bank of the data cache 230 used in the single color conversion mode. Each memory bank is composed of 128 line entries, and each line entry is composed of 4 × 8 bit memories 533 to 536 having a 32-bit length. The upper 7 bits of the memory address 521 determine the corresponding data string in the memory address, and are latched as a memory bank output.
2 The lower two bits are a byte address, which is input to the multiplexer 543, and which 4 × 8
It is used to determine whether to select 544 a bit entry as an output. Data for each of the eight memory banks is output every clock cycle and sent to main data path unit 242. That is, the data cache control unit receives the 12-bit byte address from the operand organizer 248 (FIG. 2), and outputs an 8-bit output color value for the interpolation processing in the main data path unit 242 to the operand organizers 247 and 248.

In FIG. 60, main data path section 242
(FIG. 2) executes the interpolation process in three steps. In a first step in the main data path section, the multiplication / addition section (e.g., 550) may use a corresponding memory bank (e.g., 52
The color value output from 2) and the red section position element 551 are input, and four output values are calculated according to the first step of the above equation. Output of the first step (for example, 553, 55
4) is sent to a second step 556, which uses the frac_g input 557 to output 558 according to the previous equation of the second step.
Is calculated. Finally, the second step outputs 558, 559
And the frac_b input 562 to calculate the final output color 563 based on the previous equation.

The processing shown in FIG. 60 is pipelined in order to obtain the maximum throughput as a whole. 60 is used when a single output color element 563 is required. For example, the method of FIG. 60 is used in a case where the cyan component of the output image is generated first, and then the cache table between passes is reloaded to generate the magenta, yellow, and black components of the output image. This is particularly suitable for a four-pass printing process in which each output color is an independent pass. b. Multiple output general color space mode The coprocessor 224 also operates in the MOGCS mode, but the MOGCS mode is the same as the SOCG mode except for a few points.
The operation is almost the same as in the S mode. In the MOGCS mode, the main data path unit 242, the data cache control unit 240, and the data cache in FIG. 2 cooperate to simultaneously output the four main color elements to be output. For this purpose, the size of the data cache 230 is required to be four times, but in the MOGCS operation mode, the data cache control unit 240 uses only one-fourth of all output color values of the output color space to save storage space. Store. The remaining output color values of the output color space are stored in a low speed external memory and retrieved when needed. The present apparatus and method are based on the surprising fact that the coarse color conversion table in the cache system has a very low miss rate. This is based on the finding that in many color images, the variance of the color value between one pixel and another pixel is small. Also, the coarse output color values are very likely to be the same for neighboring pixels.

FIG. 62 shows a method in which the coprocessor executes a multi-channel cache color conversion. After each input pixel is decomposed into color components, the corresponding section table values (FIG. 56) are determined as described above, and Ir, Ig, I
Three 4-bit intervals such as b570 are obtained. The combined 12-bit number 570 is converted according to Table 12 above to obtain eight 9-bit addresses. The address (eg, 572) is remapped as described below in FIG. 63, and the corresponding memory bank 573 is looked up to obtain four color output channels 574. The memory bank 573 can store 512 × 32 bit entries, of which 128 × 32 bit entries are stored. The memory bank 573 forms a part of the data cache 230 and is used as a cache as described in FIG.

FIG. 63 shows that 9-bit bank input 578 has 5 inputs.
It shows that it is remapped to 79, bit 5
By changing the order of 80 to 582, the alias of the memory pattern can be removed. This can reduce the probability that adjacent pixel values will be aliased for the same cache element. The reconstructed memory addresses 579 are 32 bits each of 12 bits.
A corresponding memory bank of 8 entries (eg, 58
Used as address to 5). By accessing the memory 585 using the 7-bit line address, an output latched 586 for each memory bank is obtained.
Each memory bank (eg, 585) has an associated tag memory, each consisting of 128 entries of 2 bits.
The 7-bit line address is also used to access a corresponding tag in the tag memory 587. By comparing up to two bits of address 579 with the corresponding tag in tag memory 587, it is determined whether the output color value is stored in the cache. The maximum 2 bits in the 9-bit address correspond to the maximum bits in the red and green data sections (see Table 12). Therefore, in the MOGCS mode, the RGB input color space is efficiently divided into four quadrants in the red and green dimensions, and up to two bits of the 9-bit address specify a quadrant in the RGB input color section.
That is, the output color value is efficiently divided into four quadrants specified by two bit tags. For this reason, the color output values corresponding to the respective tag values of a certain line are located apart in the output color space, and the alias of the memory pattern can be reduced.

If the two bit tags do not match,
The data cache controller records a cache miss and the required memory read is activated by the data cache controller along with the cache lookup process. Note that the cache lookup process is stopped until all values of the line corresponding to the 2-bit tag entry are read from the external memory and stored in the cache. This process includes a process of reading a related line of the color conversion table stored in the external memory. Since the process 575 in FIG. 63 is executed for each memory bank (for example, 573) in FIG. 62, depending on the cache contents, it may take time until a result (for example, 586) is output from the memory bank. Data 58
The eight 32-bit sets 6 are then transferred to the main data path section (242), where
Steps 590-592 are performed on all color channels simultaneously and in a pipelined process to generate four color books 595 to send to the printer device.

According to the experiment, since the cache miss rate in a general image is a cache line fetch for each pixel of 0.01 to 0.03 on average, FIG.
63 shows that the cache mechanism shown in FIG. 63 is effective. By using such a cache mechanism, in many cases, requests for memory access outside the data cache can be significantly reduced.

The instruction encoding in the two color space conversion modes (FIG. 10) performed by the coprocessor has the following structure. Instruction encoding in color space conversion

[0190]

[Table 12B]

FIG. 64 shows the instruction field encoding in the color space conversion instruction. The minor opcode encoding in the color conversion instruction is as follows. Minor opcode encoding in color conversion instructions

[0192]

[Table 13]

FIG. 65 shows that in the MOGCS mode, R
4 shows a method of converting a GB pixel stream into CYMK color values. In step S1, a 24-bit RG
The B pixel stream is the pixel organizer 246
(FIG. 2). In step S2, as described with reference to FIGS. 56 and 57, the pixel organizer 246 determines a 4-bit section value and an 8-bit section position of each input pixel using a look-up table. The section value and the position in the section of the input pixel indicate in which section the input pixel exists and in which position in the section. In step S3, the main data path unit 24
2 combines the four bit intervals of the red, green and blue components of the input pixel to produce a 12 bit address word,
The 2-bit address word is transferred to the data cache control unit 24.
0 (FIG. 2). In step S4, Table 12 and FIG.
As described in, the data cache control unit 24
A 0 translates this 12-bit address word into eight 9-bit addresses. These eight addresses correspond to the memory banks 57 of the eight output values CV (P0) -CV (P7).
3 (FIG. 62). In step S5, the data cache control unit 240 (FIG. 2) remaps the eight 9-bit addresses as described with reference to FIG.
In this way, the maximum bit of the red and green 4-bit sections is mapped to a maximum of 2 bits of the 9-bit address.

In step S6, the data cache control section 240 compares a maximum of 2 bits of the 9-bit address with a 2-bit tag in the memory 587 (FIG. 63). If the 2-bit tag does not match the maximum 2 bits of the 9-bit address, the output color value CV (P0) -CV (P7) does not exist in the cache memory 230. Therefore, in step S7, the output color value corresponding to the 2-bit tag entry is read from the external memory into the data cache 230.
When the 2-bit tag matches the maximum 2 bits of the 9-bit address, the data cache control unit 240 extracts eight output color values CV (P0) -CV (P7) in step S8 as described with reference to FIG. . Thus, the eight output color values CV surrounding the input pixel
(P0) -CV (P7) is fetched from the data cache 230 by the main data path unit 242. In step S7, the output color value CV (P0) -CV (P7) is interpolated in the main data path unit 242 using the position in the section determined in step S2, and the interpolated output color value is output.

Here, it is obvious to an expert that the storage area of the data cache capacity can be reduced by further dividing the RGB color space and the corresponding output color values into four or more quadrants, for example, into 32 blocks. is there. 3
When divided into two blocks, the storage capacity of the data cache may be only 1/32 block of the output color value. It is also clear to the expert that the data cache mechanism used in the MOGCS mode can be used in the single output general conversion mode. Also in this case, the storage area of the data cache can be reduced.

3.17.3 JPEG encoding / decoding The advantages of encoding and storing images are enormous, especially in terms of memory savings and image transfer speed from one place to another. A variety of widely distributed standards have emerged for image coding. One of the very famous standards is the JPEG standard, but a detailed description of the JPEG standard can be found in Van Nostrand Rein.
Penneba published in 1993 by Hold
A well-known book by ker and Mitchell, "JPEG:
Still Image Data Compress
See “ion Standard”. Coprocessor 224 stores the image using a subset of the JPEG standard. An advantage of the JPEG standard is that a large compression ratio can be obtained while maintaining image quality. Of course, other standards may be used to compress and store the image. JP
The EG standard is a standard well known to experts,
Various products implementing JPEG that can be used for CS are commercially available from manufacturers including JPEG core products and the like.

The coprocessor 224 has a function of JPEG encoding / decoding an image composed of 1, 3, and 4 color elements. The one-color element image may or may not be a mesh. That is, one color element can be extracted as either mesh data or unmeshed data. As an example of mesh data, there are three color elements for each pixel data (that is, RGB for each pixel data). As an example of non-meshed data, each color element of an image is stored separately and each color element is processed independently. Data that can be used. For a three-color component image, coprocessor 224 uses one pixel per word, assuming that the three-color channel is encoded to a minimum of three bytes.

The JPEG standard defines an image as a minimum coding part (M
CU) is divided into small two-dimensional parts. Here, each minimum coding part is processed independently. The JPEG encoder (FIG. 2) may be an MCU of 16 pixels horizontally and 8 pixels vertically of a down-sampled image, or may be an MCU of 8 pixels horizontally and 8 pixels vertically for an image that has not been down-sampled.

FIG. 66 shows a method of down-sampling a three-element image. Original pixel data 600
Means that each pixel 601 is Y, U, V in YUV color space
It is stored in the MUV buffer 250 (FIG. 2) in pixel format consisting of elements. This data is first converted to an MCU part consisting of four data blocks 601 to 604. The data block contains various color components, and block 6
01 and 602 are directly sampled Y elements, and blocks 603 and 604 are U and V elements that are subsampled in the example of FIG. Here, the coprocessor 224 has two types of subsampling functions. One is direct sampling without filtering, in which odd pixel data is left and even pixel data is deleted. It is also possible to filter the U and V elements by averaging adjacent values.

Another JPEG subsampling is:
This is the four-color channel sub-sampling shown in FIG.
In this sub-sampling, a pixel data block of 16 × 8 pixels 610 has four elements 611 including an opacity element (O) in addition to normal Y, U, V elements. This pixel data 610 is also sub-sampled as in FIG. However, in this case, data blocks 612 and 613 are created using the opaque channel.

FIG. 68 is a block diagram showing the JPEG encoder 241 shown in FIG.
FIG. The JPEG encoder / decoder 241 performs both JPEG encoding and decoding. The encoding process receives block data from the pixel organizer 246 (FIG. 2) via the bus 620. The block data is stored in the MUV buffer 250, and is processed for each block. The JPEG encoding process is divided into several distinct steps. These steps are: 1. Execution of discrete cosine transform in DCT section 621 2. DCT output quantization 622 3. Arrangement of DCT coefficients by zigzag scan executed by quantizer 622 4. Predictive coding of DC DCT coefficients and run-length coding of AC DCT coefficients performed by coefficient encoder 623 Variable length coding of the output of the coefficient coder performed by the Huffman coder 624. The output is sent through multiplexer 625 and Rbus 626 to result organizer 629 (FIG. 2).

The JPEG decoding process is the reverse of the JPEG encoding operation. That is, the JPEG decoding process
The process includes inputting a compressed JPEG block from the us. The compressed data is sent to the Huffman encoder 624 via the Bus 630, and the data is decoded into a DC difference and an AC run length. Next, the data is sent to a coefficient encoder 623 where the AC and DC coefficients are decoded and returned to normal scanning. Thereafter, the quantizer 622 performs inverse quantization of the DC coefficient by multiplying the DC coefficient by a corresponding quantization value. Finally, the DCT section 621 performs inverse discrete cosine transform to restore the original data, and the multiplexer 625 and the Bu through the Bus 631.
It is sent to the result organizer via s626. JPE
The G encoder 241 operates in a normal manner via a standard Cbus interface 632 that includes a register set by the instruction controller to initiate operation of the JPEG encoder. Also, quantizer 622 and Huffman encoder 624 require tables, which are loaded from data cache 230 when needed. The table data is accessed via the Obus interface unit 634. Here, the Obus interface unit 634 is connected to the operand organizer B247,
It interacts with the data cache control unit 240.

The DCT section 621 performs a discrete cosine transform and an inverse discrete cosine transform on the pixel data. DC
Regarding T, various types of DCT transform realization methods are known, and “Still Image Data” is known.
Compression Standard "(ibid.)
, The DCT 621 uses the high-speed technique described in detail in the following section, "High-speed DCT device."
Note that in the DCT conversion operation, The Trans
actions of the IEICE, vol.
E71, no. 11, November 1988-1
Arai et al.'S paper “A
Fast DCT-SQ Scheme for I
DCT transform method based on “images”.

The quantizer 622 performs quantization and inverse quantization of the DCT coefficient, and obtains an associated value from the corresponding table stored in the data cache by the Obus interface unit 634.
It works by taking out via. In the quantization process, the input data stream is divided by a value read from a quantization table in a data cache.
This division is implemented as a fixed-point multiplication. Also,
In the inverse quantization process, the data stream is multiplied by the values in the inverse quantization table.

FIG. 69 is a diagram for explaining the inverse quantization 622 in more detail. The quantizer 622 passes data to the DCT module 621 via the local bus,
DC for receiving data from T module 621
A T interface 640 is provided. In the quantization process, quantizer 622 uses two Ds per clock cycle.
Receive CT coefficients. These values are written to one of the internal buffers 641, 642 of the quantizer. Buffer 6
Reference numerals 41 and 642 denote buffers provided with two ports for buffering input data. In the quantization process,
The coefficient data from DCT sub-module 621 is stored in one of buffers 641 and 642. When the buffer becomes full, data is read from the buffer by zigzag scanning and multiplied by the multiplier 643 with the quantized value received via the Obus interface unit 634. This output is transferred to the coefficient encoder 623 (FIG. 68) via the coefficient encoding interface 645. While these processes are being performed, the coefficient of the next block is being written to another buffer. In the JPEG decoding process, the quantization module performs the inverse quantization process by multiplying the DCT coefficient decoded by the value stored in the table.
The multiplier 643 is used in both the quantization and the inverse quantization because the quantization and the inverse quantization operate exclusively. Note that the position of a coefficient in an 8 × 8 block is used as an index into the inverse quantization table.

Similarly to the quantization processing, the two buffers 64
1, 642 are used to buffer the input coefficient data from coefficient encoder 623 (FIG. 68). The data is multiplied by the quantized value and written to the buffer in reverse zigzag scan order. When the buffer is full, two inversely quantized coefficients are simultaneously read from the buffer in the usual order and sent to the DCT sub-module 621 (FIG. 68) via the DCT interface 640. Therefore, the coefficient encoder interface module 645 serves as an interface with the coefficient encoder, and sends data to and reads data from the encoder via the local bus. This module reads data from the buffer in zigzag scan order during encoding,
At the time of decoding, data is written to the buffer in reverse zigzag scan order. DCT interface module 640 and C
The C interface module 645 can also read from and write to the buffer. Therefore, the address / control multiplexer 647 is used to determine which buffer each interface is operating with, under the control of a control module 648, which consists of a state machine for controlling all modules of the quantizer. ,decide. The multiplier 643 may multiply the DCT coefficient by a quantization table value using a 16 × 8 two's complement multiplier.

Referring to FIG. 68, coefficient encoder 623 performs the following functions. (A) Predictive encoding / decoding of DC coefficient in JPEG mode (b) Run-Length encoding / decoding of AC coefficient in JPEG mode Note that the coefficient encoder 623 separates a pixel at a necessary time from the JPEG mode operation. Preferably, it can be used for predictive encoding / decoding and memory copy operations.
The coefficient encoder 623 performs prediction / run-lens encoding /
Perform decryption. Further, in addition to the run-length encoding / decoding of JPEG AC coefficients as defined in the JPEG standard, it also has a standard predictive encoding / decoding function.

The Huffman encoder 624 performs Huffman encoding / decoding of the JPEG data sequence. In the Huffman coding mode, run-Lenx-encoded data is received from the coefficient encoder 623, and a Huffman stream of packed bytes is generated. Also, in Huffman decoding mode,
The Huffman stream is read from the Pbus interface 620 in a packed byte format, and the Huffman-decoded coefficients are sent to the coefficient encoding module 623. Huffman encoder 624 is stored in the data cache and
A Huffman table accessed via a bus interface 634 is used. Alternatively, the Huffman table can be configured by hardware to increase the speed.

When using data caches in Huffman coding, the eight banks of data caches store data tables as described in detail below for each table. Huffman, quantization table stored in data cache

[0210]

[Table 14]

In FIG. 70, Huffman encoder 624
Is mainly composed of two independent blocks, an encoder 660 and a decoder 661. Both blocks 660, 6
61 is the same O through a multiplexer module 662
Share the bus interface. Each block has an input and an output, and depending on the function performed by the JPEG encoder, only one of the blocks is active at a time. a. Encoding In encoding in the JPEG mode, a variable length code (up to 16 bits for each code) is assigned to a DC difference value or an AC run length value using a Huffman table. The assigned code is sent from the CC submodule to the HC submodule. Also, the Huffman table must be pre-loaded from the data cache before the operation starts. And the variable length code is C
Combined with other bits of the DC and AC coefficients sent from the C submodule, a packed byte format is generated. As a result of the pack processing, X'FF bytes are obtained.
X'00 bytes are inserted. When the RSTm marker is required, the marker is inserted. In this case, the byte is filled with the last Huffman code “1” bit, and when the filled byte becomes X′FF. X'00 byte insertion processing is performed. Whether the RSTm marker is required
Indicated by the CC submodule. Also, the HC sub-module is configured to output E at the end of the image according to the instruction of the “last” signal on the Pbus-CC slave interface.
Insert an OI marker. In the insertion processing of the EOI marker, the same packing processing, packing processing, and insertion processing as those of the RSTm marker are required. Finally, the output stream is sent to result organizer 249 as packed bytes,
Written to external memory.

In the case of the non-JPEG mode, data is sent from the CC submodule (Pbus-CC slave interface) to the encoder as unpacked data. Each byte is independently coded using a table pre-loaded into the cache (similar to JPEG mode), and the variable length symbols are packed into packed bytes and sent to the result organizer 249. Note that the last byte of the output stream is subjected to a 1-packing process. b. Decoding The decoding algorithm includes a high-speed (real-time) algorithm and a low-speed algorithm. The fast algorithm operates in JPEG mode only, and the slow algorithm operates in both JPEG and non-JPEG modes.

The high-speed JPEG Huffman decoding algorithm maps Huffman symbols to either DC difference values or AC run-length values. This is especially JP
It is designed to be suitable for EG, and it is assumed that the example Huffman table (K3, K4, K5, K6) is used at the time of encoding. These tables are embedded in the algorithm in hardware so that they can be decoded without referring to the cache memory.
Such a decoding process assumes a case where a decoded image must be printed while guaranteeing a certain data rate. The data rate of the HC sub-module for decoding bands (blocks delimited by RSTm markers) is approximately one DC / AC coefficient per clock cycle. Between the HC submodule and the CC submodule, one clock cycle may be required to remove the X'00 insertion byte from the data stream, but this is strongly dependent on the data.

The Huffman decoder operates in the high-speed mode and extracts one Huffman symbol every clock cycle.
The high-speed Huffman decoder is described in “Decoder of variable-length code” below. The Huffman decoder 661 has a low-speed decoding algorithm based on a heap, and has a structure 670 shown in FIG.

For a JPEG encoded stream, X'00 insertion byte, X'FF
The padding byte, the RSTm marker is removed and the Huffman symbol is shifted 672 along with the other bits combined.
Sent to Note that this processing is not performed on an encoded stream including only Huffman. The first step in Huffman symbol decoding is to store the cached HUs addressed by the first 8 bits of the Huffman data stream.
This is a process of looking up 256 entries of the FVAL table. If this value is the true length of the corresponding Huffman symbol, the value is output formatter 6
76, the symbol length of the decoded value and the number of additional bits are fed back to the shifter 672, and the associated additional bits are transferred to the output formatter 676, where
Align the new start site of the Huffman stream sent to 73. Here, the number of additional bits is a function of the decoded value. If the first lookup did not result in a decoded value, i.e., the Huffman symbol was 8 bits or more, the heap address was calculated until a match or until the "improper Huffman symbol" condition was met. Subsequently, heap (position in the cache) access is executed.
If the lookup matches, the same process is performed,
When the “unsuitable Huffman symbol” condition is satisfied, an interrupt state is set.

The decoding algorithm based on the heap is as follows. Set loop symbol length N to 8 until end of image Store first 8 bits of input stream in INDEX Fetch HUFVAL (INDEX) If HUFVAL (INDEX) == 00xx000111. . (ILL) Transmission of “inappropriate Huffman symbol” signal exit elseif HUFVAL (INDEX) == 1nnn eeeee eee e- (HIT) Transfer nnn bits as value to eeeeeee Transfer symbol length N = decimal (nnn) / * 000 as symbol length 8 * / adjustment of input stream break else / * HUFVAL (INDEX) == 01iiiiiiiiiiiiiiii-(MISS) Set to HEAPINDEX == iiiiiiiiiiii (assume heap base is 0) N = 9 If the ninth bit of the input stream is 0, increment HEAPINDEX by one. Fi VALUE = Fetch of HEAP (HEAPINDEX) (the sign of the ninth bit) Loop If VALUE == 0001 0000 111 ---- (NL) Transmission of "inappropriate Huffman symbol" signal exit elseif VALUE === 1000 eeee eeee eeeeeeeeeeee transfer symbol length N as input value adjustment input stream break else / * VALUE == 01iiiiiiiiiiii- -(MISS) Set N = N + 1 (HEAPINDEX = ii iiiii iii ii) If Nth bit of input stream is 0, HEAPINDEX is incremented by 1 fi VALUE = HEAP (HEAPINDEX) fetch pool pool Stripper 671 encodes input JPEG 671 encoding To X'00 insertion byte, X'FF padding byte,
Remove the RSTm marker and transfer the “clean” Huffman symbol to shifter 672 with the concatenated additional bits. In Huffman-only encoding, no additional bits are present, so in this mode the transferred stream consists only of Huffman symbols.

The shifter 672 block has a 16-bit output register, and transfers the next Huffman symbol to the decoding unit 673 (in a bit stream from the MSB to the LSB). Symbols are often 16 bits or less,
It is the decoding unit 6 that determines how many bits to analyze.
73. Shifter 672 provides feedback 678 from decoding section 673, that is, the current symbol length and (JP
Receive the additional bit length following the current symbol (in the EG mode) and properly align the start of the next symbol in shifter 672.

The decoding unit 673 has a core of an algorithm based on a heap, and is connected to the data cache via the Obus 674. The decoding unit 673 includes a data cache fetch block, a lookup value comparison unit,
It includes a symbol length counter, a heap index addition unit, and a decoding unit for decoding the number of additional bits (decoding is performed based on the decoded value). Here, the fetch address is interpreted as follows.

Fetch address

[0220]

[Table 15]

The output formatter block 676 decodes an 8-bit value (stand-alone Huffman mode),
32 of the 4-bit value, the additional bit, and the RSTm marker information
Combine to bit words (JPEG mode). The additional bits are transferred to the output formatter 676 by the shifter 672 after the decoding unit 673 determines the start position of the additional bits for the current symbol. The output formatter 673 also includes a two deep FIFO buffer using one word delay to predict the final word. In the decoding process, it may occur that the shifter 672 (either fast or slow) attempts to decode the last stuffing bit of the input bitstream. Such a condition is usually detected by the shifter and may result in an "inappropriate symbol"
Instead of sending an interrupt, it sends a "forced end" signal. When an active "kill" signal is issued, output formatter 676 causes the most recent one decoded word (F
(Which is still in the IFO) as "last"
Delete more recent words that do not belong to the decoded stream.

FIG. 72 shows details of Huffman encoder 660 in FIG. The Huffman encoder 660 maps byte data to Huffman symbols through a look-up table, and includes an encoding unit 681, a shifter 682, an output formatter 683, and a lookup table accessed from a cache. The input value 685 is encoded by the encoding unit 681 using the encoding table stored in the data cache. As a table, two tables are required: a table including a corresponding code for each value to be encoded and a table including a code length.
Access to the cache 230 may be performed only once when encoding a symbol. In JPEG compression, A
A separate table is required for each of the C coefficient and the DC coefficient. When subsampling is performed, a separate table is required for each subsample element and each non-subsample element. Non-JPEG compression requires only two tables (code and size). The sign is shifter 68
2 to form an output stream at the bit level. The shifter 682 also performs RSTm and EOI marker insertion processing, which are byte padding processing when necessary. Then, the data byte is output formatter 68
3 and the insertion processing at X'00 byte, X'FF
Filling with FF byte preceding byte or marker code,
Formats the packed bytes. In the non-JPEG mode, only the format processing of the packed bytes is performed.

The X'FF byte insertion processing is performed by the shifter 68.
2, the output formatter 683 needs to know which byte from the shifter 682 is a marker in order to insert the X'FF byte before.
This is done by providing a shift register 682 with a tag register corresponding to the byte. Each marker located at a byte boundary is tagged by a shifter 682 in the marker insertion process. The combination processing unit 683 does not perform insertion processing after the X “FF” byte preceding the marker. Tags are shifted in synchronization with the main shift register.

The Huffman encoder uses four or eight tables in JPEG compression and uses two tables directly for Huffman encoding. The table used is shown below. Table used in Huffman encoder

[0225]

[Table 16]

3.17.4 Table Indexing The Huffman table contains the coprocessor data cache 2
At 30 it is stored locally. Data cache 230 is configured as a 128 line direct mapping cache, with each line consisting of 8 words. Each word in the cache line can be addressed independently, and this feature is used by the Huffman decoder to access multiple tables simultaneously. The table is small (≦ 256
Item), an index to a plurality of tables can be included in the Obus 32-bit address field.

As described above, in the JPEG low-speed decoding mode, a data cache is used to store various Huffman tables. The format of the data cache is shown below. Huffman / Quantization table bank address

[0228]

[Table 17]

Before the JPEG instruction is executed in the JPEG encoder 241 (FIG. 2), an appropriate image width value must be set in the image dimension register (PO_IDR) or (RO_IDR). As with other instructions, the length of the instruction is related to the number of input data items to be processed. This includes any padding data and is related to the subsampling options and the number of color channels used.

Every instruction issued by coprocessor 224 uses two functions to limit the amount of output data generated. These functions are most effective when the size of input and output data is different.
This is effective when the output data size is unknown as in G encoding / decoding. These functions determine whether to write out the output data or simply delete the data while making it appear that the instruction was properly executed. By default, this feature is off and is turned on by enabling the appropriate bit in the RO_CFG register. However, the JPEG instruction has a special option to set this bit. When JPEG compression is used, the coprocessor 224 deletes the output data.
And support for "restriction" functions.

The deletion and restriction processing will be described with reference to FIG. The input image 690 has a certain height 691 and a certain width 692
And Here, we are only interested in a part of the image,
There are often situations where other parts have nothing to do with printing. However, the JPEG encoding system targets 8 × 8 pixel blocks. Therefore, when the width of the image is not a multiple of 8, or when the MCU 6
There is a case where the region of interest constituting 95 does not exactly match the boundary. Therefore, the output deletion register RO_CU
T determines the number of output bytes to delete at the beginning 696 of the output data stream. The output limit register RO_LMT determines the maximum number of output bytes to be generated. This maximum number of output bytes includes those bytes that are not written to memory based on the result of the delete register. By such processing, it is possible to obtain a final output byte such that data after the final output byte 698 is not output.

There are two cases where the deletion and restriction functions in the JPEG decoder are particularly effective. The first case is a case where one portion 700 of one strip 701 of the decoded image is extracted or decompressed as shown in FIG. In the second case, as shown in FIG. 75, in the entire image 714, multiple complete strips (eg,
711, 712, and 713).

FIG. 76 shows the instruction format and the field encoding of the JPEG instruction. The description of the minor opcode field is described below. Instruction word-minor opcode field

[0234]

[Table 18]

3.17.5 Data Coding Instruction The coprocessor 224 preferably has a function that allows a part of the JPEG encoder shown in FIG. 2 to be used for other purposes. For example, Huffman coding is used not only in JPEG but also in other compression methods. It is also desirable that a data encoding instruction for controlling the Huffman encoding unit be provided only for hierarchical image decoding. Further, the run-lens encoder / decoder and prediction encoder can be used independently with similar instructions.

3.17.6 High-Speed DCT Apparatus A conventional discrete cosine transform (DC) as shown in FIG.
T) In the apparatus, first, 1 ×
Perform a two-dimensional transform of the 8 × 8 pixel block by performing a one-dimensional DCT in the row direction of the 8 × 8 pixel block, then performing a one-dimensional DCT in the row direction of the 8 × 8 pixel block. In such a device, an input circuit 1096, an arithmetic circuit 1104, a control circuit 1098, a replacement memory circuit 1090, an output circuit 1092
Is generally provided.

The input circuit 1096 converts 8 × 8 blocks to 8
Receive a bit pixel. The input circuit 1096 is connected to the arithmetic circuit 1 via the intermediate multiplexers 1100 and 1102.
104. The arithmetic circuit 1104 is 8 × 8
Perform arithmetic on the complete column or row of a block. The control circuit 1098 controls all other circuits,
Execute the CT algorithm. The output of the arithmetic circuit is output from the replacement memory 1090, the register 1095, the output circuit 1092.
Sent to The replacement memory further includes a multiplexer 1100
And the multiplexer 1100 sends the output to the next multiplexer 1102. Multiplexer 1102 also receives data from register 1094. The replacement circuit 1090 inputs 8 × 8 block data in a column format and outputs data in a row format. Output circuit 109
2 outputs DCT coefficients for 8 × 8 blocks of pixel data.

In a normal DCT device, the arithmetic circuit 1104
Is the most complex, the speed of the arithmetic circuit 1104 determines the overall device speed. Arithmetic circuit 1104 in FIG. 77
Generally performs arithmetic processing by dividing arithmetic processing into a plurality of processing steps as described with reference to FIG. Thus, a single circuit is used that performs each processing step 1144, 1148, 1152, 1156 using normal resources such as adders and multipliers. Such an arithmetic circuit 1104 has the disadvantage that the speed is slower than the optimal speed because a single common circuit is used to execute the various processing stages of the circuit 1104. This also includes storage means for storing intermediate results. Since the clock cycle time of the circuit must be at least as long as the slowest circuit stage, the time required for the entire process can be equal to or greater than the sum of the time required for each processing stage.

FIG. 78 shows a normal arithmetic data path in the apparatus shown in FIG. 77, and shows a part of the processing for performing the DCT in four processing stages. Note that this drawing does not show actual implementation but shows functions. Each of the four processing stages 1144, 1148, 1152, 1156 is built as a single reconfigurable circuit. 4 cycles of 1D DCT 1144, 1
Each of 148, 1152, 1156 is reconfigured. Also, in this circuit, four processing steps 1144,
Each of 1148, 1152, and 1156 uses a pool of common resources (such as an adder and a multiplier), so that the hardware scale can be reduced.

However, a disadvantage of this circuit is that the speed is not optimal. 4 processing steps 1144, 1
Each of 148, 1152 and 1156 is composed of the same pool of adders and multipliers. Thus, the clock period is determined by the slowest processing stage (in this example, 20 ns of block 1144). Delay of input and output multiplexers 1146 and 1154 (2n each
s) and the delay of the flip-flop 1150 (3 ns), the total delay is 27 ns. Therefore, this D
In the CT configuration, it operates at a maximum speed of 27 ns.

The DCT configuration of the pipeline type is well known. The disadvantage of this configuration is that it requires a lot of hardware. Although the configuration of the present invention does not reach the pipeline configuration from the viewpoint of throughput, it exhibits extremely good performance / size characteristics and speed characteristics as compared with most current DCT configurations. FIG. 79 is a diagram showing a configuration of a suitable discrete cosine transform unit used in a JPEG encoder (FIG. 2) in which pixel data is input to an input circuit 1126 and stores a column of 8-bit pixel data. . The permutation memory converts the columnar data to row-format data to perform the second pass of the two-dimensional discrete cosine transform. Input circuit 1126 and replacement memory 1118
Are multiplexed in a multiplexer 1124 and the output data is sent to an arithmetic circuit 1122. The result of the arithmetic circuit 1122 is sent to the output circuit 1120 after the end of the second pass. Control circuit 1116
Controls the data flow in the discrete cosine transform device.

In the first pass of the discrete cosine transform processing, a transformed image coefficient to be inversely transformed into column data or pixel data of an image to be transformed is sent to the input circuit 1126. In this path, the multiplexer 1124 is set by the control circuit 1116, and data is sent from the input circuit 1126 to the arithmetic circuit 1122. FIG. 80 is a diagram showing the configuration of the arithmetic circuit 1122 in more detail. In the case of executing the forward discrete cosine transform, the result of the forward circuit 1138 that executes the forward discrete cosine transform is selected in the multiplexer 1124. Here, the multiplexer 1124 is set by the control circuit 1116. In the case of performing the inverse discrete cosine transform, the inverse circuit 114 is set based on the setting of the control circuit 1126.
The output from 0 is selected in multiplexer 1142. In the first pass, each column vector is stored in the arithmetic circuit 11
22 (set appropriately by the control circuit 1166), the vector is
Written in 8. When all eight column vectors in the 8 × 8 block have been processed and written to the permutation memory 1118, the second pass of the discrete cosine transform is started.

In the second pass of the forward or inverse discrete cosine transform, the vector in row format is
18 and sent to the arithmetic circuit 1122 via the multiplexer 1124. In this pass, the multiplexer 1124 is set by the control circuit to ignore the data from the input circuit 1136 and to transfer the row vector data from the replacement memory 1118 to the arithmetic circuit 1122. Multiplexer 1142 in arithmetic circuit 1122
Converts the result data from the inverse circuit 1140 into the arithmetic circuit 112
Send to the output of 2. When the result from the arithmetic circuit 1122 is obtained, the output circuit 1120 takes in the result based on a command from the control circuit 1116 and outputs the result at a subsequent time.

Arithmetic circuit 1122 is a combinational circuit in that it does not have a storage section for storing intermediate results. The control circuit 1116 outputs data to the input circuit 113.
Since the time required from 6 to the output from the multiplexer 1124 and the arithmetic circuit 1122 is known,
The time at which the result vector from the output of the arithmetic circuit 1122 is taken into the output circuit 1120 can be accurately indicated. The advantage of having no intermediate storage in the arithmetic circuit 1122 is that the time required for exchanging data with the intermediate storage element can be saved, and the time required for data to pass through the arithmetic circuit 1122 is reduced by the internal processing stage. That is, the sum of all of them does not become N times the processing stage requiring the longest time (as in the conventional discrete cosine transform device). Here, N is the number of processing stages in the arithmetic circuit.

FIG. 81 shows that the total delay is simply the sum of four processing stages 1158, 1160, 1162, 1164, 20n
s + 10 ns + 12 ns + 15 ns = 57 ns,
It shows that the speed is higher than that of the circuit of FIG. According to such a circuit, the entire system clock cycle can be shortened. Assuming that four clock cycles are required to obtain the result in the circuit of FIG.
The minimum execution time for the entire DCT system is 57/4
ns (14.25 ns), and in FIG. 78, it can be seen that the performance is greatly improved in consideration of the fact that the DCT clock cycle must be 27 ns.

At the time of actual execution of the present DCT apparatus,
Yukihiro Arai, Takeshi Agu
i, Th by Masayuki Nakajima et al.
eTransactions of the IEIC
E, vol, E71, no. 11, a paper "High-speed D for Images" published on page 1095 of November 1988.
The DCT algorithm described in “CT-SQ method” can also be used. By executing this algorithm by hardware, it can be easily arranged in the arithmetic circuit 1122 in the DCT device. Similarly, other DCT algorithms can be implemented as hardware in arithmetic circuit 1122.

3.17.7 Huffman Decoder The following embodiment relates to a method and apparatus for a variable length code in which bit fields of various lengths are interleaved. In particular, embodiments of the present invention provide for efficient, fast, single processing stage (clock cycle) decoding of variable length encoded data. Here, it is assumed that data that is not variable-length coded but is aligned has already been deleted from the coded data stream in another preprocessing block. Further, the position information of the deleted byte-aligned data is sent to the output of the decoder at the same time as the data to be decoded. It also provides for alignment of bytes remaining in the preprocessed input data, fast detection of non-variable length coded bit fields, and elimination.

In a preferred embodiment of the present invention, it is desirable to have a high-speed Huffman decoder capable of decoding JPEG encoded data at a rate of one Huffman symbol per clock cycle between marker codes. This includes, in another preprocessing block, a marker header that is byte-aligned from the input data and not Huffman coded,
This can be realized by a method of separating and removing the marker code and the insertion byte. When the byte-aligned data is removed, the input data is sent to the data shift combination circuit block to perform a continuous insertion process of the data decoding register, and the data is sent to the decoding part. The position of the marker removed from the original input data is sent to the marker shift block, and the marker position bits are shifted simultaneously with the input data shifted in the data shift block.

The decoding section decodes the coded bit field input from the data decoding register by the combination circuit.
The output of the decoder is the decoded value (v) and the actual length (m) of the input code. Here, m is n or less. It also outputs the length (a) of the variable length bit field. here,
a is a value of 0 or more. Since the variable length bit field is not Huffman coded, it is immediately Huffman coded. The bit field of length n in the input of the decoding unit has a length greater than the actual code. The decoding unit determines the actual code length (m) and transfers it to the control block together with the length of the other bits (a). The control block determines the shift value (a
+ M) and activates the data / marker shift block to shift the input data in preparation for the next decoding cycle.

In the apparatus of the present invention, if the decoded value, the actual length of the input code, and the length of the bit field not subjected to Huffman coding are output within a predetermined time, RO
A decoding unit of any combinational circuit such as M, RAM, and PLA can be used. In the present embodiment, the decoding unit
It outputs predictive coded DC coefficient values and AC run length values as specified in the EG standard. Further, as specified in the JPEG standard, the non-Huffman-coded bit field removed from the input data at the same time as the decoded value indicates additional bits that determine the values of the DC and AC coefficients. Another type of non-Huffman coded bit field removed from the data in the data decoding register is a padding bit preceding the byte alignment marker in the original input data stream as specified in the JPEG standard. is there. These bits are detected by the control block checking the contents of the padding area of the data register. The padding area consists of the k most significant bits of the data register and is indicated by the presence of a marker bit in the largest bit of the marker register. If all bits in the padding area are the same (1 in the JPEG standard), they are determined as padding bits and are removed from the data register without being decoded. Then, the data and the contents of the marker register are updated for the next decoding cycle.

The apparatus embodiment includes an output block for performing output data format processing as required by the preferred embodiment of the present invention. The output block is a signal indicating the position of a corresponding non-variable-length coded bit field such as an additional bit in JPEG, an input byte aligned as a marker in JPEG, or an uncoded bit field. And outputs the decoded value.

Data decoded by the JPEG encoder 241 (FIG. 2) is JPEG compatible,
Variable length uncoded bit fields called "additional bits", variable length uncoded knit fields called "padding fields", fixed lengths called "markers", "insertion bytes", and "stuffing bytes" The byte-aligned, uncoded bit field consists of an interleaved variable length Huffman coded code. FIG. 82 shows typical input data.

FIGS. 83 and 84 show the entire configuration and data flow in the Huffman decoder of the JPEG encoder 241. FIG.
FIG. 83 shows the configuration of the Huffman decoder for JPEG data in detail. The stripper 1171 removes the marker code (code FFXXhex, XX is non-zero), inserts a byte (code FFhex), and fills the byte (code 00hex following the code Ffhex). These are all byte-aligned elements of the input data and are sent to the stripper as 32-bit words. The largest bit of the first word to be processed is at the beginning of the input bit stream. In the stripper 1171, the byte-aligned bit field is removed from the input data before the Huffman code decoding process is actually performed in the downstream part of the decoder.

The input data is input to stripper 1171 as one 32-bit word in each clock cycle. FIG. 85 shows the numbering of the input bytes 1211 from 0 to 3. If the byte with number (i) is removed because it is an insertion byte, a padding byte, or a marker,
The remaining bytes from the number (i-1) to 0 are the stripper 11
At the output of 71, it is shifted left and decrements the number (i) by one.
At this time, byte 0 becomes an “irrelevant” byte. The validity of the byte output from the stripper 1171 is shown in FIG.
Are encoded by another output tag 1212 shown in FIG. Bytes not removed by stripper 1171 are output left-justified in the stripper. For each byte being output, the corresponding byte is valid (stripper 1171).
), Invalid (removed by the stripper 1171), or valid and at the rear of the marker. Tag 1212 controls the loading of data bytes into data register 1182 through the data shifter and marker register 1183 through the marker shifter.
Control the loading of marker positions into 1 from input word
A similar technique is performed when more than one byte is deleted. That is, all remaining valid bytes are left justified, and the corresponding output tag indicates the validity of the output byte. FIG. 85 shows examples 1213 of output bytes and output tags for various combinations of input bytes.

In FIG. 83, the roles of the pre-shifter and post-shifter blocks 1172, 1173, 1180 and 1181 are as follows.
That is, when there is a sufficient free area in the data register 83, data is continuously loaded into the data register and the marker register. The data shifter and the marker shifter block are composed of a pre-shifter block and a post-shifter block, which are identical and controlled similarly. The difference is that the data shifter processes the data from the stripper 1171 while the marker shifter processes only the tags and outputs the marker positions to the decoder at the same time as the decoded Huffman values. The outputs of the post shifters 1180 and 1181 are shown in FIG.
Corresponding registers 1182, 11 as shown in FIG.
83 directly.

FIG. 86 also shows data pre-shifter 1172. Data pre-shifter 1172 adds 32 zeros to the minimum bit 1 in the data from stripper 1171.
251 to extend the data to 64 bits. Next, the extension data is a barrel shifter 1252 having a width of 64 bits.
To the right by the number of bits currently in the data register 1182. At this time, the number of bits is
2. Control logic 1185 that keeps track of how many valid bits are in the marker 1183 register
Given by And the barrel register 1252
64 bits are divided into 64 2 × 1 basic multiplexers 12
54 to the multiplexer block 1253. Each basic 2 × 1 multiplexer 1254 includes one bit from barrel shifter 1252 and data register 1182.
1 bit as input. The data register bit is output when the bit in the data register is valid. On the other hand, if invalid, the barrel shifter 1252
The bits of are output. All basic multiplexers 12
The control signal to register 54 is the pre-shifter control bit 0. . . 5 is decoded from the shift control 1 signal of the control block. The output of basic multiplexer 1254 is sent to barrel shifter 1255, and is shifted to the left by the number of bits given by 5-bit control signal shift control 2, as shown in FIG. These bits indicate the number of bits used for decoding the current data in the data register 1182, and include the current decoded Huffman code length followed by the number of additional bits, or padding to be deleted if padding bits are detected. If the number of bits or the number of valid bits in the data register 1182 is equal to or less than the number of bits to be deleted, 0 is added. Thus, the data output from barrel shifter 1255 contains data register 1182 after a single decode cycle.
Will contain the new data to be loaded. The contents of data register 1182 are shifted out of the register so that the most significant bit is decoded and stripper 1
From 171, 0, 8, 16, 24, and 32 bits are added to the data register 1182 and so on. If there are not enough bits in the data register 1182 to be decoded, the data from the stripper 1171, if present, is loaded in the current cycle. If there is no data from the stripper 1171 in the current cycle, the decoded bits from the data register 1182 are deleted if the number of bits is sufficient, and if not, the contents of the data register 1182 are not changed.

The marker pre-shifter 1173, post-shifter 1181 and marker register 1183 are the same as the data pre-shifter 1172, data post-shifter 1180 and data register 1182, respectively. Part 117
3, 1181 and 1183, as well as the data flow between these parts,
0, 1182. A similar control signal is sent from the control unit 1185 to both sets of parts. The difference between these sites is due to the marker pre-shifter 117.
3 and the input data type of the data pre-shifter 1172, and how the contents of the marker register 1183 and the data register 1182 are used. As shown in FIG. 88, the tag 1261 from the stripper 1171 is input as an 8-bit word, and the data register 118
Two bits are allocated for each data byte going to 2. According to the encoding method shown in FIG. 85, the maximum bit of the 2-bit tag indicating the byte that is valid and is the rear portion of the marker is 1. 4 sent simultaneously from stripper 1171
Only the maximum bit position of one tag is
173 is sent out as an input 1262. In this way, the input to the marker pre-shifter has a bit set to 1 indicating the position located at the rear of the marker in the data bit encoded first. At the same time, they mark the position of the first encoded data bit followed by a marker in data register 1182. The synchronous behavior of the marker position bits in the marker register 1183 and the data bits in the data register 1182 allows the control block 1185 to detect and remove padding bits and to simultaneously decode the marker position with the decoded data. Can be sent to output. As described above, two pre-shifters (data 1172 and marker 1173) and a post-shifter (data 1
180 and marker 1181), register (data 1182)
And the marker 1183) are supplied with the same control signal, so that complete parallel and synchronous operations are possible.

A decoding unit 1184 (also shown in FIG. 89) inputs a maximum of 16 bits of the data register 1182, and outputs a decoded Huffman value, a current input code length to be decoded, and additional bits following the input code. The length (which is a function of the decoded value) is sent to the combinational circuit decoding unit 1184 for extracting the length. The additional bit length becomes apparent when the corresponding previous Huffman symbol is decoded, and becomes the start position of the next Huffman symbol. Therefore, to maintain the rate at which one value is decoded every clock cycle, Huffman value decoding must be performed in a combinational circuit block. As shown in FIG. 89, the decoding unit receives the 16-bit token from the data register 1182 and generates a Huffman value (8 bits), a corresponding Huffman-coded symbol (4 bits), and additional bits (4 bits). It is desirable to have four PLA style decoding tables hardwired as a combinational circuit block that performs the following.

The padding bit deletion processing is performed by the control unit 1
This is performed in actual decoding processing when a padding bit string is detected in the data register 1182 in the padding bit decoding unit which is a part of the 185. FIG. 90 shows a padding bit decoding unit. Marker register 11
It is checked whether a marker position bit exists in the eight maximum bits of 83 and 1242. If the marker position bit exists, the data register 118 corresponding to the bit preceding the marker bit in the marker register 1242
2, all bits in 1241 are determined as the current padding area. The contents of the current padding area are
The padding bit detection unit 1243 checks whether all bits are 1 or not. If all bits in the current padding area are 1, it is determined that the bit is a padding bit and is deleted from the data register. here,
The deletion processing is performed by shifting the contents of the data registers 1182 and 1241 (and simultaneously the marker registers 1183 and 1242) to the left in one clock cycle using the corresponding shifters 1172, 1173, 1180 and 1181. This process is the same as the normal decoding mode except that no decoded value is output. If all bits in the current padding area are not 1, a normal decoding cycle is executed instead of a padding bit deletion cycle.
The padding bit is detected for each cycle as described above, and if a padding bit exists in the data register 1182, it is deleted.

FIG. 87 shows the control unit 1185 in detail. The central part of the control unit is a register 1223, which holds the current number of valid bits in the data register 1182. The number of valid bits in the marker register 1183 is always equal to the number of valid bits in the data register 1182. The control unit performs three functions. The first function is to calculate the new number of bits in data register 1182 stored in register 1223. The second function is shifters 1172, 1173, 1180, 1181, 1186,
1187, decoding section 1184, output format section 118
8 is the generation of a control signal. The third function is the detection of padding bits in data register 1182 as described above.

The new number of bits (new_nob) in the data register 1182 is
ob) is calculated by adding the number of bits (nos) that can be loaded from the stripper 1171 in the current cycle to the number of bits (nos) that can be loaded in the current cycle, and subtracting the number of bits (nor) deleted from the data register 1182 in the current cycle. . Here, the current cycle is a decoding cycle or a padding bit deletion cycle. Therefore, the new number of bits is calculated as follows:

New_nob = nob + nos-nor These processes are executed by the adder 1221 and the subtractor 1222. In the current cycle, the stripper 117 is used.
If no data is input from 1, (nos) becomes 0. Further, the number of bits in the data register 1182 is insufficient, that is, the bit in the data register is
Since it is equal to or less than the sum of the current code length from 85 and the subsequent additional bit length, (nos) becomes 0 even when the decoding process is not performed in the current cycle. Value (new_no
b) may exceed 64, and it is checked at block 1224 if it is. In such a case, the stripper 1171 is stopped, and no new data is loaded. Multiplexer 123
3 is used to reduce the number of bits loaded from the stripper 1171 to zero. Here, the stripper 11
The signal for stopping 71 is not shown. Decoding unit 12
The signal "padding cycle" from 31 controls the multiplexer 1234 to select the number of padding bits or the number of decoded bits (the length of the sign bit and the additional bit) as the number of bits (nor) to be deleted. If the comparator 1228 determines that the number of decoded bits is greater than or equal to the number of bits (nob) in the data register, the number of valid bits to be provided to the multiplexer 1234 is set to zero in the NAND gate 1230. That is, (nor) is set to zero, and the bit of the data register is not deleted. Multiplexer 1234
Are also used to control the post-shifters 1182 and 1183. The width of data register 1182 is set to avoid a deadlock condition. That is, it is set so that an area enough to accommodate the maximum number of bits from the stripper 1171 is secured in the data register, or a sufficient number of valid bits is deleted as a result of the decoding / padding bit deletion cycle.

The calculation of the number of bits to be deleted in the decoding cycle is performed in the adder 1226. The operand is input from combinational circuit decoding section 1184. 1
Since the 6-bit code length is encoded as “0000” in the decoding unit, the “ou_reduce” logic 122
In 5, the "0000" is encoded to "10000" to obtain the current unsigned operand. This operand and the output of subtractor 1227 provide control signals to output format shifters 1186 and 1187.

A block 1229 is used for detecting an EOI (end of image) marker position. The EOI marker itself is deleted by the stripper 1171, but the stripper 11
There is a padding bit which is the last bit of the data existing at a position preceding the EOI marker before being deleted at 71. The comparator 1229 checks whether the number of bits in the data register 1182 stored in the register 1223 is 8 or less. If it is 8 or less, no new data is input from the stripper 1171 (the data register 1182 holds the remaining bits of the data portion to be decoded), and the padding area before the EOI marker from which the remaining bits are deleted It will show the size. The processing of the padding area and the deletion of the padding bit are the same as the procedure used for the padding bit before the RST marker described above.

The barrel shifters 1186 and 1187 and the output format unit 1188 have a support division, and various implementations according to the embodiment can be considered. Also, it may not be implemented at all. These control signals are provided from the control unit 1185 as described above. The additional bit pre-shifter 1186 receives 32 bits from the data register and shifts to the left by the currently decoded Huffman code length. In this way, all additional bits following the currently decoded code will be to the left in accordance with the output of barrel shifter 1186,
Sent as input to barrel shifter 1187. The additional bit post shifter 1187 adjusts an additional bit position from left alignment to right alignment in an 11-bit field used as a data output format and also shown in FIG. The extra bits field is extended from bit 8 to bit 18 in the output word format 1196, and some of the maximum bits may be invalid depending on the actual number of extra bits. This number of bits is encoded into 1196 bits 0 to 3 as defined in the JPEG standard. When a different format is used as the output data format, the barrel shifters 1186 and 1187 and their functions are changed according to the format.

The output format block 1188 performs a process of packing decoded values, and according to the JPEG standard, the control unit 1
DC / AC coefficient (1196, bits 0 to 7) and DC coefficient indication bit (1196, bit 19) given from 185, additional bit (1196, bits 8 to 18) given from additional bit post shifter 1187, marker register 1183 Marker position bit (1
196, bit 23) into words according to the format shown in FIG. The output format unit 1188 also addresses functional requirements for the output interface of the decoding unit. If the output interface changes as a result of different functional requirements, the implementation of the output format part will usually change accordingly. The Huffman decoder described above provides a very effective decoding process and realizes a high-speed decoding process.

3.17.8 Image Conversion Instructions These instructions are for performing general affine transformation of a source image. The process of generating a part of the converted image is roughly divided into two areas. One is to determine which part of the source image is associated with the current output scan line, and the other is to perform the necessary sub-sampling / interpolation processing to generate an output image for each pixel.

FIG. 92 shows a flowchart of the step 720 required to calculate the destination pixel value, assuming that the appropriate region of the source image has been decoded. First, if subsampling has been performed, the subsample is considered at 721. Next, another interpolation processing 722 is performed.
And other processing such as subsampling processing are usually implemented. Usually, interpolation and subsampling are separate steps, but interpolation and subsampling may be performed together. In the interpolation processing, first, the surrounding 4
Find the pixel and determine if pre-multiply 723 is needed before bilinear interpolation 724 is performed. The bilinear interpolation process 724 generally requires a large amount of calculation, and this limits the image conversion processing operation. The final step in calculating the destination pixel value is to add the bilinearly interpolated subsamples from the source image. The summed pixel values are integrated 727 in various ways to produce a destination image pixel 728.

The instruction word code for the image conversion instruction is shown in FIG. 93, and the description of the minor opcode field is shown in the following table. Instruction word: minor opcode field

[0270]

[Table 19]

The description of the instruction operand and the result field is as follows. Instruction operands and result words

[0272]

[Table 20]

Operand A points to a data structure known as a "kernel descriptor" that describes all the information needed to define the actual conversion. This data structure is one of two formats
(Defined by the L bit of the A descriptor). FIG. 94
9 shows the long code format of the kernel descriptor.
5 indicates a short code format. The kernel descriptor is
Describe the following information. 1. Source image start coordinates 730 (unsigned fixed length,
24.24 resolution). Position (0,0) is the upper left of the image. 2. 2. Horizontal 731 and vertical 732 (subsample) delta (2's complement, fixed length, 24.24 resolution) 3. a 3-bit bp field 733 indicating the position of a binary point in the fixed-length matrix coefficients described below; Integral matrix coefficients 735 (if present). These are the "variable" point resolutions (2's complement) of the 20 binary points, which are the locations of the binary points implicitly specified by the bp field. 5. An rl field 736 indicating the number of words remaining in the kernel descriptor. This value is a value obtained by subtracting 1 from the value obtained by multiplying the number of columns by the number of rows.

Although the kernel coefficients of the descriptor are arranged for each column, adjacent columns are arranged in the opposite direction so as to form a zigzag scan. In FIG. 96, operand B comprises a pointer to an index table that points to the scan line of the source image. As shown in FIG. 96, the structure of the index table is such that the operand B 740 points to the index table 741, and the index table points to the scan line (eg, 742) of the required source image pixel. Generally, the index table and the source image pixels are cacheable and located in local memory.

Operand C holds the horizontal / vertical sub-sample rate. The horizontal / vertical sub-sample rate is defined by the dimensions of the sub-sample weight matrix specified when the C descriptor is present. The dimensions of the matrices r and c are encoded in the data word of the image conversion instruction as shown in FIG. Channel N of result pixel P [N]
Is calculated based on the following equation.

[0276]

(Equation 4)

Internally, the integral value is 3 for each channel.
6 binary points. The position of the binary point in the field is specified by the BP field.
The BP field indicates the number of bits ahead of the integration result to be deleted. The 36-bit integral is represented as a signed two's complement and clamped or wrapped as specified. FIG. 98 shows an example of interpretation of the BP field in the coefficient code.

3.17.9 Convolution Instruction The convolution processing applied to the rendering image is to apply a two-dimensional convolution kernel to the source image to generate a result image. Convolution is typically used in edge sharpening and various image filters. The convolution process is implemented in the coprocessor 224. In the image conversion process, the kernel is shifted by the kernel width for each output pixel, whereas in the convolution process, one kernel is output for each output pixel.
The processing is the same as the image conversion processing except that the source pixel moves.

The source image has the value S (x, y) and nx
If the m convolution kernel has the value C (x, y), then S and C
The n th channel of the convolution H [n] of

[0280]

(Equation 5)

Is given by Where i∈ [0, c],
j∈ [0, r]. The meaning of the offset value, the resolution of the intermediate result, and the meaning of the bp field are the same as those of the image conversion command. FIG. 99 is a diagram showing an example in which the convolution kernel 750 applies a source image 751 to generate a result image 752. The source image address generation and the output pixel calculation are performed in the same manner as the image conversion command. The instruction operand has the same format as the image conversion. FIG. 100 shows the instruction word codes for the convolutional instructions, and the following table describes the various fields.

Instruction word

[0283]

[Table 21]

3.17.10 Matrix Multiplication Matrix multiplication is used for color space conversion processing in which there is an affine transformation relationship in two color spaces. Matrix multiplication is defined by the following equation.

[0285]

(Equation 6)

Matrix multiply instruction operands and result words have the following format: Instruction operands and result words

[0287]

[Table 22]

FIG. 101 shows the instruction word codes for the matrix multiply instruction and the following table shows the minor opcode fields.

[0289]

[Table 23]

3.17.11 Halftoning The coprocessor 224 includes multilevel dither for halftoning. Values from 2 to 255 are significant halftone levels. The data to be halftoned can be either bytes (one channel from unmesh or mesh data) or pixels (mesh) as long as the screen is correspondingly mesh or unmesh. Up to four output channels (or four bytes from the same channel), packed bits (in the case of two-level halftones) or codes (two or more output levels), packed together or unpacked to one code per byte ) Can be generated.

The output halftone value is calculated using the following equation. (P × (l−1) + d) / 255 where p is a pixel value (0 ≦ p ≦ 255), l is the number of levels (2 ≦ l ≦ 255), and d is a dither matrix value (0 ≦ d ≦
254). Operand codes are as follows. Instruction operands and result words

[0292]

[Table 24]

In the instruction word code, the minor opcode specifies the number of halftone levels. The operand B code is for a halftone screen and is coded in a manner similar to tile synthesis. 3.17.12 Hierarchical Image Format Decoding The hierarchical image format decoding process includes multiple steps. These steps are horizontal interpolation, vertical interpolation, Huffman decoding, and residual fusion. Each step is performed with a different instruction. In the Huffman decoding step, the remaining values added to the interpolated values from the interpolation step are Huffman coded. Therefore, a JPEG decoding unit is used in Huffman decoding.

FIG. 102 shows the horizontal interpolation processing. The output stream 761 is twice as much data as the input stream 672, and the last data value 763 is duplicated 76
4. FIG. 103 shows an example in which quadruple horizontal interpolation is performed. In the second step of the hierarchical image format decoding, the pixel sequence is vertically upsampled by a factor of 2 or 4 by linear interpolation. In this step, one pixel column becomes the operand A and the other columns become the operand B.

In the case of vertical interpolation, in either case of double or quadruple, the output data stream has the same number of pixels as the input stream. FIG. 104 shows an example of vertical interpolation in which two input data streams 770 and 771 are used to generate a two-fold interpolation output stream 772 and a four-fold interpolation output stream 773. In the case of pixel interpolation, the interpolation process is performed separately for every four channels of the four channel pixels.

The remainder fusion process involves byte-by-byte addition of the two data streams. The first stream (operand A) is a base value stream, and the second stream (operand B) is a residual value stream. Fig. 105
Shows two input streams 780 and 781 and an output stream 782 corresponding to the case where the residual fusion processing is used.

FIG. 106 shows the instruction word codes of the hierarchical image format instruction. The following table shows the details of the minor opcode field. Instruction word-minor opcode field

[0298]

[Table 25]

3.17.13 Instruction Copy Instructions These instructions are divided into two distinct groups. a. General-purpose data movement instructions These instructions include an input interface module, an input interface switch 252, a pixel organizer 246, a JPEG encoder 241, a result organizer 2
49, using the normal data flow path in the coprocessor 224 comprising the output interface module. In this case, the JPEG encoding module sends the data directly without any processing.

The other instructions for the data manipulation operation include the following. -Packing and unpacking of sub-byte values (bits, 2-bit values, 4-bit values) into bytes-Packing and unpacking of bytes in words-Alignment-Byte lane swapping and duplication-Memory clear-Duplicate values Data Manipulation operations are performed with a combination of a pixel organizer (input) and a result organizer (output). These instructions are often used in combination with other instructions. b. Local DMA instruction No data operation is performed. As shown in FIG. 2, data transfer (bidirectional) is performed between the local memory 236 and the peripheral interface 237. These instructions are the only instructions whose execution overlaps with other instructions. At most one of these instructions can execute concurrently with "non-overlapping" instructions.

In the memory copy operation, operand A indicates the data to be copied, and the result operand indicates the target address of the memory copy instruction. In a general-purpose memory copy instruction, an operand B defines a data manipulation operation on an input, and an operand C defines an operation on an output operand word. 3.17.14 Flow Control Instruction The flow control instruction is an instruction group for controlling various parts of the instruction execution model as shown in FIG. Flow control instructions include conditional jumps or unconditional jumps that allow movement from one virtual address to another as the instruction stream is executed. A conditional jump instruction is determined by masking the relevant field with a coprocessor or register and comparing it with a predetermined value. This allows the generality of the instruction to be maintained. In addition, flow control instructions also include wait instructions used to synchronize between overlapping and non-overlapping instructions or as part of microprogramming.

FIG. 107 shows the codes of the flow control instructions. The following table describes the minor opcodes. Instruction word-minor opcode field

[0303]

[Table 26]

[0304] In the jump instruction, the operand A word specifies the destination address of the jump instruction. If the S bit of the minor opcode is set to 0, operand B specifies the coprocessor register and uses it as the source of the condition. The value of the operand B descriptor specifies the address of the register, and the value of the operand B word is the value for comparing the register contents. The operand C word specifies a bitwise mask applied to the result. That is, the jump instruction condition is true if the following bitwise expression is satisfied.

(((Register_value x
or Operand B) and Operand
C) = 0x0000000000) Further, the instruction is used for register access for sufficient control at the microprogramming level. 3.18 Accelerator Card Modules In FIG. 2, the various modules are further described.

3.18.1 Pixel Organizer The pixel organizer 246 specifies the address of the data stream from the input interface switch 252 and stores it in a buffer. The input data is stored in the internal memory of the pixel organizer or in the MUV buffer 250. After completing all necessary data processing on the input stream, the input stream is passed to the main data path 242 or the JPEG encoder 241 as necessary. The operation mode of the pixel organizer can be configured by a normal CBus interface. Pixel organizer 246 operates in one of five modes as specified by the PO_CFG control register. These modes are as follows. (A) Idle mode: a mode in which the pixel organizer 246 does not operate. (B) Sequential mode: input data is internal FIFO
O and the pixel organizer 24
6 is a mode for generating a 32-bit address of data and requesting data from the input interface switch 252. (C) Color space conversion mode: a mode in which the pixel organizer buffers pixels for color space conversion. Furthermore,
Requests the interval and fraction values stored in the MUV buffer 250. (D) JPEG compression mode: pixel organizer 24
6 is a mode for storing image data in the MUV buffer in MCU format. (E) Convolution operation and image conversion mode: a mode in which the pixel organizer 246 stores the matrix coefficients in the MUV buffer 250 and transmits it to the main data path 242 if necessary.

The pixel organizer 246 uses the MUV buffer 250 for operation of both the main data path 242 and the JPEG encoder 241. In color space conversion, the interval and fraction tables are stored in MUV RAM
250 and accessed as 36-bit data (4 color channels) x (4-bit interval value and 8-bit fractional value). For image transformation and convolution operations, MUV RAM 250 stores matrix coefficients and associated configuration data. The coefficient matrix is 16
It is limited to rows x 16 columns, and each coefficient is up to 20 bits wide. MUVRAM 250 requires one coefficient per clock cycle. In addition to coefficient data, control information such as binary points, source start coordinates, sub-sample deltas, etc., must also be communicated to main data path 242. This control information is fetched by the pixel organizer 246 before the matrix coefficients.

In JPEG compression, the pixel organizer 246 double buffers the MCU using the MUV buffer 250. In order to improve the performance of JPEG compression, it is desirable to use a double buffer technique. MUV
One half of RAM 250 is written using data from input interface switch 252. Meanwhile, the other half is read by the pixel organizer to get the data to send to the JPEG encoder 241. The pixel organizer 246 performs horizontal subsampling of color components where needed, and pads the MCU if the size of the input image is not an integral multiple of the MCU.

The pixel organizer 246 performs the byte lane swap, the normalization,
Byte replacement, byte pack and unpack,
It also formats input data, including copying operations.
Operation is performed as needed by setting the pixel organizer register. Referring to FIG. 108, the pixel organizer 246 will be described in more detail. The pixel organizer 246 operates according to the control of its own register set included in the CBus interface control unit 801, and
Are connected to the instruction control unit 235 via the global CBus. The pixel organizer 246 includes an operand fetch unit 802, and requests operand data required by the pixel organizer 246 from the input interface switch 252. , The start address of the operand data is specified by the PO_SAID register set immediately before execution. PO_S
The AID register may hold immediate data according to the designation by the L bit of the PO_DMR register. The current address pointer is stored in the PO_CDP register and is incremented by the burst length if required by the input interface switch. Data is MUV RA
When fetched into M250, the current offset of the data is the MUV specified by the PL_MUV register.
It is connected to the base address of the RAM 250.

The FIFO 803 is used to buffer the sequential input data fetched by the operand fetch unit 802. Data operation unit 80
4 executes various operations as described in FIG. The output of the data operation unit is the MUV address generation unit 80
It is conveyed to 5. The MUV address generation unit 805 transmits data to one of the MUV RAM 250, the main data path 242, and the JPEG encoder 241 according to the configuration register. Pixel organizer control 806 is a state machine that generates the necessary control signals for all sub-modules of pixel organizer 246. The necessary signals include signals for controlling communication on various Bus interfaces. The pixel organizer control section outputs diagnostic information required by the other module 239 according to the setting of the status register.

FIG. 109 shows the operand fetch unit 802 of FIG. 108 in more detail. The operand fetch unit 802 includes an instruction bus address generation unit (IAG) 8
10 and includes a state machine that generates a request to fetch operand data. This request is sent to the request arbitration unit 811. The request arbitration unit 811 arbitrates between the request of the address generation unit 810 and the request of the MUV address generation unit 805 (FIG. 108), and inputs a request for winning ( MAG) is sent to the interface switch 252. Request arbitration unit 811 includes a state machine for handling requests. This is the FIFO count unit 814
To monitor the status of the FIFO and determine when the next request should be dispatched. The byte enable generation unit 812 receives the information of the IAG 810, and the byte enable pattern 8 for specifying a valid byte in each operand returned by the input interface switch 252.
16 is generated. The byte enable pattern is stored in the FIFO along with the associated operand data. MAG
When the request and the IAG request arrive at the same time, the request arbitration unit 8
11 processes the MAG request in preference to the IAG request.

In FIG. 108, the MUV address generator 805 operates in several different modes. The first of these modes is the JPEG (compression) mode. In this mode, input data for JPEG compression is supplied by the data operation unit 804, and the MUV buffer 250 is used as a double buffer. MUV R
The AM 250 address generation unit 805 includes a data operation unit 80
M suitable for storing the input data processed by
Generate the address of the UV buffer. MAG805 is
A read address for extracting color component data from the stored pixels is generated, and an operation is performed to form an 8 × 8 break for JPEG compression. MA
G805 also handles the case where the MCU partially overlaps the image. FIG. 110 shows an example of a padding operation performed by the MAG 805.

In ordinary pixel data, MAG8
05 is an MUV RAM 250 with four 8-bit RAMs
The four color components are stored in the same address in. To retrieve data from the same color channel simultaneously, the MCU data is barrel-shifted to the left before the MU
It is stored in the VRAM 250. The number of bytes shifted to the left of the data is determined by the lower two bits of the write address. For example, FIG. 111 shows that when subsampling is not required, 32-bit pixel data is MUV
2 shows a data structure arranged in the RAM 250. In the 3-channel or 4-channel interleaved JPEG mode, subsampling of input data may be selected. Multi-channel J with sub-sampling
In the PEG compression mode, MAG805 (FIG. 108)
Performs subsampling before 32-bit data is stored in the MUV RAM 250 for optimal performance of the JPEG encoder. Of the first four input pixels, only the first and fourth channels stored in MUV RAM 250 contain useful data. The data of the second and third channels is sub-sampled and stored in a register of the pixel organizer 246. In the next four input pixels, the second
And the third channel is filled with sub-sampled data. FIG. 112 shows an example of an MCU data configuration in the multi-channel sub-sampling mode. The MAG treats all single-channel unpacked data exactly like multi-channel pixel data. M
An example of the single channel pack data read from the UV RAM is shown in FIG.

The input process sets the input MCU to M
While stored in UV RAM, the read process reads 8x8 blocks from MUV RAM. Generally, the blocks are generated by the MAG 805 for each of the four coefficients by sequentially reading data for each channel. In the pixel data and the unpacked input data, the stored data is organized as shown in FIG. Thus, to synthesize an 8 × 8 block of unsampled pixel data, the read process reads the data from the MUV RAM skewed. FIG. 114 illustrates an example of such a process. FIG. 114 shows a read sequence for four channel data, and it can be seen that the storage format of the MUV RAM 250 makes it easy to read multiple values simultaneously from the same channel.

In the color conversion mode, the MUV RAM 2
Numeral 50 is used as a cache for storing interval and fraction values, and MAG 805 functions as a control unit of the cache. MUV RAM250
Caches three color channel values. here,
Each color channel has 256 pairs of 4-bit intervals and fractional values. At each pixel output through the DMU, MAG 805 is used to obtain the values from MUV RAM 250. When this value is not available,
MAG 805 issues a memory read request to fetch the missing interval and fraction values. For effective use of bandwidth, instead of fetching only one entry per request, a method of fetching many entries is used.

For image transformation and convolution operations, the MU
The VRAM 250 stores the matrix coefficients of the MDP.
The MAG scans all matrix coefficients stored in the MUV RAM 250. At the beginning of the image transformation and convolution instructions, MAG 805 issues a request to the operand fetch, which causes the operand fetch to fetch the kernel description "header" (FIG. 94) and the first matrix coefficient of the bust request. .

FIG. 115 shows the MUV address generator (MAG) 805 of FIG. 108 in more detail. MAG
Reference numeral 805 includes an IBus request module 820 for multiplexing the IBus request.
2 generated. The request is sent to an operand fetch unit that is adapted to execute the request. Since the pixel organizer 246 operates in one of the image conversion mode and the color space conversion mode, no arbitration is required between the control units 821 and 822. The IBus request module 820 derives information including a bust address and a bust length necessary to generate a request to the operand fetch unit from the associated pixel organizer.

The JPEG controller 824 has two state machines, a JPEG write controller and a JPEG read controller, and is used in the JPEG mode. The two control units operate simultaneously and are synchronized with each other by using an internal register.
In the JPEG compression operation, the DMU outputs MCU data and stores it in the MUV RAM. The JPEG write control unit is responsible for horizontal padding and pixel subsampling control, and the JPEG read control unit is responsible for vertical padding. Horizontal padding is performed by stopping the DMU output, and vertical padding is performed by re-reading the already read 8 × 8 block.

The JPEG write control keeps track of the current position of the DCU and DMU output pixels in the source image and
The information is used to determine if U should be stopped. M
When the CU is written to the MUV RAM 250, J
The PEG write control sets or resets an internal register to indicate whether the MCU is at the right edge of the image or at the lowest edge of the image.
Based on the contents of the register, the JPEG read control unit determines whether vertical padding is necessary or the last MC of the image.
Judge whether you read up to U.

The JPEG write control unit tracks the DMU output data and converts the DMU output data to the MUV RA
Store it in M250. The control unit stores a current position of an input pixel using a register set. This information is used when stopping the DMU output and performing horizontal padding. When all the MCUs are written to the MUV RAM 250, the control unit stores the MCU information in the JPEG-RW
-Write to the IPC register so that it can be used by the JPEG read controller thereafter.

The control unit determines that the last MCU has the MUV R
After being written to AM 250, it enters SLEEP state and remains there until the current instruction is completed. The JPEG read control unit reads an 8 × 8 block from the MCU stored in the MUV RAM 250. In a multi-channel pixel, the control unit reads the MCU several times and extracts a different byte in each read from each pixel stored in the MUV RAM.

This control unit detects whether to perform vertical padding using information provided by JPEG-RW-IPC. Vertical padding is MUV RAM25
This is performed by reading the 8 bytes immediately before reading from 0 again. The image conversion control unit 821 reads the kernel descriptor from the IBus, and transmits the kernel header to the MDP 242. And po. The matrix coefficients are scanned the number of times specified by the len register. In image conversion and convolution instructions, all data output by PO 246 is to be fetched directly from IBus and is not passed on to the DMU.

First fetched immediately after kernel header
The first eight bits of the matrix coefficients represent the number of remaining matrix coefficients to fetch. Kernel header is not modified directly M
Passed to the DP, but the matrix coefficients are sign expanded before being passed to the MDP. The pixel subsampler 825 is
It comprises two identical channel subsamplers, each operating on one byte of the input word. When the associated configuration register has not been activated, the pixel subsampler copies its input directly to its output. On the other hand, when the configuration register is activated, the subsampler subsamples the input data by averaging or decimating the input data.

The MUV multiplex module 826 selects MUV read and write signals from the currently active control. The internal multiplexing unit selects the read address output via various control units using the MUV RAM 250. The MUV RAM write address is stored in an 8-bit register of the MUV multiplex module. MU
The control unit using the V RAM 250 is the next MUV RAM
Control for determining the address is performed, and the write address register is loaded.

The MUV effective access module 827 is used by the color space conversion control unit, and the interval and the fraction value of the current pixel output by the data operation unit are set to the MUV.
Determine if it is available in RAM 250. When one or more color channels are missing, the MUV enabled access module 827 may assign the associated address to the IBus
Communicate to request module 820 to load interval and fraction values in burst mode. When a cache miss is serviced, the MUV enabled access module 827
Sets an internal valid bit that represents the set of interval and fraction values fetched so far.

The copy module 829 copies the input data the number of times determined by the internal pixel register. The input stream will be stopped while the duplication module is copying the current input word. The PBus interface module 830 includes the pixel organizer 24
6 to the main data path 242 and the JPEG encoder 241
Used to retime to or vice versa. Finally, the MAG controller 831 generates a signal for initiating various sub-modules and a signal for shutting down. Note that the MAG control unit 831 sends the input PB from the main data path 242 and the JPEG encoder 241.
Multiplexing is also performed on the us signal.

3.18.2 MUV Buffer In FIG. 2, the pixel organizer 246 is interrelated with the MUV buffer 250, as will be apparent from the above description. Reconfigurable MUV
Buffer 250 supports various processing modes, including simple look-up table mode (mode 0), multiple look-up table mode (mode 1), and JPEG mode (mode 2). In each mode, the buffer stores different types of data objects. For example, data words stored in a buffer,
Various lookup table values, single channel data, and multiple channel data are data objects. Typically,
Data objects have different sizes. Further, the data objects stored in the reconfigurable MUV buffer 250 can actually be accessed in various ways depending on the operating mode of the buffer.

Data objects are often encoded before being stored, in order to accommodate the various methods required to write back and store different types of data. The method used to code the data object is determined by the size of the data object, the format of the data object being represented, how the data object is written back from the buffer, and the configuration of the memory modules formed on the buffer. You.

FIG. 116 is a block diagram of the components used to implement the reconfigurable MUV buffer 250. The reconfigurable MUV buffer 250 includes an encoder 1290, a storage device 1293, a decoder 1291, and an address read / rotation signal generator 1292. When a data object is input to the input data stream 1295, the data object is encoded into internal data by the encoder 1290 and placed in the internal data stream 1296. The encoded data object is stored in storage device 1
293.

When decoding the stored data object, the encoded data is retrieved from the storage device by the encoded data output stream 1297. The encoded data on the encoded data output stream 1297 is decoded by the decoder 1291. The decrypted data object appears on output data stream 1298.

The write address 1035 to the storage device 1293 is given by the MAG 805 (FIG. 108). Write address 1299, 1300, 13
01 is also given by the MAG 805 (FIG. 108), and the address read / rotation signal generator 12
92 to the storage device 1293. Address reading / rotation signal generator 12
92 also includes an input / output rotation signal 1303,
1304 is generated for each of the encoder and the decoder. Write valid signals 1306 and 1307 are provided from an external source. The processing mode signal 1302 provided by the controller 801 (FIG. 108) includes an encoder 1290, a decoder 1291, an address read / rotation signal generator 1292, and a storage device 1.
293. The increment signal 1308 increments an internal counter in the address read / rotation signal generator, and may be used in the JPEG mode (mode 2).

When the reconfigurable MUV buffer 250 is in the simple look-up table mode (mode 0), the buffer 250 essentially behaves like a single mode memory module. A data object can be stored in or retrieved from a buffer in a manner essentially similar to accessing a memory module.

When the reconfigurable MUV buffer 250 is operating in the multiple look-up table mode (mode 1), the buffer 250 can be divided into a plurality of tables using up to three search tables stored in the storage device 1293. Divided. The lookup tables can be accessed simultaneously and independently. As an example, the values of the interval and fraction are stored in the storage device 129 in the multiple lookup table mode.
3 are stored in the input data stream 12
The lower 3 bytes of 95 are indexed. Each of the three bytes is a storage device 1293
Issued to an independent search table stored in.

When an image is JPEG compressed, the image is converted to an encoded data stream. Pixels are extracted from the original image in MCU format.
MCUs are read from left to right and top to bottom of the image.
Each MCU is recombined into a number of 8x8 blocks. Many 8x8 blocks are extracted from the MCU.
The MCU depends on several factors, such as the color components of the original image, the multi-channel JPEG mode, and the need for subsampling. The 8 × 8 block is then forward DCT (FDCT), quantized and entropy coded. In the case of JPEG compression, encoded data is read sequentially from a data stream. The data stream is subjected to entropy decoding, inverse quantization, and inverse DCT (IDCT). The output of the IDCT process is an 8 × 8 block. Multiple 8x8 blocks are integrated to reconstruct the MCU. When using JPEG compression, a large number of 8x8 blocks depends on the factors mentioned above. The reconfigurable MUV buffer 250 is also used when decomposing an MCU into a number of 8 × 8 blocks or reconstructing a number of 8 × 8 blocks into an MCU.

When the reconfigurable MUV buffer 250 is performing the JPEG mode processing, the input data stream 1295 to the buffer 250 has the JPEG compression processed pixels or JPE data.
Includes a single component performing G compression. The output data stream of the buffer 250 is JPE
Single channel data block or JP for G decompression processing
It contains the pixel data of the EG expansion process. This JP
In the example of EG compression, the input pixels are Y, U, V, O
Can be configured up to channels. When a specified number of pixels have been processed as a complete pixel block, the extraction of a single component data block can begin. Each single component data block is composed of data of the same channel pixels stored in the buffer. Thus, in this example, up to four single component data blocks can be extracted from one pixel data block. In this specific example, when the reconfigurable MUV buffer 250 is processing in the JPEG mode (mode 2) for JPEG compression, a large number of unit minimum codes (MCUs)
Can buffer 64 single or multiple channels of pixels each, and can extract multiple 64-byte long single channel component data blocks from each buffered MCU. For example, while buffer 1289 is in JPEG mode (mode 2) to perform JPEG decompression, the output data stream
It consists of output pixels with a maximum of four components Y, U, V, O. When the required number of completed single component data blocks have been written to the buffer, pixel data can be extracted. The bytes from the four single component data blocks corresponding to the different color components are retrieved as output pixels.

FIG. 117 shows the encoder 1290 shown in FIG.
FIG. For pixel block decompression, each of the input data objects is stored in the storage device 12.
Before being stored in 93, it is encoded by rotation in the byte direction (FIG. 129). The size of the rotation is determined by the input rotation control signal 1303. In this example, when the pixel data is a maximum of four bytes, 32-bit four-input one-output multiplexers 1320 and 1325 are used to select one of four possible input pixel rotations. For example, if four bytes of a pixel are (3,2,1,
0), the rotation of this pixel is (3,2,1,0) (0,
3, 2, 1) (1, 0, 3, 2) (2, 1, 0, 3). The four encoded bytes are output to the storage device 1290.

When the buffer is in a mode other than the JPEG mode (mode 2), for example, in a single lookup table mode (mode 0) or a multiple lookup table mode, rotation in the byte direction is not necessary.
Also, it cannot be performed on input data objects. The input data object is, in the latter case, disturbed by rotation by ignoring the input rotation control signal with no rotation value. This value 1323 is 2 input 1 output multiplexer 13
21 generates a control signal 1326 by selecting an input rotation control signal 1303 and a no-operation value 1323. The current processing mode 1302 is compared with the value of the pixel block decomposition mode to generate a multiplexer select signal. . 4-input, 1-output multiplexer 1320 controlled by signal 1326
Selects one of the four rotations of the input data object and encodes the encoded input data stream 1
Generate a potential data object encoded on 326.

FIG. 118 is a circuit diagram of a combinational circuit implementing a decoder 1291 for decoding the encoded output data stream 1297. Decoder 1321 operates in essentially the same way as an encoder. The decoder operates on data only when the data buffer is in JPEG mode (mode 2). The lower 32 bits of the encoded output data object in the lower encoded data stream 1297 are passed to the decoder. The data is decoded using byte-wise rotation in the opposite sense as rotating by encoder 1290. A 32-bit 4-input, 1-output multiplexer is used to select one of four possible types of encoded data. For example, if a 4-byte input pixel is labeled as (3,2,1,0), the rotation type of this pixel is (3,2,1,0)
2,1,0) (2,1,0,3) (1,0,3,2)
Four (0, 3, 2, 1) are possible. The output rotation control signal 1304 is used when the buffer is a pixel block decomposition node and when no operation values are ignored in other operation modes. The no operation value 1333 is 0. The two-input one-output multiplexer 1331 generates the signal 1334 by selecting the output rotation control signal 1304 and the no-operation value 1333. Current processing mode 13
02 is compared with the value of the pixel block decomposition mode to generate a multiplexer select signal 1332. A 4-input, 1-output multiplexer 1330 controlled by signal 1334 provides an encoded output data stream 1
297. Select the four types of rotation of the encoded output data object on the output data stream 1
298 on the output data.

In FIG. 116, the method of generating the internal read address used in the circuit is based on the processing mode 1302 of the reconfigurable MUV buffer 250.
Selected by. In the single lookup table mode (mode 0) and the multiple lookup table mode (mode 1), the read address is the external read address 1.
MAG805 in the form of 299, 1300, 1301 (FIG. 1)
08). In the simple lookup table mode (mode 0), the memory modules 1380, 1381, 1382, 1 are stored on the storage device 1293.
383, 1384 and 1385 (FIG. 121) are processed together. The memory modules 1380 to 1385 (FIG. 12)
The write address and the read address given in 1) are essentially the same. That is, the storage device 12
93 requires only one read address and one write address to be supplied to the external circuit, and these addresses are stored in the memory module 1380 as empty 1385 (FIG. 12).
Use internal logic to distribute to 1). In mode 0, the read address is given by the external address 1299 (FIG. 116) and is distributed to the internal address 1348 (FIG. 121) essentially unchanged. External read addresses 1349, 1350, 1351 (FIG. 12)
1) is not used in mode 0. The write address is given by the external write address 1305 (FIG. 116), and each memory module 1380 is essentially unchanged.
To 1385 (FIG. 121).

Here, the configuration of a three lookup table in the multiple lookup table mode (mode 1) is shown. When three tables are accessed independently,
The encoded input data is 1380 to 1385 (FIG. 1).
All memories up to 21) are also written to the joule at the same time, thus requiring one index for each of the three tables. Memory modules 1380 to 13
The three indices to 85 (FIG. 212), the read address, are provided by the storage device 1293. These read addresses are distributed to the appropriate memory modules 1380 to 1385 using internal logic. In essentially the same manner as in single look-up table mode, an externally applied write address is connected to each memory module address from 1308 to 1385 without substantial change.
As a result, in the multiple lookup table mode (mode 1), the external read addresses 1299, 1300, 1
311 is an internal read address 1348, 1349, 1
350 respectively. Internal read address 1
352 is not used in mode 1. An internal address generation method used in the JPEG mode (mode 2) is different from the above-described method.

FIG. 119 is a circuit diagram of a combination circuit for mounting a read address and rotation signal generation circuit 1292 for a reconfigurable data buffer in the JPEG mode (mode 2) for performing JPEG compression. In the JPEG mode (mode 2), the signal generator 1292
40 and the output of the data byte counter 1341 are used to calculate the internal read address of the memory module including the storage device 1293. The component block counter 1340 generates the number of component blocks extracted from the pixel data blocks stored in the storage device. The number of blocks is given by multiplying the output of the data byte counter 1341 by four. Specifically, the internal read addresses 1348 and 134 in the pixel block decomposition mode
9, 1350 and 1351 are calculated as follows. The component block counter has an offset value of 1343,
Output data byte counter 1341 is used to generate base read address 1354, and is used to calculate 1344, 1345, 1347.
The offset value 1343 is the base read address 135
4 is added to the internal read address 1348 (or 1349, 1350, 135).
1). The offset values of the memory modules generally take different values for simultaneous reading performed by multiple memory modules, but are essentially the same in the extraction of component blocks. The same applies to the base address 1354 used to calculate the four internal read addresses in the pixel data block decomposition mode. The increment signal 1308 is used as an increment signal of the component byte counter. The counter is incremented for each successful read. The component block counter increment signal 1356 is used to increment the component block counter 1340 after a data block for single calibration has been successfully retrieved from the buffer.

The output rotation control signal 1304 (FIG. 116) is derived from the output of the component block counter and the output of the output data byte counter, and is essentially the same as the generation of the internal address. The output of the component block counter is used to calculate a rotation offset 1347. The output rotation control signal 1304 is a rotation offset 135
5 and the base least significant bit of the sum of the base read address 1354. The input rotation control signal is provided by the least significant two bits of the external write address 1305 as in the example of the address and rotation control signal generator.

FIG. 120 is another address generator 1292 used to reconstruct multi-channel pixel data from single component data stored in the reconfigurable MUV buffer 250. In this case, the buffer is JPE for JPEG decompression.
The mode becomes the G mode (mode 2). In this case, the single component data block is stored in the buffer, and the pixel data block is retrieved from the buffer. In this example, the write address to the memory module is given by the external write address 1305 without substantial change. Single component blocks are stored in contiguous memory. Input rotation control signal 1 of this example
303 is simply set by the least significant two bits of the write address. Pixel counter 1360 is used to keep track of the number of pixels extracted from a single component block stored in the buffer. The output of the pixel counter is read address 13
48, 1349, 1350, 1351 and an output rotation control signal 1304.
Generally, the read address is the storage device 129
3 is different for each module.
In this example, the read address is a single component block index 1362, 1363, 1364, 1
365 or 1365 and byte index 1361
It consists of two parts. An offset is added to bits 3 and 4 of the output pixel counter to calculate a single component block index for a particular block. Offsets 1366, 1367, 1368,
1369 is different for each read address. Bit 2 to bit 0 of the pixel counter are used for the byte index 1361 of the read address. The read address is, as shown in FIG. 120, a single component block index 1362, 1363, 13
64, 1365 or 1365 and the result of combining byte index 1361. In this example, the output rotation control signal 1304 is generated by bits 4 and 3 of the output of the pixel counter without substantial change. The increment signal 1308 is used as a pixel counter increment signal for incrementing the pixel counter 1360. Pixel counter 1360 is incremented when a pixel is successfully removed from the buffer.

FIG. 121 shows the structure of the storage device 1293. Storage device 1293 is 1383,
It is possible to have three 4-bit wide memory modules 1384 and 1385 and three 8-bit wide memory modules 1380, 1381 and 1382. The memory module is a 36-bit word in single lookup table mode (mode 0), a 12 × 3 bit word in multiple lookup table mode (mode 1), JPE
Can be combined to store 32 bit pixels or 4x8 bit single component data in G mode (mode 2). Usually each memory module has an encoded input and output data stream (12
96 and 1297). For example, memory module 1380 has a data input port connected to bits 0 through 7 of encoded input data stream 1296 and a data output port connected to bits 0 through 7 of encoded output data stream 1297. . In this example, the write addresses of all memory modules are connected together and simultaneously share the same value. On the other hand, the read addresses 1386, 1387, 1388,
1390 and 1391 are read address generators 1292
Which generally take different values. In the example, a common write enable signal is used to issue a write enable signal to all 8-bit memory modules, and a second common write enable signal sends a write enable signal to all 4-bit memory modules. Used to get out.

FIG. 122 shows read addresses 1386, 1387, 1388, 1389, and 139 for accessing a memory module in the storage device 1293.
FIG. 3 is a circuit diagram of a combinational circuit for generating 0. Each encoded input data object is decomposed into sub-portions, and each sub-portion is stored in a separate memory module of the storage device. Thus, typically, the write addresses of all memory modules in all processing modes are essentially the same, and substantially no logic is required to calculate the write addresses of the memory modules. On the other hand, the read address usually differs for each processing, and also differs for each memory module in each processing mode. All bytes in the output data stream 1298 of the reconfigurable MUV buffer 250 are unit component data extracted from pixel data stored in the JPEG compressed JPEG mode (mode 2) buffer, or JPEG decompressed JPEG. Must contain pixel data stored in the mode buffer and extracted from the single component data. The request for output data is satisfied by generating four read addresses 1348, 1349, 1350, 1351 to the buffer. In the multiple look-up table mode (mode 1), up to three lookup tables are stored in the buffer, so up to three read addresses 1348, 1349, 1350 are needed to index the three lookup tables. . The read addresses of all memory modules are the same as in single look-up table mode (mode 0), and only read address 248 is used in this mode.
The control circuit example shown in FIG. 122 uses the processing mode signal of the buffer and up to four read addresses to calculate the read addresses 1386-1391 of each of the six memory modules constituting the storage device 1293. The read address generator 1292 has external address buses 1348 and 1349 as input signals,
Using the external read signals 1350 and 1351, the internal read addresses 1386, 1387, and 1 of the memory module constituting the storage device 1293 are used.
389, 1390 are generated.

FIG. 123 is a diagram showing how 20-bit matrix coefficients are stored in the buffer 250 when the buffer 250 is in the single look-up table mode. In this case, no encoding is normally performed on the data object on the cache when the data object is written to the reconfigurable MUV buffer. The matrix coefficients are stored in 8-bit memory modules 1380, 1381, 1382. Bits 7 to 0 of the matrix coefficient are stored in the memory module 1380 and bits 15 to 8
Are stored in the memory module 1381, and bits 19 to 16 are stored in the lower 4 bits of the memory module 1382. Data objects stored in a buffer as needed for the rest of the instruction are retrieved many times. In single lookup table mode,
The read and write addresses of all memory modules are essentially the same.

FIG. 124 is a diagram showing how a table entry is stored in the buffer in the multiple lookup table mode (mode 1). In this case, three search tables are stored in the buffer, and each search table has a 4-bit interval value and an 8-bit decimal value. Normally, the interval value is stored in a 4-bit memory module, and the decimal value is stored in an 8-bit memory module. In this case, the three search tables 1410, 1411 and 1412 are stored in the memory bank 13
80 and 1383, 1381 and 1384, 1382 and 13
85. The control signal 1306 which is not effective even in the separation past
And 1307 (FIG. 121) are stored in the storage device 129 without affecting the decimal value stored in the storage device.
3, an interval value can be written. A decimal value can be written in essentially the same way without affecting the interval value.

FIG. 125 shows how pixel data is written to the reconfigurable MUV buffer 250 in the JPEG mode (mode 2), which breaks up pixel data blocks into single element data blocks. It is. Storage device 12
93 is a memory module that is integrated and handled in the same manner as the 8-bit memory module, and memory modules 1380, 1381, 1382 including 1381 and 1384,
It is controlled as four 8-bit memory banks consisting of 1383 and 1384. Memory module 1385 is JP
It is not used in the EG mode (mode 2). The 32-bit encoded pixel is broken down into four bytes, each stored in a different 8-bit memory module.

FIG. 126 shows how a single component data block is stored in storage device 1293 in the single component mode. The storage device 1293 is a memory module integrated and handled in the same way as an 8-bit memory module, and memory modules 1380, 1381, 1382, 1383, 1384 including 1381 and 1384
As four 8-bit memory banks. The memory module 1385 is not used in the JPEG mode (mode 2). The 32-bit encoded pixel is broken down into 4 bytes, each with a different 8 bytes.
Bits are stored in the memory module. In this case, a single component block consists of 64 bytes. When a single component block is written to the sub-buffer, a different amount of byte rotation is applied to each. 32-bit encoded pixel data is retrieved by reading different single component data blocks in the buffer.

For more details on how to manage the reconfigurable data buffer 250, see the section on the pixel organizer. In the above example, it was shown that the reconfigurable data buffer is used for processing data related to different instructions. A reconfigurable data buffer with three processing modes has been identified. Different address generation techniques are required in each of the buffer processing modes. The single look-up table mode (mode 0) is used to store matrix coefficients in a buffer in image conversion. The multiple look-up table mode (mode 1) is used to buffer multiple interval and fraction lookup tables in a multi-channel color space conversion (CSC). The JPEG mode (mode 2) is used for decomposing MCU data into 8 × 8 single component blocks or recomposing 8 × 8 single component blocks into MCUs in JPEG compression and JPEG expansion.

3.18.3 Result Organizer The MUV buffer 250 is also used in the result organizer 249. The result organizer 249 buffers and formats the stream of the main data path 242 or the JPEG coder 241. The result organizer 249 also compresses the result data described in FIG.
Also related to decompression, denormalization, byte lane swap, and reorganization. Further, the result organizer 249 includes an external interface controller 238, a local memory controller 236, and a peripheral interface controller 237.
In response to the request, transfer the result.

In the JPEG decompression mode, the result organizer 249 stores the MUV RAM 250 in the JPEG coder 24.
9 to double buffer the image data. The double buffer uses the data of the JPEG coder 241 written in half of the MUVRAM 250 to perform JPEG
In the case of decompression, when the image data written in the other half at the same time is output to the designated storage location, the performance can be improved.

The 1, 3 and 4 channel image data are 8 × 8 including 8-bit components from the same channel.
While performing JPEG decompression in block form, it is passed to the result organizer 249. The result organizer stores these blocks in the specified order in the MUVRAM 250, and for multi-channel interleaved images,
The mesh of the channel when data is read from the MUVRAM 250 is stored. For example, in a 3-channel JPEG compression by YUV, a JPEG coder 24
1 outputs three 8 × 8 blocks in the order of Y first, then U, and finally V. The meshing is performed by extracting each block or one component, and constructing the pixels in (YUVX) form. Where X
Is an unused channel. Byte swapping occurs when output channel swapping becomes necessary. The result organizer also needs to perform the necessary sub-sampling for reconstruction of the chroma data of the decompressed output data. This implies that each program channel is repeated to generate.

Returning to FIG. 127, details of the result organizer 249 of FIG. 2 are shown. Result Organizer 24
9 is based around a normal standard CBus interface 840 that contains a register file of registers that are set for the process. The processing of the result organizer 249 is similar to that of the pixel organizer 249, except that a reverse data operation is performed. The data operation unit 842 performs byte lane swapping, component assignment, component release, and denormalization on the MUV address generator 80.
5 for the data generated. The executed processing is described above with reference to FIG. 42, and processing is performed according to various fields set in the internal registers. The FIFO queue 843 stores the output data in the RB
Buffering is performed before output using the us control unit 844. The RBus control unit 844 includes an address decoder and an address generator. The address for the storage module is stored in an internal register in addition to the data of the required number of output bytes. Further, the internal RO_C
The UT register determines how many output bytes are missing before being sent onto the output bus byte stream. In addition, the RO_LMT register determines the maximum number of data items to be output using the next data after the output restriction has been suspended. The MAG 805 generates an address of the MUVRAM 250 at the time of JPEG decompression. MUV
RAM 250 is used to double-buffer the output from the JPEG coder. The MAG 805 is an MUVRAM 25 depending on an internal configuration register.
A mesh of the components at 0 is performed, and a single channel, three channels, and four channels of pixels are output. Since byte lane swapping is required before storing the pixel data in the proper location, the MUVRA
The data obtained from M250 is passed through a data manipulation unit. When the result organizer 249 is not in the JPEG mode, the MAG 805 simply sends the data of the PBus receiver 845 directly to the data operation unit 842.

3.18.4 Operand Organizer B
2 and C. Returning again to FIG. 2, two independent operand organizers 247 and 248
0 and a function to transfer data to the JPEG coder 241 or the main data path 242. Operand organizers 247 and 248 operate in various modes. (A) The idle mode in which the operand organizer responds only to a CBus request. (B) The direct mode when the data of the current instruction is stored in the internal register of the operand register. (C) The sequential address and data cache controller 240 Sequential mode to generate data when the buffer is full.

The processing mode of the multiple main data paths 242 requires at least one of the operand organizers to be in the sequential mode. These modes, including compositing, in operand organizer B247 are required for buffered pixels that are composited with other images. Operand organizer C24
Reference numeral 8 is used in a combining process for attenuating the value of each data channel. In the halftone mode, the operand organizer B247 buffers 8-bit matrix coefficients, and in the hierarchical image format decomposition mode, the operand organizer B247 buffers both the vertical interpolation and the residual fusion instruction data. (D) In the steady mode, operand organizer B assembles a single internal data word and repeats that word the number of times specified by the internal register. (E) In the tile mode, the operand organizer B buffers data constituting a pixel tile. (F) In the random mode, the operand organizer directly transfers the address of the MDP 242 or the JPEG coder 241 to the data cache controller.

The internal length register determines the number of items generated individually by the operand organizers 247 and 248 when processing in the sequential, tile, and steady mode. Each of the operand organizers 247, 248 holds the number of data items processed so far and stops when it reaches a value determined by an internal register. Each of the operand organizers is more reliable with respect to input data format using byte lane swapping, component substitution, compression / decompression / normalization functions. Requested processing is configured using internal registers. Further, each of the operand organizers 247 and 248 is configured to limit data items.

FIG. 128 shows a more detailed configuration of the operand organizers (247, 248).
Operand organizers 247 and 248 are standard C
It includes a register 850 that controls the Bus interface and the entire operand organizer. Further, the OBus control unit 851 is connected to the data cache controller, generates addresses in the sequential, tile, and steady modes, generates control signals enabling communication of the OBus interface of the operand organizers 247 and 248, and stores past input streams. It controls the data manipulation unit that performs normalization, repetition, etc., which requires a state saved from the clock cycle. When the operand organizers 247 and 248 are in the sequential or tile mode, the OBus controller unit 851 sends a request for data to the data cache controller. At this time, the address is determined by the internal register.

[0359] Each operand organizer further includes a 36-bit wide FIFO buffer 852 used to buffer data from the data cache controller 240 in various modes of processing. The data operation unit 853 performs the same function as the function corresponding to the data operation unit 804 of the pixel organizer 246.

The main data path / JPEG coder interface 854 distributes data and addresses exchanged between the main data path and the JPEG coder modules 242 and 241 in the normal processing mode. MDP /
The JC interface 854 is a data operation unit 85
3 from the main data path and to a process configured to repeat the data. In the case of the color conversion mode, the units 851 and 854 are bypassed to establish high-speed access of the color conversion table with the data cache controller 240.

3.18.5 Main Data Path Unit The feature of the following embodiment relates to an image processor which provides a low-cost computer architecture capable of performing a plurality of image processing operations at high speed. Further, the image processor aims to provide a flexible computer architecture that can be configured to perform image processing operations not originally defined. It is also an object of the image processor to provide a computer architecture that has a lot of the same logic and makes the design process simple and cheap.

The computer architecture includes a control register block, a decoding block, a data object processor, and flow control logic. The control register block stores all information related to the image processing operation. The decoding block decodes the information into constituent signals and constitutes an input data object interface. The input data object interface receives and stores data objects from outside. Then, these data objects are distributed to the data object processor. In some image processing operations, the input data object interface may generate the addresses of the data objects so that the source of these data objects can provide the correct data object. The data object processor performs an arithmetic operation on the received data object. Flow control logic controls the data object flow in the data object processing logic.

In particular, the data object processor
There can be several identical data object sub-processors, each processing a portion of the input data object. The data object subprocessor connects several identical multi-function arithmetic units that perform arithmetic operations on the relevant part of the data object, post-processing logic that processes output data objects, and multi-function arithmetic and post-processing units. Multiplexing logic. The multi-function arithmetic unit has a storage device for calculated data objects. This storage is enabled or disabled by the flow control logic. The multi-function arithmetic unit and the multiplexing logic are configured by configuration signals generated by the decoding logic.

Note that configuration signals from the decoding logic can be changed by an external programming agent. Through this mechanism, any multi-function block and multiplexing logic can be individually configured by an external programming agent and configure the image processor to perform image processing operations not previously defined. to enable. These and other features of embodiments of the present invention are described in detail below.

In FIG. 2, as described above, the main data path section 242 performs all data manipulation operations and instructions other than JPEG data encoding. These instructions include composition, color space conversion, image conversion, convolution, matrix multiplication,
Includes halftoning, memory duplication, and decompression of the hierarchical image format. The main data path 242 includes the pixel organizer 246 and the operand organizer 2
47 and 248, receive the pixel and operand data and send the result output to the result organizer 249.

FIG. 129 is a block diagram of the main data path unit 242. The main data path unit 242 is a general-purpose image processor, and includes an input interface 1460, an image data processor 1462, and an instruction word register 146.
4. Instruction word decoder 1468, control signal register 14
70, register file 1472, and ROM 14
75.

The instruction control unit 235 transfers the instruction word to the instruction word register 1464 via the bus 1454.
Each command word contains information such as the type of image processing operation to be performed and plugs for selecting various options of the image processing operation. The instruction word is bus 1465
Through to the instruction word decoder 1468. Thus, the instruction control unit 235 can instruct the instruction word decoder 1468 to decode the instruction word. Upon receiving the instruction, instruction decoder 1468 decodes the instruction word into a control signal. These control signals are then carried via bus 1469 to control signal register 1470. Then, the output of the control signal register is
It is connected to an input interface 1460 and an image data processor 1462 via a line 71.

In order to make the main data path unit 242 more flexible, the instruction control unit 235 can write directly to the control signal register 1470. As a result, anyone who is familiar with the structure of the main data path unit 242 can perform a detailed configuration of the main data path unit 242, and the main data path unit 242 can perform image processing operations not described in the instruction word. You can do it.

If not all the information necessary to execute a desired image processing operation can be stored in the instruction word, the instruction control unit 235 stores all the information that cannot be stored in some of the register files 1472. Can be written to the register. This information is transmitted to the input interface 1460 and the image data processor 1462 via the bus 1473. In some image processing operations, the input interface 1460 may update the contents of the selected register in the register file 1472 to reflect the current state of the main data path unit 242. When a problem occurs when performing an image processing operation, the instruction control unit 235 can easily find the problem using the above-described features.

When decoding of the instruction word is completed and the desired control signal is loaded into the control signal register, the instruction control unit 235 may instruct the main data path unit 242 to start execution of the desired image processing operation. it can. Upon receiving this instruction, input interface 1460 connects to bus 145.
Start receiving data objects from 1. The input interface 1460 starts receiving operand data from the operand bus 1452 or the operand bus 1453 depending on the type of image processing operation to be performed, or generates an address of the operand data to generate the operand bus 1452 or the operand bus. Begin receiving operand data from 1453. Input interface 1460 stores and rearranges input data according to the output of control signal register 1470. When performing calculations such as affine image transformation operations and convolution operations, input interface 1460 connects to buses 1452 and
It also generates the coordinates to be fetched via 53.

The image data processor 1462 performs a main arithmetic operation on the data objects re-arranged by the input interface 1460. Image processor 1462 performs interpolation between two data objects with a predetermined interpolation factor, multiplies the two data objects, and divides the result by 255, normal multiplication and addition for the two data objects, data Performs operations such as truncation of the fractional part of the object with various precisions, clamping to reduce the overflow of the data object to a certain maximum value, and the underflow of the data object to a certain minimum value, scaling and clamping of the data object. be able to. The control signal on the bus 1471 controls which of the arithmetic operations is performed on the data object, the order of the operations, and the like.

The ROM 1475 has a dividend of 255 / x truncated in 8.8 format, where x is a number from 0 to 255. ROM 1475
Is input interface 1 via bus 1476
460 and the image data processor 1462. ROM 1475 is used to generate short length blends, multiply data objects by 255, and divide the result by other data objects.

The number of operand buses, for example 1452, is 2
, But sufficient for most image processing operations. FIG. 130 shows the input interface 1460 in more detail. The input interface 1460 includes a data object interface section 1480, operand interface sections 1482 and 1484, an address generation state machine 1486, and a blend generation state machine 148.
8, matrix multiplication state machine 1490, interpolation state machine 1494, data synchronization section 1500, arithmetic section 1496, other registers 14
98 and data distribution logic 1505.

Data object interface unit 1
480 and operand interface units 1482 and 1484 receive data objects and operands from outside. Interface section 1482, 148
4 is constituted by a control signal from the control bus 1515. Interface units 1482, 1484
Has a data register containing the data object / operand just received, and both output a VALID signal when the data register is valid. Outputs of the data registers of the interface units 1482 and 1484 are connected to the data bus 1505. VALI of interface unit 1482, 1484
The D signal is connected to the flow bus 1510. When configured to fetch operands, the operand interface units 1482 and 1484 allow the arithmetic unit 14
It receives the address from N. 96, the matrix multiplication state unit 1490, and the output of the data register of the data object interface unit 1480, and selects a necessary address according to the control signal from the control bus 1515.
In some cases, particularly when there is no need to receive and store data from outside, the operand interface unit 14
82 and 1484 are stored in the data object interface unit 1480 or the arithmetic unit 149.
6 may be configured to store data from the output of the data register.

The address generation state unit 1486 is used by the arithmetic unit 14 in the affine image conversion operation and the convolution operation.
Control 96 calculates the next coordinate of the source image to be accessed. The address generation state unit 1486 waits for the START signal on the control bus 1515 to be set.
When the START signal of the control bus 1515 is set, the address generation state unit 1486 releases the STALL signal to the data object interface unit 1480 and waits for the arrival of the data object. In addition,
Address generation state machine 1486 is an address generation state machine 1
The counter is set to be equal to the number of kernel descriptor data objects that need to be fetched. The output of the counter is decoded and becomes an enable signal for the data register of the operand interface units 1482 and 1484 and the other register 1498. Data object interface unit 148
When the VALID signal is asserted from zero, the address generation state machine 1486 will decrement the counter and the next portion of the data object will be latched into a different register.

When the counter reaches zero, address generation state machine 1486 causes operand interface 1484 to operate.
And instructs the operand interface unit 1482 to start fetching the index table value and the pixel from. The address generation state unit 1486 loads two counters each having the number of rows and the number of columns.
At every clock edge and when not stopped by a STALL signal, such as from the operand interface 1482, the counter is decremented to output the remaining rows and columns. Then, the arithmetic unit 1496 calculates the next coordinate to be fetched. When both counters reach zero, the counters reload the row and column numbers and the arithmetic unit 1
496 is configured to look for the upper left corner of the next matrix.

If interpolation is used to determine the true value of a pixel, address generation state 1486 reduces the number of rows and columns every two clock cycles.
This is performed using a one-bit counter, the output of which is used as an enable for the row and column counters. After the matrix has been scanned once, the state machine sends a signal that decrements the count of the length counter. When the counter has reached 1 and the last index table address has been sent to the operand interface 1482, the state machine issues a final signal and resets the start bit.

[0378] The blend generation state unit 1488 includes the arithmetic unit 1
Control 496 to 0 to 255 for blend length
Generate a sequence up to This sequence is used as an interpolation factor for interpolating between the blend start value and the blend end value. The blend creation state machine 1488 determines which mode (jump mode or step mode) should be executed. If the blend length is less than 256, the jump mode is used; otherwise, the step mode is used.

The blend generation state unit 1488 performs the following calculation, and stores the result in the register (reg0, reg1,
reg2). If the brand ramp is in step mode with a predetermined length, 511-length is reg0 (24 bits) and 512-2 * length is reg
1 (24 bits) and end-start is reg2
(4 × 9 bits). If the ramp is in jump mode, 0 to reg0 (24 bits), 255 / (length-1) to reg1 (24 bits), and end-start to reg2 (4 × 9 bits), respectively Latch.

In the step mode, the following processing is executed in each cycle. When reg0> 0, reg1 is added to reg0, and the result is stored in reg0. Another incrementer could be enabled, in which case the output would be incremented by one. When reg0 ≦ 0, 510 is added to reg0, and the result is stored in reg0. The incrementer is not increased. The output of the incrementer is a ramp value.

In the jump mode, the following processing is executed in each cycle. Add reg1 to reg0. The output of the addition is 24 bits and is output in a fixed point format of 16.8. The sum output is re
Store it in g0. If the first bit of the fraction result is 1, the integer part is increased. The lower 8 bits of the integer part of the incrementer are the ramp value. This ramp value, ie, re
The output of g2 and the blend start value are sent to the image data processor 1462 to generate a ramp.

A matrix multiplication state machine 1490 performs a linear color space conversion on an input data object using a conversion matrix. The transformation matrix has 4 × 5 dimensions. The first to fourth columns are multiplied by the four channels of the data object, and the last column contains the constants to be added to the sum of the products. When the START signal from control bus 1515 is activated, the matrix multiply state machine operates as follows.

1) A line number to be fetched from the buses 1482 and 1484 for constant coefficients of the conversion matrix is generated. The other register 1498 is enabled so that the constant coefficient can be stored. 2) A 1-bit flip-flop is provided to generate line numbers to use as addresses when fetching half of the matrix from buses 1482 and 1484. In addition,
It also generates a "MAT_SEL" signal that selects from half of the data object what to multiply by half of the matrix.

3) When there is no data object input from the data object interface unit 1480, the processing ends. Interpolation state machine 1494 performs horizontal interpolation of data objects. In the horizontal interpolation, the main data path unit 242 receives a data object stream from the bus 1451 and interpolates between adjacent data objects. And
Output a stream of data objects that is twice or four times as long as the original stream. Since data objects can be packed into bytes or pixels, the interpolator 1494 performs different operations in each case to maximize throughput. Interpolation state machine 1494 operates as follows.

1) By generating the INT_SEL signal, the data distribution logic 1503 causes the input data objects to be reordered and to interpolate on the correct data object pair. 2) Generate an interpolation factor for interpolating between adjacent data object pairs.

3) Generate a STALL signal to prevent the data object interface 1480 from accepting data objects anymore. This is required because the output stream is longer than the input stream. The STALL signal is sent to the flow bus 1510. The arithmetic unit 1496 includes a circuit for performing arithmetic calculations, and is configured by a control signal of a control bus 1515. It is used only by two instructions: affine image transformation and blending in convolution and compositing.

In the affine image conversion and convolution operation, the arithmetic unit 1496 performs the following operation. 1) Calculate the next x and y coordinates. To calculate the x coordinate, the arithmetic unit 1496 adds the horizontal and vertical delta x components to the current x coordinate using an adder, or subtracts the horizontal and vertical delta x components from the current x coordinate using a subtractor. So that Arithmetic unit 1 to calculate y-coordinate
498 adds the horizontal or vertical delta y component to the current y coordinate using an adder, or subtracts the horizontal or vertical delta y component from the current y coordinate using a subtractor.

2) The y-coordinate is added to the index table offset to calculate an index table address. If you use interpolation to find the original value of a pixel,
The sum is further increased by 4 to find the index entry. 3) Add the x coordinate to the index table entry,
Find the address of the pixel.

4) Subtract 1 from the length count. In blend generation, the arithmetic unit 1496 operates as follows. 1) In the step mode, an internal variable of the ramp generation algorithm is calculated using a certain ramp adder. On the other hand, another adder is used to increase the ramp value when the interval variable is greater than zero.

2) In jump mode, only one adder is needed to add the jump value to the current ramp value. 3) In the jump mode, fractions are truncated. 4) At the beginning of ramp generation, subtract the brand start from the brand end.

5) Subtract 1 from the length count. The other register 1498 provides an extra storage space other than the data register in the data object interface unit 1480 and the operand interface units 1482 and 1484. Other register 1498
Is typically used to store internal variables or buffer past data objects from the data object interface 1480. The register 1498 is configured by a control signal of the control bus 1515.

[0392] The data synchronization section 1500 includes a control bus 151.
5 control signals. Data synchronization unit 150
0 provides the STALL signal to the data object interface 1480 and the operand interface 1482 and 1484,
If one interface part receives some data objects that other interfaces do not have,
Stop the interface until all of the other interfaces have received data.

Data distribution logic 1505 responds to control signals on control bus 1515, including the MAT_SEL signal from matrix multiplication state machine 1490 and the INT_SEL signal from interpolation state machine 1494, from data bus 1510 and register file 1472. The data objects are rearranged via the bus 1530. The rearranged data is output to bus 1461.

FIG. 131 shows the image data processor 1462 of FIG. 129 in more detail. The image data processor 1462 includes a pipeline control unit 1540 and a number of color channel processors 1545, 1550, and 155.
5 and 1560. All color channel processors have an input interface 1460 (FIG. 13).
Receive input from bus 1565 driven by 1). All channel processors and pipeline controller 1
540 is constituted by a control signal from a control signal register 1470 via a bus 1472. All color channel processors also receive input from register file 1472 and ROM 1475 of FIG.
It may be received via 80. The outputs of all the color channel processors and the pipeline control unit are grouped into a bus 1570, and the image data processor 1
462 to form an output 1455.

The pipeline control unit 1540 controls the flow of data objects of all color channel processors by enabling or disabling registers of all color channel processors. The pipeline control unit 1540 includes a register pipeline. The shape and length of the pipeline are
The configuration is the same as that of the pipeline of the pipeline control unit 1540 and the pipeline of the color channel processor. The pipeline control unit operates from the bus 1565 to V
Receive the ALID signal. Pipeline control unit 1540
Input VAL at each pipeline stage
If the ID signal is activated and the pipeline stage is not stopped, the pipeline stage activates the register enable signal for all color channel processors and latches the input VALID signal. The output of the latch, the VALID signal, then moves to the next pipeline stage. In this way, the movement of data objects in the pipeline is simulated and controlled without using data storage.

The color channel processors 1545 and 15
50, 1555, and 1560 perform the main arithmetic operations on the input data object, and each processor is responsible for one channel of the output data object.
In the preferred embodiment, the number of color channel processors is limited to four because most pixel data objects have a maximum of four channels.

Some of the color channel processors handle opacity channels of pixels. Although not shown in FIG. 131, the control bus 1
There is additional circuitry connected to 471, and the color channel processor translates control signals from control bus 1471 to correctly handle opaque channels. This is because in some image processing operations, the operation on the opaque channel is slightly different from the operation on the color channel.

FIG. 132 shows the color channel processor 1
545, 1550, 1555, and 1560 are shown in more detail (generally shown as 1600 in FIG. 132).
Each color channel processor 1545, 1550, 15
55 and 1560 are a processing block A 1610, a processing block B 1615, a big adder 1620, a fraction truncation unit 1625, and a clamp or wrapper 1630.
And an output multiplexing unit 1635. The color channel processor 1600 includes a control signal register 1470
Control signal from the pipeline control unit 1540 via the bus 1602, and an enable signal from the pipeline control unit 1540 to the bus 1604.
, The information from the register file 1472 via the bus 1605, other data objects from the color channel processor via the bus 1603, the data objects from the input interface 1460 via the bus 1601, Receive each.

The processing block A 1610 includes a bus 1601
Performs some arithmetic operations on the data objects from, and outputs the partially calculated data objects to bus 1611. The processing that the processing block A1610 should perform for the image processing operation will be described below. In the synthesis, the processing block A 1610 multiplies the data object from the data object bus 1451 by opacity, and sets a value between the blend start value and the blend end value as shown in FIG.
129, pre-multiply the operands from the operand bus 1452 in FIG. 129 or multiply the blend color by opacity. Then, the multiplication on the premultiplied operand or the blend color data is attenuated.

In general color space conversion, processing block A
1610 interpolates between the four color table values using the two fractional values from bus 1451 of FIG. In the affine image transformation and convolution operation, processing block A1610 pre-multiplies the color of the source pixel by opacity and interpolates between the same row of pixels using the current x-coordinate fraction.

In the linear color space conversion, processing block A
1610 pre-multiplies the color of the source pixel by the opacity and multiplies the pre-multiplied color data by a transformation matrix coefficient. In the horizontal interpolation and the vertical interpolation, the processing block A1
610 interpolates between two data objects.

At the residual margin, processing block A1610 adds two data objects. The processing block A1610 includes a number of multifunctional blocks 1
640 and a processing block A glue logic 1645. Multi-function block 1640 is configured by control signals and can perform one of the following functions.

The addition and subtraction are performed on the two data objects. Conveys one data object. Interpolate between two data objects by some interpolation factor. Pre-multiply colors by opacity. Multiply two data objects and multiply the product by a third data object.

Addition and subtraction are performed on two data objects, and the result is premultiplied by opacity. The registers of multifunction block 1640 are enabled or disabled by an enable signal from bus 1604 generated by pipeline control 1540 of FIG. Processing block A glue logic 1645 includes data objects from bus 1601 and bus 160
3 and the output of some multifunction blocks 1640 and sends them to the inputs of other selected multifunction blocks 1640. The processing block A glue logic 1645 is also configured by a control signal from the bus 1602.

The processing block B 1615 includes a bus 1601
Performs an arithmetic operation on the data object from the bus 1611 and the partially calculated data object from the bus 1611 and transfers the partially calculated data object to the bus 1
616. The processing performed by the processing block B1615 for the image processing operation will be described below. In composition with non-positive operators, processing block B 1615 multiplies the pre-processed data object from data object bus 1451 and the operand from operand bus 1452 by the composite multiplicand from bus 1603 and 8.8. Multiply the output of the ROM, which is the 255 / opacity value of the format, on the clamped / wrapped data object.

In a composition with a positive operator, processing block B1615 adds the two pre-processed data objects. Further, in the opaque channel, subtract 255 from the sum, multiply the difference by the offset, and divide the product by 255. In the general color space conversion, the processing block B1615
Interpolate between the four color table values using the two fractional values and process block A1610 using the remaining fractional values.
Interpolate between the partially interpolated color values from and the previous interpolation result.

In the affine image transformation and convolution operation, processing block B1615 interpolates between the partially interpolated pixels using the fractional part of the current y-coordinate and replaces the interpolated pixels with the subsample weight matrix. Multiply the coefficient. In the linear color space conversion, the processing block B16
15 pre-multiplies the color of the source pixel by the opacity and multiplies the pre-multiplied color by a transformation matrix coefficient.

The processing block B 1615 includes a number of multi-function blocks and a processing block B glue logic 1650. The multi-function block is a processing block A1610
, But in processing block B glue logic 1650, buses 1601, 1603, 161
Accept the data objects from 1,1631 and the output of the selected multi-function block and send them to the input of the selected multi-function block. The processing block B glue logic 1650 is also configured by a control signal from the bus 1602.

The big adder 1620 has the processing block A
1610 and some of the partial results from processing block B 1615. This is from the input interface 1640 via the bus 1601, from the processing block A 1610 via the bus 1611, from the processing block B 1615 via the bus 1616, and from the
The respective input is received from the register file 1472 via the interface 05 and the result connected to the bus 1621 is output. The big adder 1620 is also configured by a control signal of the bus 1602.

The big adder 1620 can have different configurations according to various image processing operations. The operation of the big adder 1620 in the predetermined image processing operation will be described below. In a composition with a non-positive operator,
Big adder 1620 sums the two partial products from processing block B 1615.

In a composition with a positive operator, when the offset enable is activated, the big adder 1620 subtracts the sum of the preprocessed data object with the offset from the opacity channel. In the affine image conversion / convolution operation, the big adder 1620 accumulates the product from the processing block B1615.

In the linear color space conversion, in the first cycle, the big adder adds two matrix coefficient / data object products and ordinary coefficients. In the second cycle, add the other two matrix coefficient / data object products to the sum of the previous cycle. The fraction truncation (rounding) unit 1625 is the bus 1
It receives the input from the big adder 1620 via 621 and truncates the output fraction. The number of bits representing the fractional part is obtained from the register file 1472 to the bus 1605.
Is displayed by the BP signal. The following table shows how to interpret the BP signal. The truncated output is the bus 162
6 is provided.

[0413] Fraction table

[0414]

[Table 27]

[0415] The fraction cutoff unit 1625 performs two operations other than fraction cutoff. 1) Determine if the truncated result is negative. 2) Determine if the absolute value of the truncated result is greater than 255. The clamp or wrapper 1630 receives input from the fractional truncation unit 1625 via the bus 1626, and performs the following operations in that order.

If the option to determine the absolute value of the truncated result is enabled, determine the absolute value. The underflow of the data object is clamped to a certain minimum value, and the overflow of the data object is clamped to a certain maximum value. The output multiplexing unit 1635 selects the final output from the output of the processing block B on the bus 1616 and the output of the clamp or wrapper on the bus 1631. Although some final processing is also performed on the data object, an operation performed for a predetermined image processing operation will be described below.

In the synthesis without the pre-multiplication with the non-positive operator, the multiplexing unit 1635 sets the
The 15 outputs are combined to form a data object without pre-multiplication. In pre-multiplication compositing with non-positive operators, multiplexer 1635 passes the output of clamp or wrapper 1630.

In a composition with a positive operator, multiplexer 1635 combines the several outputs of processing block B 1630 to form a data object result. In the general color space conversion, the multiplexing unit 1635 applies a translation / clamp function to an output data object.
In another operation, the multiplexer 1635 passes the output of the clamp or wrapper 1630.

FIG. 133 shows one such as 1640.
One multifunctional block is shown in more detail. The multi-function block 1640 includes a mode detection unit 1710, two addition operand logic units 1660 and 1670, three multiplexing logic units 1680, 1865, and 1690, a two-input addition unit 1675, and two addends. 2 input multiplication unit 1695
And a register 1705.

[0420] The mode detection unit 1710 includes a MODE signal 1711 from the control signal register 1470 shown in FIG.
It receives two SUB signals 1712 and a SWAP signal 1713 from the input interface 1460 of FIG. Mode detection section 1710 decodes these signals, and performs addition operand logic sections 1660 and 1670;
It generates control signals that are passed to multiplexing logic 1680, 1685, and 1690. The control signal configures the multi-function block 1640 to perform various operations. The multi-function block 1640 has eight modes.

1) Addition / subtraction mode: Input 1655 is added to input 1665 or subtracted from input 1665 in accordance with SUB signal 1712. Further, the SWAP signal 693
, The input can be swapped. 2) Bypass mode: Bypass input 1655 to output. 3) Interpolation mode: Using input 1675 as an interpolation factor,
Interpolate between inputs 1655 and 1665. The inputs 1655 and 1665 can be swapped according to the SWAP signal 1713.

4) Pre-multiply mode: multiply input 1655 by input 1675 and divide the result by 255. The output of the INC register 1708 is connected to bus 1 for correct results.
At 707, the next stage is told if the results of this stage should be increased. 5) Multiplication mode: multiply input 1655 by input 1675.

6) Addition / subtraction and pre-multiplication mode: input 1
665 to input 1655 or input 165
5 and multiply the result by the input 1675, and
Divide this product by 255. The output of the INC register 1708 tells the next stage if the result of this stage on bus 1707 should be incremented to get the correct result.

Addition operand logic units 1660 and 167
0 is used so that it can be subtracted by an adder.
If necessary, find the one's complement of the input. Adder 1
675 sums the outputs of add operand logic 1660 and 1670 on buses 1662 and 1672 and outputs the sum on bus 1677. Multiplexing logic 1680,1
685 and 1690 select the appropriate multiplicand and addend to perform the desired function. These are all configured by the control signal of the bus 1714 from the mode detection unit 1710.

The multiplication unit 1695 having two addends multiplies the input from the bus 1682 by the input from the bus 1677. The sum of the inputs from buses 1687 and 1692 is then added to the product. The adder 1700 includes a multiplication unit 169
The upper 8 bits of the output of the multiplication unit 1695 are added to the lower 8 bits of the output of 5. The carry of the adder 1700 is latched in the INC register 1701. INC register 170
1 is enabled by signal 1702. Register 1705 stores the product from multiplication section 1695. This is also enabled by signal 1702.

FIG. 134 is a block diagram of the synthesizing operation. This combining operation receives three input data streams. 1) Accumulated pixel data: In this accumulator model,
The result is derived from the same location where it was stored. 2) Composite operand: consists of color and opacity. Both color and opacity are flat, blended, pixel,
Or it could be a tile.

3) Attenuation: Attenuates operand data.
The attenuation can be a flat bitmap or a bytemap. Pixel data typically consists of four channels. The three channels form the color of the pixel. The remaining channel is the opacity of the pixel. Pixel data may or may not be pre-multiplied. When pixel data is pre-multiplied, each color channel is multiplied by opacity. Pre-multiplying pixels simplifies the formula for the compositing operation, so it is common for pixel data to be pre-multiplied before compositing with other pixels.

Table 1 shows the synthesis instructions executed in the preferred embodiment.
Shown in Each instruction operates on pre-multiplied data.
(Ac0, a0) is the pre-multiplied pixel color ac
And opacity a0, r is the "offset" value, wc () is the wrap / clamp operator, and the inverse operators of the over, in, out, and top operators in Table 1 are also implemented. The composite model has an accumulator on the left side.

Synthetic block 1760 in FIG. 134
Has three color sub-blocks and an opaque sub-block. Each color sub-block operates on one color channel and an opaque channel of the input pixel to obtain the color of the output pixel. The above operation is shown below in the form of pseudo code. PIXEL Composite (IN color A, color B: PIXEL; IN opacity A, opacity B: PIXEL; IN comp_op: COMPOSITE_OPERATOR) END IF; THEN X = 1 if IF comp_op is over, over, loado, or plus; THEN X = opacyB if ELSE IF comp_op is in, rin, atop, or rat op; ELSE IF comp_op is out, rout, or xor If there is, THEN X = not (opacityB); ELSE IF comp_op is loadzero, loadc, or loadco, THEN X = 0; END IF; IF comp_op is over, over, atop, ratop, or xor. THEN Y = not (opacity); ELSE IF comp_op is plus, loadc, or load co; and THEN Y = not (opacity); ELSE IF comp_op is plus, loadc, or load co; ELSE IF comp_op is in, rin, out, route, loadzero, or load THEN Y = 0; END IF; result = coloA * X + olorB * Y; RETURN result; for instruction 'load' and 'LOADO' has a different meaning to the opaque channel, or code differ in opaque sub-block.

Block 1765 in FIG. 134 clamps or wraps the output of block 1760. When block 1765 is configured to clamp, all values less than the minimum allowed are reduced to the minimum and all values greater than the maximum allowed are reduced to the maximum allowed.
When block 1765 is configured to swap,
Calculate the following formula.

((X-min) mod (max-mi)
n)) + min, where min and max mean the minimum and maximum values allowed for the color. The minimum and maximum values are 0
And 255 are desirable. Block 177 in FIG.
0 pre-multiplies the result from block 1765. This pre-multiplies the pixels by multiplying the pre-multiplied color value by 255 / o. Here, o means opacity after synthesis. The value of 255 / o is obtained from ROM in the synthesis engine. The values in the ROM are stored in 8.8 format, and fractions and fractions are rounded.
The result of the multiplication is stored in a 16.8 format. To generate the inverse pre-multiplied pixel, the result is 8
Rounded with bits.

[0432] The brand generation unit 1721 generates a brand of a specific length having a specific start value and a specific end value. This is performed over the following two stages. 1) Ramp generation 2) Interpolation In ramp generation, the synthesis engine generates a sequence that increases linearly from 0 to 255 over the length of the instruction. There are two types of ramp generation: a "jump" mode with a length less than 255 and a "step" mode with a length greater than 255. The mode is determined by the upper 24 bits of the length. In jump mode, the ramp value increment is at least one per clock cycle. In Step mode,
The increment of the ramp value is at most 1 for each clock cycle.

In the jump mode, the synthesis engine calculates 8.8 to obtain a step value of 255 / (length-1).
Format ROM is used. This value is applied to a 16-bit accumulator. The output of the accumulator is truncated at 8 bits to form a sequence. In step mode, the compositing engine uses an algorithm similar to Bresenham's drawing algorithm. The algorithm is shown below.

Void line draw (length: INTERGER) d = 511-length; incrE = 510; incrNE = 512-2 * length; ramp-0; for (i = 0; i (length; i ++) （ifd = 0 then d + = incrE; else {d + = incrNE; ramp ++; {}} Then, the following formula is used to generate a brand from the lamp.

Blend = ((end-start) × ramp / 255) + start 255 The truncation is performed for the division. The above equation requires two adders and a block to "pre-multiply" (for end-start) by the ramp of each channel. Another image processing that can be performed by the main data path unit 242 is a general color space conversion.
Generalized color space conversion (GCSC) uses piecewise trilinear interpolation to determine output color values. Preferably, a transformation from a three-dimensional input space to a one-dimensional or four-dimensional output space is performed.

In some cases, the accuracy of tri-linear interpolation at the edges of the color gamut is a problem. This problem is exacerbated in printing devices that are sensitive to near edges. GCSC to avoid this problem
Can be selectively calculated in the extended output color space and scaled and clamped within the appropriate range using the following equation:

[0437] Other image processing that the preferred embodiment can perform are image transformation and convolution operations. In image conversion, the source image is scaled, rotated, and skewed. In a convolution operation, pixels of a source image are sampled with a convolution matrix to generate a destination image. The following steps are required to generate a scan line in a target image.

1) The scan line of the target image as shown in FIG. 135 is inversely converted. This makes it possible to identify the pixels of the source image required to generate the scan lines of the destination image. 2) Decompress the necessary part of the source image. 3) Invert the horizontal and vertical subsampling distances and the starting x, y coordinates of the target image into the source image.

4) The above information is transmitted to the processing section, and necessary sub-sampling and interpolation are performed to obtain the pixels of the output image. Subsampling, interpolation, writing of destination pixels, etc. are performed by the preferred embodiment, and calculations of relevant parts in the source image, subsampling frequency to be used, etc. are performed by the host application.

FIG. 136 is a block diagram showing the steps necessary for calculating the target pixel value. FIG. 136 assumes that the required source image pixels are available. The final step in calculating the destination pixel is to sum all quadratic linearly interpolated subsamples from the source image. FIG. 137 is a block diagram of an image conversion engine derived by appropriate settings in the main data path unit 242. The image conversion engine 1830 includes an address generation unit 1831, a pre-multiplication unit 1832, and an interpolation unit 183.
3, an accumulating unit 1834, a truncating unit, a clamping unit, and a logical unit 1835 for calculating an absolute value.

The address generator 1831 generates the x and y axes of the source image required to form the result pixel. It also generates an address to determine an index offset from the input index table 1815 and the pixels of the image 1810. Address generator 18
31 reads the kernel descriptor before generating the x and y axes of the source image. There are two types of kernel descriptor formats, which are shown in FIG.
The kernel descriptors are: 1) the starting coordinates of the source image (unsigned fixed point, 2
4.24 precision). Position (0,0) is the upper left corner of the image.

2) Horizontal and vertical sub-sample deltas (2
3) A 3-bit bp field indicating the position of the binary point in the fixed-point matrix coefficients. FIG. 150 shows the definition and description of the bp field. 4) Accumulation matrix coefficients. It is of "variable" decimal precision with 20 binary positions (two's complement), the position of the binary point being implicitly defined by the bp field.

5) An rl field indicating the remaining number of words in the kernel descriptor. This value is the same as the value obtained by multiplying the number of rows by (the number of columns−1). In the short kernel descriptor, other parameters except the constant part of the starting coordinate of x have the following values. Fraction of start coordinates of x <-0, start coordinates of y <-0, horizontal delta <-1.0, vertical delta <-1.0. After the address generation unit 1831 is configured, the current coordinates are calculated. There are two ways to do this, depending on the dimensions of the subsample matrix. If the dimension of the subsample matrix is 1 × 1, the address generator 1831 adds a horizontal delta to the current coordinates until sufficient coordinates are obtained.

If the dimension of the subsample matrix is not 1 × 1, the address generator 1831 adds a horizontal delta to the current coordinates until one row of the matrix ends. Thereafter, the address generation unit 1831 adds a vertical delta to the current coordinates to obtain the coordinates of the next row. The address generator 1831 subtracts the horizontal delta from the current coordinates until one or more columns are completed to find the next coordinate. Thereafter, the address generator 1831 adds the vertical delta to the current coordinates and repeats this process. FIG.
The diagram at the top of 50 shows how to access the matrix. Using this structure, the matrix is scanned in a zigzag manner and the current x, y axes are calculated by this method, so that fewer registers are required. The accumulation matrix coefficients must be arranged in a similar order in the kernel descriptor.

After generating the current coordinates, the address generation unit 18
31 is to find the address of the index table,
The y-axis is added to the index table base address (if the source pixel is interpolated, the address generator 1831 also needs to find the next index table). The index table base address is (y +
0). After obtaining the index offset from the index table, the address generator 1831 adds it to the x coordinate. This sum is used to determine one pixel from the source image (two pixels if the source pixel is interpolated). If the source pixels are interpolated,
The address generator 1831 adds the x coordinate to the next index offset to obtain two or more pixels.

When obtaining coordinates for image conversion, a similar technique is used in the convolution operation. The only difference from the convolution operation is that the start coordinate of the matrix at the next output pixel is separated from the start coordinate of the matrix at the previous pixel by a horizontal delta. In the image transformation, the starting coordinates of the matrix at the next pixel are separated by a horizontal delta from the coordinates of the upper right pixel of the matrix at the previous output pixel.

In FIG. 139, the middle diagram shows the above difference. The pre-multiplier 1832 multiplies the pixel's color and opacity channels if necessary. Interpolator 1832 interpolates the source pixels to determine the true color of the required pixel. It takes two pixels from the source image memory, interpolates using the fractional part of the current x coordinate, and inputs the result to a register. Thereafter, two pixels in the next column of the source image memory are taken and similarly interpolated using a fraction of x. Thereafter, the interpolation unit 1833 uses the fractional part of the current y coordinate to interpolate this interpolated value with the previous interpolated value.

The accumulator 1834 performs two tasks. 1) Multiply the matrix coefficient by the pixel. 2) Output the value obtained by accumulating the above results for all matrices to the next stage. The initial value of the accumulating unit 1834 is initialized to 0 or a specific value according to the channel.

Block 1835 truncates the output of accumulator 1834 and limits underflow or overflow values to maximum or minimum values, if necessary. And
If necessary, the absolute value of the output may be obtained. The position of the binary point in the output of the accumulator is specified by the bp field of the kernel descriptor. The bp field indicates the number of bits to be discarded in the accumulation result. This is shown in the lower diagram in FIG. This accumulated value is treated as a signed two's complement.

Another image processing operation that can be performed by the main data path unit 242 is matrix multiplication. Matrix multiplication is used for color space conversion when there is an affine relationship between two spaces. This is a difference from general color space conversion (based on cubic linear interpolation). The result of the matrix multiplication is defined by the following equation:

[0451]

(Equation 7)

Where ri is the result pixel and ai
Is the A operand pixel. Matrix size is 5 columns 4
Must be a line. FIG. 140 shows the main data path unit 2
42 is a block diagram of a multiply-adder that performs matrix multiplication at 42. FIG. It comprises a multiplier for multiplying the pixel channel by a matrix coefficient, an adder for summing the results, and a logic for clamping an output value and obtaining an absolute value as necessary.

It takes two clock cycles to complete the matrix multiplication. A multiplexing unit is set for each cycle so that data of the multiplying unit and the adding unit are correctly selected. In the 0th cycle, the least significant two bytes of the pixel are selected by the multiplexers 1851 and 1852.
The coefficient is then multiplied by the matrix coefficient in the two columns on the left side of the matrix, ie, line 0 in the cache.

In the first cycle, the upper two bytes of the pixel are selected by the top multiplexer. The coefficients are then multiplied by the two columns on the right side of the matrix. The result of the multiplication is added 1854 to the result of the last cycle. The sum in the adder is truncated to 8 bits 1855.
The “operand logic unit” 1856 rearranges the output of the multiplication unit so that the input of the addition unit 1854 becomes four. This performs a rearrangement to allow addition to the result of the multiplier and outputs the correct product of the 24-bit coefficients and the 8-bit pixel components.

[0455] The "AC logic unit" 1855 truncates the least significant 12 bits of the output of the adding unit, and obtains the absolute value of the truncated result according to the setting. The result is then clamped or wrapped, depending on the settings. When the “AC logic” is set to clamp, all values below 0 are 0
In addition, all values 255 and above are suppressed to 255. "A
When the "C logic part" is set to wrap, the lower 8 bits of the constant part are output.

The main data path section 242 can be set to perform image processing other than the above. A computer architecture capable of reducing costs by design reuse and performing various image processing operations quickly will be described below. It should be noted that since the computer architecture is flexible, even if an external programming agent is used to the architecture, the computer can be configured to execute image processing operations that were not originally predicted. Also, since the core of the design mainly consists of several multifunctional blocks, the design effort can be significantly reduced.

3.18.6 Data Cache Control Unit and Cache The data cache control unit 240
4 KB read data cache 23
0 is provided. The data cache 230 is arranged as a direct mapped RAM cache, and any line of the same length in the external memory can be directly mapped to the same line of the same length in the cache memory 230 (FIG. 2). . This line in a cache memory is commonly called a cache line, and the cache memory is made up of many such cache lines.

The data cache control unit 240 services data requests from the two operand organizers 247 and 248. First, it is confirmed whether data exists in the cache 230. Otherwise, data is fetched from external memory. The data cache controller 240 has a programmable address generator, which enables the data cache controller 240 to operate in several different addressing modes. There is also a special addressing mode in which the address of the requested data is made by the data cache control unit 240. In this mode, data of up to eight words (256 bits) can be sent to the operation organizers 247 and 248 simultaneously.

The cache RAM consists of eight independently addressable memory banks (addressed by different line addresses). Required for some special addressing modes where the data from each bank is united into 256 bits. This arrangement can service up to eight 32-bit requests simultaneously if they come from different banks.

The cache operates in the following modes, which will be described in detail below. If necessary, all caches can be automatically populated. 1. Normal mode 2. 2. Single output general color space conversion mode 3. Multi-output general color space conversion mode JPEG encoding mode 5. Low-speed JPEG decoding mode 6. Matrix multiplication mode 7. Disable mode Invalidation mode FIG. 141 shows the data cache control unit 24 in FIG.
0 shows the address, data, control flow, and data cache 230.

The data cache 230 has the direct map cache described above. The data cache controller 240 includes a tag memory 1872 having a tag entry for each cache line, with the tag entry having the most significant external memory address to which the cache line is currently mapped. It also has a line valid state memory 1873 indicating whether the current cache line is valid. The initial state of all cache lines is invalid.

The data cache control unit 240 can simultaneously service data requests from the operand organizer C247 (FIG. 2) and the operand organizer C248 (FIG. 2) through the operand bus interface.
In operation, the operand organizers 247, 248
Either or both of FIG. 2 provides an index 1874 and issues a data request signal 1876. The address generator 1881 generates one or more complete external addresses 1877 for the index 1874. The cache control unit 1878 stores the tag memory 18 with respect to the tag address of the generated address 1877.
Determine whether the requested data is in cache 230 by examining 72 and examining line valid state memory 1873 to see if the associated cache line is valid. When the requested data is present in the cache memory 230, an acknowledgment (response) signal 1879 is sent along with the requested data 1880 to the associated operation organizer 247,248. When the requested data does not exist in the cache memory 230, the requested data 1870 is input through the input bus interface 1871 and the input interface switch 252 (FIG. 2).
Is fetched from external memory. Data 1870 is fetched by outputting request signal 1882 and providing the address 1877 at which requested data 1870 was generated. The acknowledgment signal 1883 and the requested data 1870 are stored in the cache controller 1878, respectively.
And sent to the cache memory 230. The cache line associated with that cache memory 230 is then updated with the new data 1870. The tag address of the new cache line is also written to the tag memory 1872, and the line valid state 1873 for the new cache line is activated. Acknowledge signal 187
9 is sent along with data 1870 to the associated operand organizer 247 or 248 (FIG. 2).

In FIG. 142, the data cache 23
0 shows a memory configuration. The data cache 230 has 128 cache lines C0,. . . , C127 as a direct map cache. The cache RAM has separate addressable memory banks B0,. . . , B7
Each memory bank has 128 32-bit bank lines, and each cache line Ci has 8 banks.
The two memory banks B0,. . . 8 equivalent in B7
One bank line B0i,. . . , B7i.

FIG. 143 shows the configuration of the generated external memory address. The generated address is a 32-bit word consisting of a 20-bit tag address, a 7-bit line address, a 3-bit bank address, and a 2-bit byte address. The 20-bit tag address is used to compare the tag address with the tag stored in tag memory 1872. The 7-bit line address is used for the address of the associated cache line in cache memory 1870. The 3-bit bank address is used for the address of the memory bank associated with the memory of the cache memory 1870. The 2-bit byte address is used to address the associated byte of the 32-bit bank line.

FIG. 144 shows the data cache control unit 24.
0 shows a block diagram of the structure of the data cache 230. Here, the 128 × 256 bit RAM constitutes the cache memory 230, which comprises eight 128 × 32 bit separate addressable memory banks. This RAM has a writable port (write), a write address port (write_addr), and a write data port (write_data). It also has a readable port (read), eight read address ports (read_addr), and eight read data output ports (read_data). Cache memory 23
A write enable signal is generated from the cache control block 1878 to allow simultaneous writing to all memory banks of zeros. If necessary, the data cache 230 may store the write data port (write_dat).
Through a), the data is updated to one or more lines of data from the external memory. Providing a line address to a write address port (write_addr),
One line of data is written by using the 8: 1 multiplexer MUX. The 8: 1 multiplexer MUX selects a line address from the external address generated under the control of the data cache control unit (addr_select). A read enable signal is generated from cache control block 1878 to allow simultaneous reading of all memory banks of cache memory 230. In this manner, data of eight different bank lines are simultaneously read from eight read data ports (read_data) according to respective line addresses provided to eight write address ports (read_addr) of the memory banks of the cache memory 230. be able to.

Each cache memory 230 bank has a programmable address generator 1881.
This allows simultaneous access to eight different locations from the eight associated memory banks. Each address generator 1881 has a dcc mode input for setting an operation mode of the address generator 1881, an index packet input, a base address input, and an address output. The modes of operation of the programmable address generator 1881 include: (a) a signal to the dcc mode input places each address generator 1881 in a random access mode, an external memory address is provided to the index packet input, and one or more (B) JPEG encoding and decoding, color space conversion, matrix multiplication mode in which a signal to the dcc mode input puts each address generator 1881 into an appropriate mode. In this mode, the index to the index packet input is input to each address generator 1881 to generate an index address. Depending on the operation mode, the address generator can generate up to eight different external memory addresses.

The eight address generators 1881 are composed of eight different logic circuits, each of which has a base address as an input and a dcc having an external memory address as an output.
It consists of a mode and an index. The base address register 1885 stores the current base address, which is a combination of index packets, and stores the current base address in the dcc mode register 18.
Reference numeral 88 stores the current operation mode (dcc mode) of the data cache control unit 240.

The tag memory 1872 has one block, 128
It is composed of a × 20-bit multiport RAM. This RAM has one write port (update-line-
addr), one writable port (write), 8
Read ports (tag0_data, ..., tag)
7_data). This is accomplished by determining the tag address of the line (read0lin) of the one or more generated memory addresses where the eight address generators 1881 are currently stored.
e-addr,. . . , Read7line-add
r) allows eight simultaneous lookups.
The current tag address of these lines is the port (tag0
-Data,. . . , Tag7-data) to the tag comparing unit 1886. Port (update-l
A tag write signal is generated by the cache control block 1872, if necessary, to allow writing of in-addr) to the tag memory 1872.

A 128-bit line valid memory 1
Reference numeral 873 holds a valid state of each cache line of the cache memory 230. This includes one write port (update-line-addr), one writable port (update), and eight read ports (read0-line-addr, ..., read7).
line-addr), 8 readable ports (lin
evalid0,. . . , Linevalid7) is a 128 × 1 bit memory. Like the tag memory, it has eight address generators 1881, 1
For each line address of one or more generated memory addresses, determine the line valid state saved in the current line,
Port (read0 line-addr, ..., re
ad7 line-addr) for eight simultaneous lookups. The current line val of this line
The de bit is the port (linevalid0, ...,
linevalid7) to the tag comparing unit 1886. If necessary, the port (update-li) may be added to the write port of the line valid state memory 1873.
ne-addr) to line-valid state memory 18
A write signal to enable writing to 73 is generated from cache control block 1878.

The tag comparing unit 1886 is composed of eight tag comparators, and stores the tag memory 18 of the line accessed by the line address of the currently generated external address.
Tag_data input for receiving the currently saved tag address in 72, tag_add for receiving the tag address of the currently generated external memory address
r input, dcc_input for receiving the current operation mode signal (dcc_mode) for setting the tag address part to be compared, line valid state memory 1873 in the line accessed by the line address of the currently generated external address, and Line_v to receive the saved line valid state
It has a valid input. The comparison unit 1886 has eight hit outputs for each of the eight address generation units 1881. When the tag address of the generated external memory address matches the contents of the tag memory 1872 at the position accessed by the generated external memory line address, the hit signal and the line va to that line are output.
A lid status bit 1873 is output. In this embodiment, the data structure saved in the external memory becomes smaller, and the most significant bits of the tag address are all the same.
Therefore, only the least significant bit of the tag address change needs to be compared. This is made possible by the tag comparator 1866 setting the current operation mode signal (dcc_mode) to compare the least significant bit of the tag address.

When access to data in the cache memory 230 is possible, the cache control unit 1878 requests from the operands B247 and C248 (p
proc_req) and a notification (proc_ack). Depending on the operation mode, data of different addresses is requested from up to eight banks of the cache memory 230. When the requested data can be accessed from the cache memory 230, the tag comparison unit 1886 issues a hit to a line of that memory. Hit signal (hit
0,. . . , Hit7), the cache control unit 1
878 generates a readable signal at the port (cache_read) and enables reading to the cache line from which the hit signal was issued. Hit signal (hit
0,. . . , Hit7) but not the request (proc_re
q) When 1876 is issued, the generated request (ex
The external memory address of the data cache line is sent to the external memory together with (t_req). This cache line is written to the eight banks of the cache memory 230 through it when input (ext_data) is available. In this case, the tag information is also written in the tag memory 1886 of the line address, and the line status bit 1873 of the line is output.

Data from the eight banks of the cache memory 230 is output through a number of multiplexers in the data organizer 1892 and is positioned in a predetermined manner in output data packets 1894. In one operation mode, the data organizer 1892 uses the current operation mode signal (dcc_mode) and the byte address (byte_addr) of the generated external memory address to generate eight 32 bits output from eight memory banks.
An 8-bit word can be selected and output from the bit word. Data Organizer 1892 in other modes
Directly outputs eight 32-bit words output from eight memory banks. As described above, the data organizer arranges and outputs this data in a predetermined format.

The request is made in the next stage. 1) The processing unit is a cache control unit 187
8 to the processing unit interface to request packet data. 2) The eight address generation units 1881 generate addresses of each block of the cache memory according to the operation mode.

3) The tag position of the generated address is compared with the tag addresses saved in four blocks of the three-port tag memory 1886, and positioned by the line portion corresponding to the eight generated addresses. 4) If they match and the line valid state 1873 for that line is issued, the requested data is considered to be in cache memory 230.

5) Data that does not exist is transferred to external bus 1890
And the eight blocks of cache memory 230 are updated with the contents of the data lines from its external memory. The tag address of the new data is written to the tag memory 1886, and the line
The d state 1873 is issued. 6) If all the requested data is present in the cache memory 230, it appears in the processing unit in a fixed packet format.

As described above, all parts of the coprocessor 224 (FIG. 2) have the standard CBus interface 303.
(FIG. 20). Data cache control unit 24
Details of the 0 and standard CBus interface registers of the cache 230 are described in Appendix B B42 to B46. The setting of this register is performed by the data control unit 24.
0 operation is controlled. For simplicity, two registers (b
FIG. 153 shows only “ase_address” and “bcc_mode”.

When the data cache control unit 240 and the data cache 230 are valid, the data cache control unit invalidates all cache lines first and operates in the standard mode. At the end of an instruction, the data cache control 240 and the cache 230 always switch to the standard operation mode. All modes except the "Invalidate" mode have "Auto-fill and
validate ”. dcc_
By setting one bit in the cfg2 register,
All caches can start from the address saved in the base_address register.
During this operation, operand organizers B, C247,
The data request from 248 is aborted. The cache will be valid after this operation. a. Standard Cache Mode In this mode, the external memory address of the requested data is provided by two operand organizers. The address generator 1881 outputs the external memory address, and checks whether it exists in the memory cache 230 using the internal tag memory. If both requested data are not present in cache 230, data is requested from input interface switch 252. Round-robin scheduling is employed for persistent and simultaneous requests.

For a simultaneous request, if one data item exists in the cache, it will be located in the last 32 bits of the requested data bus. Other data is requested externally through the input interface switch. b. Single Output General Color Space Conversion Mode In this mode, the request is issued from the operand organizer B in the form of a 12-bit byte address. Figure 60
The requested data item is an 8-bit color output value, as shown in FIG. The 12-bit address is input to the index_packet input of the address generator 1881, and the eight address generators 1881 generate a 32-bit external memory address in the format shown in FIG. The bank, line, and byte addresses of the generated address are determined by Table 12 and FIG. External memory addresses are interpreted as eight 9-bit lines and byte addresses, which are used to point to bytes in eight banks of RAM. The cache is accessed by the main data path 242 for interpolation to the operand organizer to determine the 8-byte value of the bank returned in the manner described above with reference to FIG. Since all single output general color value tables fit in the cache memory 230,
Preferably, a single output color value table is loaded into cache memory 230 before applying the single color conversion mode. c. Multi-output general color space conversion mode In this mode, a 12-bit word address is received from the operand organizer unit B247. The request data item is the 32-bit color output value described above with reference to FIG. The 12-bit address is stored in the address generator 1
881 is input to the index_packet input, and 8
One address generator 1881 produces eight different 32-bit external memory addresses of the form shown in FIG.
Table 12 shows the line and tag address of the external memory address.
And FIG. The external memory address is
As described above with reference to FIG. 63, it is interpreted as eight 9-bit addresses having a 9-bit address divided into a 7-bit line address and a 2-bit tag address. If no tag address is found, the cache stops until the appropriate data is loaded from input interface switch 252 (FIG. 2). If data is available, the output data is output to the operand organizer. d. JPEG encoding mode In this mode, tables and the like necessary for the JPEG encoding mode are saved in the bank of the cache RAM. The table is stored in the JPEG encoding mode (Table 1).
4, 16). e. Slow JPEG decoding mode In this mode, data is generated according to Table 17. f. Matrix multiply mode In this mode, the cache is used to access data on 256 byte lines. g. Disabled mode In this mode, all requests are passed to the input interface switch 252. h. Invalidate mode In this mode, the contents of all caches are invalidated by clearing the line valid status bit.

3.18.7 Input Interface Switch In FIG. 2, the input interface switch performs a function of adjusting request data from the pixel organizer unit 246, the data cache control unit 240, and the instruction control unit 235. It also transmits necessary addresses and data to the external interface controller 238 and the local memory controller 236.

The input interface switch 252 stores the setting in any register of the base address or the memory object in the host memory map. This is a virtual address aligned on a page boundary because 20 address bits are required. In response to a request from the pixel organizer unit, the data cache control unit, or the instruction control unit, the input interface switch 252 first subtracts the coprocessor base address bit from the upper six bits of the data start address. If the result is negative or the upper 6 bits of the result are not 0, then the PCI bus is the desired destination.

If the upper 6 bits of the result are 0, it means that the data map represents a memory location of the coprocessor. The input interface switch then examines the next three bits to determine if the coprocessor is in the correct position. The legal location of the coprocessor is: 1) offset 0x from the coprocessor base address
16 megabytes occupied by general interfaces starting from 01000000.

2) Local memory controller (LMC) occupying 32 starting at offset 0x0200000 from the base address of the memory object of the coprocessor 32
Megabytes. Requests pointing to illegal coprocessor locations are:
Considered an error by the input interface switch. The PCI bus is a data source for addresses other than the area occupied by the memory objects of the coprocessor. The input interface switch uses the i source signal to inform the EIC whether the requested data is from the PCI bus or from the general interface.

After the address decoding process, the legitimate request is transmitted to the appropriate IBus interface. EIC and L
The MC transmits data to the input interface switch when the i-ack signal is output. However, since the input interface switch does not count the number of input words, the i-oe signal controlled by the pixel organizer unit, the command control unit, and the data cache control unit must monitor when the current data transmission ends. No.

The input interface switch 252 controls three modules: a pixel organizer, a data cache controller, and an instruction controller. They can request data at the same time, but since there are only two physical resources, the request is not processed immediately. The adjustment technique used for the input interface switch is priority based and can be programmed. The control bits in the input interface switch setting register are:
The relative priority of the instruction control unit, the data cache control unit, and the pixel organizer unit is specified. A request from a lower priority module is accepted in the absence of a request from the other two modules to access the same resource. Given that at least two request sources are given the same priority, it becomes necessary to use round-robin techniques to determine the request source from which requests are accepted.

Since it is impossible to immediately access one source, the input interface switch needs to store the address and burst length of the requested data and check whether to prefetch the data provided by the requestor. There is. In the process for a certain source, IBu
If there is no s process, an adjustment process for determining the priority is required.

FIG. 145 shows the details of the command interface switch 252. The switch 252 has two IBus transceivers 661 between the address decoder 863 and the controller 864 in addition to the standard CBus interface and the register file 860. The address decoder 863 decodes an address in response to a request received from the pixel organizer, the data cache controller, and the instruction controller. The address decoder 863 checks whether the address is valid and remaps the address if necessary. The control unit 864 determines which request is transmitted from the IBus transceiver 661 to the I bus transceiver 661.
It decides whether to transmit to the Bus transceiver 662. Priority is programmable.

The IBus transceivers 861 and 862 are
It has a multiplexing and demultiplexing function, and a tri-state buffering function for enabling communication from another interface to the input interface switch. 3.18.8 Local Memory Control Unit In FIG. 2, the local memory control unit 236 is in charge of all of the control of the local memory and the processing of the access request between the local memory and the module in the coprocessor. The local memory controller 236 responds to a write request from the result organizer 249 and a read request from the input interface switch 252. Further, the peripheral interface control unit 237 and the ordinary general C
It also responds to read and write requests from the Bus input. The local memory controller uses a programmable priority system and employs a FIFO buffer to maximize throughput.

In the present invention, in addition to a first-in first-out (FIFO) buffer, a multiport burst dynamic memory controller is used to decouple ports from the memory array. FIG.
Reference numeral 46 denotes a block diagram of a 4-port burst dynamic memory control unit according to the first embodiment of the present invention. This circuit has two write ports (A1944 and B1) that require access to the memory array 1910.
946) and two read ports (C1948 and D19)
50) is included. Read ports 1948, 19
The 50 data paths are separate FIFOs 1936, 1938
Out of the memory array 1910 via
The data path from one write port is a separate FIFO
After passing through 1920 and 1922, the signal goes to the memory array 1910 via the multiplexing unit 1912. The central control unit 1932
It drives all control signals necessary for interfacing to the dynamic memory 1910 and coordinates overall port access. Refresh counter 193
4 determines the required time of the refresh cycle of the dynamic memory for the memory array 1910,
Adjust these together with 932.

Preferably, reading and writing of data from and to memory array 1910 is performed by using write port 19.
44, 1946 to FIFO 1920, 1922 or FIFO 1936, 1938 to read port 19
48, 1950 at twice the rate. As a result, the write and read ports 1944, 194
6, 1948, 1950, the time required to transfer data through the memory array 1910,
Alternatively, the time required for transfer to the memory array 1910 (which is the bottleneck of any memory system) is made as short as possible.

Data is written to write ports 1944, 19
The data is written to the memory array 1910 via any one of 46. The circuits connected to the write ports 1944, 1946 are provided with FIFOs 1920, 1922 having an initial value of zero.
Only you will recognize. Write port 1944, 1
Data transfer through 946 is performed in FIFO 1920, 1
Proceed smoothly until 922 is full or the burst is over. The data is first FIFO 192
0, 1922, the control unit 1932
Arbitrate with other ports for access to the AM.
When access is available, data is FIFO at maximum rate
1920, 1922, and the memory array 19
Written to 10. A burst write cycle to DRAM 1910 starts only when a preset number of data words have been stored in FIFOs 1920 and 1922 or when the burst from the write port has ended. In either case, the DRAM 1910
Burst from the permitted point, and FIFO 19
Continue until 20, 1922 is empty or there is a cycle request from a higher priority port. In either event, data is transferred from the write ports to the FIFO 1920, 1 until the FIFO is full or the current burst ends and a new burst begins.
The data is continuously written to 922 without any interruption. In the latter case, the new burst is the same as the previous burst
The process does not proceed until the data 20 and 1922 are emptied and written into the DRAM 1910. In the former case, the first word is read from FIFO 1920,
As soon as the data is written to the AM 1910, the data transfer is resumed. Since data transfer from the FIFOs 1920 and 1922 is at the highest rate, the write ports 1944 and 1944
The stall 46 is possible only when the control unit 1832 is interrupted by a cycle request from another port. FIFO1 from write ports 1944, 1946
It is desirable to keep any interruptions to data transfers to 920, 1922 as minimal as possible.

The read ports 1948 and 1950 operate in the reverse order. As soon as the read ports 1948, 1950 issue a read request, a DRAM cycle is requested. When permission for this request is obtained, the memory array 1910 is read and the corresponding FIFOs 1936, 193 are read.
8 is written. FI is the first data word
As soon as the data is written to the FOs 1936 and 1938, the data can be read by the read ports 1948 and 1950. Thus, while there is an initial delay in obtaining the first data word, there is probably no further delay in obtaining subsequent data words. D
RAM read is a higher priority DRA
M request, read FIFO 1936, 1938
Is full or the read ports 1948, 1
If 950 no longer requests data, it ends. Once reading is completed in this way, the FIFO
The processing is not restarted until the number of data words preset in O1936 and 1938 is sufficient. Once the read port completes the cycle, FIFO 1936,
Any data remaining in 1938 is discarded.

In order to ensure that the DRAM control always exceeds the minimum value, a preset number of data words must be transferred (or the corresponding FIFO1
920 and 1922 are empty or read FIFO 19
Re-arbitration for DRAM accesses is limited so that bursts are not interrupted (until 36, 1938 is full). All access ports 1944, 1946, 194
8, 1950 have corresponding burst start addresses, which are latched in counter 1942 at the start of the burst. This counter holds the current address for dealing with the port, so that even if the transfer is interrupted, it is possible to restart at least the correct memory address. Only the address of the currently active DRAM cycle is multiplexed by 1940.
And sent to the row address counter 1916 and the column address counter 1918. The lower N bits of the address are input to column counter 1918, while one upper address bit is input to row counter 1916. The multiplexing unit 1914 outputs a row address from the row counter 1916 to the memory array 1910 during the row address time of the DRAM, and sends a column address from the column counter 1918 during the column address time of the DRAM. Row address counter 1916 and column address counter 1918 indicate that memory array DRAM1
910. This is true both at the beginning of the port cycle and at the continuation of the interrupted burst. The column address counter 1918 is incremented after each memory transfer occurs, and the row address counter 1916 is incremented when the column address counter 1918 changes to zero. In the latter case, the burst is terminated and must be restarted with a new row address.

In this embodiment, the memory array 1910 has 4
X 8 bit byte lines, 3 words per word
It is assumed that two bits are configured. Furthermore, a set of 4-byte write enable signals 1950, 1952 corresponding to the respective write ports 1944, 1946.
To individually write data to each 8-bit portion of each 32-bit data word in memory array 1910. Memory array 1910
Since it is possible to arbitrarily mask data writing to any byte in each word to be written to the corresponding FIFO, it is necessary to store write enable information in the corresponding FIFOs 1926 and 1928 together with each data word. These FIFOs 1926,
1928 is controlled by the same signals used to control the write FIFOs 1920 and 1922, but only four bits are used instead of the 32 bits required to write data to the FIFOs 1920 and 1922. Similarly, the multiplexing unit 1930
Controlled in the same way as 12. The selected write enable is input to the control unit 1932, and the control unit uses the information to synchronize the write data input to the memory array 1910 by the multiplexing unit 1912 with the addressed word in the memory array 1910. To selectively enable or disable writing to the file.

The structure shown in FIG. 146 operates under the control of the control unit 1932. FIG. 147 is a block diagram of the control unit 19 shown in FIG.
32 is a state diagram showing details of the operation of FIG. After power-up and upon completion of reset, the state machine forces IDLE1
00 state, all the DRAM control signals become inactive (high) in this state, and the multiplexer 1914 sends the row address to the DRAM array 1910. When a refresh or cycle request is detected,
Transition is made to the RASDEL 11962 state. When there are no more cycle requests and refreshes at the next clock edge, the state machine returns to the IDLE 1900 state. Otherwise, transition to the RASON 1966 state occurs when the DRAM tRP (RAS precharge timing limit) cycle is satisfied, at which time the row address strobe signal RAS goes low. After tRCD (delay timing restriction from RAS to CAS) is satisfied, the state transits to the COL1968 state, and the multiplexing unit 1914 is switched so as to select a column address to be input to the DRAM array 1910. CASON 1970 at next clock edge
To the DRAM column address strobe (CA
S) The signal goes active low. Once, tCAS (C
If AS Active Timing Limit is met, CA
The state transits to the SOFF1972 state.
The column address strobe (CAS) goes inactive high again. Here, if more data words are to be transferred and if a higher priority cycle request or refresh is not imminent or too fast to re-arbitrate, then tCP (C
When the (AS precharge timing limitation) cycle is satisfied, the state returns to the CASON 1970 state, and the DRAM column address strobe (CAS) becomes active low again. If there is no further data word transfer or re-arbitration occurs and a higher priority cycle request or refresh is imminent, tRAS (RAS active timing limit) and tCP (CAS precharge timing limit) If both are met, RA instead
Transition is made to the SOFF 1974 state. In this state, DR
The AM row address strobe (RAS) signal goes inactive high. State machine IDL at next clock edge
It returns to the E1860 state and prepares for the start of the next cycle.

When a refresh request is detected in the RASDEL2 1964 state, once tRP (RAS precharge timing restriction) is satisfied, RCASON
Transition is made to the 1980 state. In this state, the DRAM column address strobe becomes active low, and DRAM CAS starts before the RAS refresh cycle. At the next clock edge, a transition is made to RRASON 1978 and the DRAM row address strobe (RAS) goes active low. When tCAS (CAS active timing limit) is satisfied, the transition is RCASOFF 19
76, and the DRAM column address strobe (CA
S) becomes inactive high. Once tRAS (RA
If the S active timing limit is satisfied, the transition is R
ASOFF 1974, the DRAM row address strobe (RAS) goes inactive high, effectively ending the refresh cycle. The state machine continues to behave as described above for a normal DRAM cycle and transitions to the IDLE 1960 state.

The refresh counter 1934 shown in FIG.
Is a simple counter which generates a refresh request signal at a fixed rate of once per 15 microseconds or at a rate determined by the requirements of a special DRAM vendor. When a refresh request is issued, the request remains in the issued state until acknowledged by the state machine of FIG. This acknowledgment occurs when the state machine enters the RCASON 1980 state and remains there until the state machine detects withdrawal of the refresh request.

FIG. 148 shows the pseudo code form of FIG.
The operation of 46 arbitrators 1924 is shown. Here, a method for determining which of the four cycle request issuers is permitted to access the memory array 1910,
Describes a mechanism that modifies the priority of a cycle requestor to maintain fairness to access. The symbols used for these codes are described in FIG.

Each request issuer has 4 bits that indicate the priority of the request. The upper two bits are preset to a general priority by a configuration value set in a general configuration register. The lower two bits of the priority are stored in a two-bit counter updated by the arbitrator 24. In determining the winner of the arbitration, the arbitrator 1924 will simply determine the 4
Compare bit values and grant access to requestor with highest value. When the requester is granted the cycle, the value of the lower 2 bits priority counter becomes zero, and the lower 2 bits of the other requesters having the same upper 2 bits priority value and the lower 2 bits priority value lower than the winner. All bit priority counts are incremented by one. As a result, the requester who is now permitted to access the memory array 1910 has the lowest priority among requesters having the same upper two-bit priority value. The priority value of the lower 2 bits of the requestor whose priority value of the upper 2 bits is different from the winner is not affected. The value of the upper two bits of the priority determines the overall priority of the requester, and the value of the lower two bits implements a fair arbitration scheme between requesters of the same higher priority. By using this scheme, it is possible to partially switch from a fixed priority connected by hardware (the upper 2 bits of each requester is unique) and to perform partial hardware connection (some but not all upper 2 bits). Various arbitration schemes can be realized, up to a strict fair exchange (priority is different from the others) (priority values of all upper 2 bits are the same).

FIG. 149 shows the structure of a priority bit for each requester and how to use the bit. Here, the meaning of the symbols used in FIG. 148 is also defined. Various FIFOs in the above embodiment
O1920, 1922, 1938, and 1936 are 32 bits wide and 32 words deep. This depth offers a good line compromise between efficiency and circuit area consumed. However, the depth value can be changed to suit the needs of a particular application as performance changes.

The four-port configuration shown here is merely one embodiment. Providing only a single FIFO buffer between the memory array and either the read or write port can be effective. However, using a large number of read and write ports will provide the highest speed improvement. 3.18.9 Other Modules The other modules 239 operate the coprocessor 224, reset synchronization, multiplex error and interrupt signals by routing internal diagnostics signals to external pins as needed, and internal and external forms of the CBus. Interfacing and general / external Cbu of internal and general Bus signals
A clock for multiplexing to the s output pin is generated and selected. Of course, the operation of the other module 239 depends on the clocking requirements and implementation details of the ASIC technology used.

3.18.10 External Interface Control The following described aspects of the invention relate to a method and apparatus for providing virtual memory on a host computer having a coprocessor that shares virtual memory. . Embodiments of the present invention seek to enable a coprocessor to operate in a virtual memory mode in conjunction with a host processor.

In particular, the coprocessor can operate in the virtual memory mode of the host processor. The coprocessor includes a virtual memory-to-physical memory mapping device that can reference the host processor's virtual memory table, and translates the instruction address generated by the coprocessor into a corresponding physical address in the host processor's memory. Map. Rather, the virtual memory-to-physical memory mapping device forms part of a computer graphics coprocessor for generating graphic images. The coprocessor includes a number of modules that can perform various complex operations on the image. The mapping device is responsible for the interaction between the coprocessor and the host processor.

External interface control unit (EIC) 2
38 provides an interface to the coprocessor PCI Bus and General Bus. Further, the external interface control unit also provides a memory management for connecting between the internal virtual address space of the coprocessor and the physical address space of the host system. The external interface control unit 238 operates as a master on the PCI bus when reading data from the host memory in response to a request from the input interface switch 252 or writing data to the host memory in response to a request from the result organizer 249. . Access to PCI Bus
“PCI Local Bus Specificat
ion, draft2.1 ”PCI special
It is embodied according to the standard of interest group, 1994.

The external interface controller 238 arbitrates simultaneous requests for PCI transactions from the input interface switch 252 and the result organizer 249. Preferably, the arbitration is configurable. The type of request received may include reading one or less cache lines at a time by the host coprocessor, reading cache lines between one and two lines by the host, and reading two or more cache lines at a time. included. Infinite length writing is also implemented by the external interface control unit 238. Further, the external interface control unit 238
Also optionally prefetches data.

The construction of the external interface controller 238 includes memory management that provides address mapping from virtual memory to host physical memory for all coprocessor internal modules. This mapping is completely transparent to the module requesting access. When the external interface control unit 238 receives a request to access the host memory, it initializes the memory management unit and translates the requested address. If the memory management unit fails to translate the address, in some cases one or more PCI Bus transactions may result in completing the address translation. This means that the memory management unit itself can be another source to request a transaction from the PCI Bus. When a burst requested from input interface switch 252 or result organizer 249 crosses a virtual page boundary, external interface control 238 automatically activates the memory management unit and remaps all virtual addresses correctly.

[0506] Memory management unit (MMU)
(915 in FIG. 150) is based on 16 lookaside buffers (TLBs). The TLB acts as a cache for virtual to physical address mapping. T
The following operations are possible in the LB. 1) Comparison: Given a virtual address, the TLB returns either the corresponding physical address or a TLB miss signal (if no valid entry matches the address).

2) Replacement: A new virtual-to-physical mapping is written to the TLB in place of an existing entry or an invalid entry. 3) Invalidation: When a virtual address is given and a TLB entry is matched, the matching entry is invalidated. 4) Invalidate All: Invalidates all TLB entries.

5) Read: The virtual and physical addresses of the TLB entry are read on a 4-bit address basis. Used for testing only. 6) Write: The virtual and physical addresses of the TLB entry are written on a 4-bit address basis. The entry in the TLB has a format as shown in FIG. Each valid entry is composed of a 20-bit virtual address 670, a 20-bit physical address 671, and a flag indicating whether the corresponding physical page is writable. The allowable page size of the entry is 4K bytes. A register in the MMU can be used to mask up to 10 bits of the address used for the comparison. This supports up to 4 Mbytes of TLB pages. Since there is only one mask register, all TLB entries refer to pages of the same size.

[0509] The TLB contains "Least-Recent".
A ly Used "(LRU) replacement algorithm is used. The new entry overwrites the oldest entry since it was last written or matched in a comparison operation.
This only applies if there are no invalid entries. If there is an invalid entry, it is written to the invalid entry before overwriting the valid entry.

FIG. 152 shows the flow of the TLB comparison operation.
The received virtual address 880 is 3 of 881 to 883.
Divided into two parts. The lower 12 bits 881 are always sent directly to the corresponding physical address bits 885 because they are always part of the offset in the page. Next 10
Bit 882, as set by the mask bit,
Either the offset part or the page number part depending on the page size. A value of zero in the mask register 887 indicates that the bit is part of the page offset and should not be used for TLB comparison. The 10 address bits are logically "ANDED" with the 10 mask bits to provide the lower 10 bits of the virtual page number 889 for TLB lookup. The upper 10 bits 883 of the virtual address are used directly as the upper 10 bits of the virtual page number 889.

[0511] The 20-bit virtual page number generated in this manner is sent to the TLB. If this matches one of the entries, the TLB returns the number of the location that matched the corresponding physical page number 872. The physical address 873 is generated from the physical page number using the mask register 887 again. The upper 10 bits of the physical page number 872 are directly used as the upper 10 bits of the physical address 873. The next 10 bits of the physical address 872 are
875 is selected from either the physical page number (when the corresponding mask bit is 1) or the virtual address (when the mask bit is 0). The lower 12 bits 885 of the physical address are directly provided from the virtual address.

Finally, according to the match, the LRU buffer 87
6 is updated to indicate use of the matched address. T
The LB miss occurs when the input interface switch 252 or the result organizer 249 requests access to a virtual address that does not exist in the TLB 872. In this case, before the MMU proceeds with the requested access,
The requested virtual-to-physical translation must be fetched from the page table in host memory 203 and written to the TLB.

The page table is a hash table of the host main memory. Each page table entry has two 3D entries in the format shown in FIG.
It consists of two bit words. The second word comprises the upper 20 bits for the physical address and the lower 12
Bits are reserved. The upper 20 bits of the corresponding virtual address are given in the first word. Lower 12
The bits include a valid (V) bit and a writable (W) or "read only" bit, with the remaining 10 bits.
Bits are reserved.

The page table entry basically contains T
It contains the same information as the LB entry. Extra flags in the page table are reserved. The page table itself is usually distributed over a plurality of pages in the main memory 203, and is generally adjacent to the virtual space and not in contact with the physical space. The MMU contains a set of 16 page table pointers set by software, each being a 20-bit pointer to a 4K byte memory area containing the page table portion. This means that the coprocessor 224 supports a page table of 64K byte size and has 8K page mapping. In a 4K byte page size system, this means up to 32 Mbytes of mapped virtual address space. Rather, the page table pointer always refers to a 4K byte memory area, regardless of the page size used for the TLB.

An MMU operation after a TLB miss is shown in FIG. 154 at 690 as follows. 1. The hash function 892 on the virtual page number 891 that does not exist in the TLB is executed to generate a 13-bit index in the page table. 2. Using the upper 4 bits 894 of the page table indexes 894 and 896, the page table pointer 895 is used.
Select

[0516] 3. The 20-bit page table pointer 895 and the lower 9 bits of the page table index 896 are concatenated, and the least significant 3 bits are set to 000.
Generates the physical address 890 of the requested page table entry (to occupy bytes). 4. Starting from the physical address 898 of the page table entry, 8 bytes are read from the host memory.

5.8-byte page table entry 9
When the 00 is returned to the PCI bus, if the VALID bit is set to 1, the virtual page number is compared to the original virtual page number that caused the TLB miss. If they do not match, the next page table entry is fetched using the above process (the physical address is incremented by 8 bytes). This process continues until a page table entry with a matching virtual page number is found or an invalid page table entry is encountered. If an invalid page table entry is encountered, a page fault error is issued and processing stops.

[0518] 6. When a page table entry with a matching virtual page number is found, the replace operation writes the complete entry to the TLB. The new entry is the TL pointed to by the LRU buffer 876
Placed in position B. Then, the TLB comparison operation is performed again, and the processing of the original requested host memory access can be performed smoothly. As new entries are written to the TLB, the LRU buffer 876 is updated.

The hash function 892 implemented in the EIC 238 uses the following equation for a 20-bit virtual page number (vpn). index = ((vpn >> S1) XOR (vpn >>
S2) XOR (vpn >> S3)) &Ox1ffff; Here, S1, S2, and S3 are independently programmable shift amounts (positive or negative) and can take four values.

When the linear search of the page table crosses the 4K byte boundary, the MMU automatically selects the next page table pointer and continues the search at the correct physical memory location. This involves wrapping the page table from the end to the beginning. The page table always has at least one invalid (null) so that the search is always terminated.
l) Contains an entry.

Each time software replaces a page in host memory, a page table entry for the new virtual page must be added and the entry corresponding to the replaced page must be deleted. Also, old page table entries must not be cached in the TLB of coprocessor 224. This is done by performing a TLB invalidation cycle in the MMU.

The invalidation cycle gives the virtual page number to be invalidated with the bit causing the invalidation work, and the MMU
This is accomplished through a register write to. This register write is performed directly by software or through an instruction interrupted by the instruction decoder.
Invalidation work is performed by TL for the provided virtual page number.
Performed on B. When a TLB entry matches, the entry is marked invalid and the LRU table is updated so that the invalidated location is used for the next replacement operation.

[0523] The pending revocation work is any pending T
Has a higher priority than LB comparison. When the invalidation operation is completed, the MMU clears the invalidation bit,
Notifies that the next invalidation process is possible. If the MMU cannot find a valid page table entry for the requested virtual address, it is called a page fault. The MMU issues an error signal and stores the faulted virtual address in a software accessible register. The MMU enters an idle state and waits until the error is resolved. When the interrupt is cleared,
The MMU starts again with the next requested transaction.

A page fault is also issued when a write operation is performed on a page marked as read-only (not marked as writable). The external interface controller (EIC) 238 responds to transaction requests from the input interface switch 252 and result organizer 249 addressed to the general bus.
Each request module indicates whether the current request is for a general bus or a PCI bus. Unlike using a common bus for communication between the input interface switch 252 and the result organizer 249, EIC operations for general bus requests are completely separate from operations for PCI requests. Further, the EIC 238 is also compatible with a Cbus transaction type that directly addresses the general bus space.

FIG. 150 shows the structure of the external interface control section 238. The IBus request is sent to the multiplexing unit 9
Through 10, multiplexor 910 routes the request to the appropriate internal module (PCI or general bus) based on the destination of the request. The request for the general bus is sent to the general bus control unit 911 which also has the RBus and the CBus. RBus
Since the above general bus and PCI bus requests use different control signals, a multiplexing unit is not required for this bus.

The IBus request led to the PCI bus is IB
us driver (IBD) 912. Similarly, the RBus request to the PCI is sent to the RBus receiver (RB
R) 914. IBD912 and RBR
914 sends the virtual address to a memory management unit (MMU) 915 that returns a physical address. IBD,
The RBR and then the MMU can each request PCI transactions, which are generated and controlled by a PCI Master Mode Controller (PMC) 917. IBD and MMU require only PCI read,
RBR requires only PCI writes.

A separate PCI target mode control unit (P
TC) 918 processes all PCI transactions addressed to the coprocessor as targets.
This sends a CBus master mode signal to the command control,
Allow access to all other modules. PT
C sends the returned CBus data to the PCI bus via the PMC, so that control of the PCI data bus pins comes from a single source.

The CBus transactions addressed to the EIC registers and module memory are handled by the standard CBus interface 7. All submodules receive bits from the control register and return bits to the status register. These are standard CBus
Located inside the interface. Parity generation and checking for PCI bus transactions
Parity generation and check (PGC) module 921 which operates under the control of C and PTC. The generated parity is sent to the PCI bus similarly to the parity error signal. The result of the parity check is
It is also sent to the configuration register of the PTC for error reporting.

FIG. 155 shows the structure of the IBus driver 912 of FIG. The accepted IBus address and control signals are latched 930 at the beginning of the cycle. OR gate 931 detects the beginning of a cycle and generates a start signal to control logic 932. The upper address bits of latch 930 forming the virtual page number are loaded into counter 935. The virtual page number is sent to MMU 915 (FIG. 150) which returns the physical page number latched in 936.

The physical page number and the lower virtual address bit are recombined by the mask 937, and the PMC 717
Form address 938 for a PCI request to (FIG. 102). The burst count for the cycle is also loaded into counter 939. The prefetch operation is different from that of the counter 941, the address latch, and the comparison circuit 943.
Is used. The data returned from the PMC includes a FIFO 94 with a marker indicating whether the data is part of a prefetch.
4 is loaded. As data becomes available in the portion prior to FIFO 944, it is read through latches 945, 946 and clocked out by logic. Read logic 946 also generates an IBus acknowledgment signal.

A central control block 932 controls the sequential processing of all address and data elements, including the state machine, and the interface to the PMC. The virtual page number counter 935 is the page number bit from the IBus address and is loaded at the start of the IBus transaction. The upper 10 bits of this 20-bit counter always come from the accepted address.
For the lower 10 bits, each bit is loaded from the accepting address if the corresponding mask bit 937 is set to 1, otherwise the counter bit is set to 1. The 20-bit value is sent to the MMU interface.

In normal operation, virtual page numbers are not used after initial address translation. However, if the IBD detects that the burst crosses a page boundary, the virtual page counter is incremented and another conversion is performed. A simple increment to a 20-bit value results in an increment of the actual page number field because the low order bit that is not part of the virtual page number is set to one when the counter is loaded. After being incremented, mask bit 937 is used again to set up the counter for the next increment.

After conversion, the physical address is latched 936 each time the MMU returns a valid physical page number. The mask bits are used to correctly combine the returned physical page number with the original virtual address bits. The physical address counter 938 is loaded from the physical address latch 936. It is incremented each time a word is returned from the PMC. Each time the counter is incremented, the counter is monitored to determine if the transaction is about to cross a page boundary. The mask bits are used to determine which bits of the counter are used for the comparison. When the counter detects that the number of words remaining in the page is less than two, it signals the control logic 932 to terminate the current PCI request after two data transfers and, if necessary, to add a new address. Request a conversion. The counter is reloaded after the new address translation and the PCI request resumes.

The burst counter 939 is loaded with the IBus burst value at the beginning of the transaction.
It is a bit down counter. It is decremented each time a word is returned from the PMC. When the value of the counter falls below two, a signal is sent to the control logic 932, which can terminate the PCI transaction after two data transfers (unless prefetching is possible).

[0535] The prefetch address register 943 is
Loaded with the physical address of the first word of any prefetch. The subsequent IBus transaction begins, and if the prefetch counter indicates that at least one word was successfully prefetched, the first physical address of the transaction is compared to the value of the prefetch address. If they match, the prefetch data is used to satisfy IBus pickup,
PC at address after last prefetched word
An I transaction request starts.

The prefetch counter 941 is a 4-bit counter, and is incremented each time a word is returned by the PMC during a prefetch operation to the same count as the maximum input FIFO depth. When the subsequent IBus transaction matches the prefetch address, the prefetch count is added to the address counter and then subtracted from the burst counter, allowing the PCI request to start at the required location. Alternatively, if the IBus transaction requires only a portion of the prefetched data, the length of the requested burst is subtracted from the prefetch count, then added to the latched prefetch address, and the remaining prefetch data is further processed. Pending to fulfill request.

[0537] The data FIFO 944 is 8 words x 33
Bit asynchronous fall-through FIFO. PMC
Is written to the FIFO with a bit indicating whether the data is part of a prefetch. FI
Data from the top of the FO will be available as soon as it becomes available.
It is read from the FO and sent to the IBus. The logic for generating the data read signal operates in synchronization with clk,
Generate an IBus acknowledgment output. If the transaction is filled with prefetched data, the signal from the control logic will be
Information about the number of prefetched data to be read from O is provided to the read logic.

FIG. 156 shows the structure of the RBus receiver 914 shown in FIG. Control is split between the two state machines 950, 951. Write state machine 951 controls the interface to RBus. The input address 752 is latched at the start of the RBus burst. Each data word of the burst is written to FIFO 754 with a byte enable. When the FIFO 954 becomes full, the write logic 951 cancels the r-ready, preventing the organizer from writing any more words.

[0539] The write logic 951 signals the start of the RBus burst to the main state machine 950 via the resynchronization start signal to prevent the organizer from writing any more words. The upper address bits forming the virtual page number are loaded into counter 957. The virtual page number is sent to the MMU, which returns a physical page number 958. The lower bits of the physical page number and the virtual address are recombined according to the mask, and the counter 960
And provides the address for the PCI request to the PMC. The data and byte enable for each word of the PCI request are clocked out of the FIFO 954 by the main control logic 950, which also handles all PMCM interface control signals. The main state machine indicates that it is active via a busy signal, which is resynchronized back to the write state machine.

[0540] The write state machine 951 detects the end of the RBus burst using the r-final. Then F
The loading of the data into the IFO 954 is stopped, and the main state machine is notified that the RBus burst has ended. The main state machine continues the PCI request until the data FIFO is empty. It then cancels the busy and causes the write state machine to start the next RBus burst.

Referring back to FIG. 150, the memory management unit 915 includes an IBus driver (IBD) 912.
And an RBus receiver (IBR) 914 for converting a virtual page number to a physical page number. FIG.
FIG. 7 shows details of the memory management unit. 16-Entry Translation Lookaside Buffer (TL
B) 970 receives input data from TLB address logic 971 and sends back output. TLB control logic 972, which includes a state machine, receives requests buffered in TLB address logic from RBR or IBD. Upon receiving the request, it selects the source of the input and the work to be performed by the TLB. Valid TL
The B operation is comparison, invalidation, all invalidation, writing and reading. The source of the TLB input address is IB
D and RBR interface (for comparison work), page table entry buffer 974 (for TLB miss service) or register in TLB address logic. The TLB returns the status of each task to the TLB control logic. The physical page number from the successful comparison operation is sent back to the IBD and RBR. The TLB keeps a record of the most recently accessed (LRU) location, which is useful for the TLB address logic to use as a location for write operations.

If the comparison operation fails, the TLB control logic 972 signals the page table access control logic 976 to initiate a PCI request. The page table address generator 977 uses the internal page table pointer register to generate a PCI address based on the virtual page number. Data returned from the PCI request is latched into page table entry buffer 974. If a page table entry that matches the required virtual address is found, the physical page number is sent to TLB address logic 977 and then page table access control logic 976
Notifies that page table access has been completed.
Then the TLB control logic 972
And a comparison operation is started again.

The register signals to and from the SCI are resynchronized 980 in both directions. The signal goes to all sub-modules. Module memory interface 981 decodes access to TLB and page table pointer memory elements from the standard CBus interface. TLB access is read-only and uses TLB control logic to obtain data. The page table pointer is readable and writable, and is directly accessed by the module memory interface. These paths also include synchronization circuits.

3.18.11 Peripheral Interface Controller FIG. 158 shows an example of the peripheral interface controller (PIC) in FIG. 2 in detail. PIC237
Operates in one of several modes for transferring data to or from external peripheral devices. The basic modes are: 1) Video output mode: In this mode, data is transferred to the periphery under the control of an external video clock and clock data enable. The PIC 237 sends an output clock and a clock enable sign at the required timing for the output data.

2) Video input mode: In this mode, data is transferred to the periphery under the control of an external video clock and clock data enable. 3) Centronics mode: This mode is based on IEEE
According to the standard protocol defined in the 1284 standard,
Transfer data to and from the periphery. The PIC 237 separates the protocol of the external interface from the internal data source and destination as needed. The internal data source writes the data to a single stream of output data and is transferred to external peripherals according to the mode selected. Similarly, all data from the external periphery is written to a single input data stream and used to fulfill the required transaction for one of the possible internal data destinations.

[0546] Possible output data sources include LM
C236 (using ABus), RO249 (RBus)
), And three of the general CBus. PIC 237 responds to transactions from these data sources only one at a time. Transactions from one source are completed before the next source is considered. Generally, only one data source should be active at any given time. When two or more sources become active, they are processed in order of CBus, ABus, and RBus priorities.

As usual, the module is a standard CBus interface 99 containing the PIC internal registers.
Operate under 0 control. Further, the CBus interface 992 can access and control peripheral devices via the coprocessor 224. The ABus interface 991 can also handle memory interactions with the local memory controller. In addition to the result organizer 249, the ABus interface 991 and the CBus interface 992 both send data to an output data path 993 that contains a byte-wide FIFO. Access to the output data path is controlled by an arbitrator that constantly checks which source has priority or ownership over the output stream. The output data path interfaces the bidet with output control 994 and centronics control 997 depending on which is enabled. Each module 994, 997 reads one byte at a time from the internal FIFO of the output data path. The Centronics control unit 997 implements a standard Centronics data interface to control peripheral devices. The video output controller includes logic for controlling the output pads according to the required video output protocol. Similarly, the video input control 998 includes logic to control any video input standard being used.
The video input control unit 998 includes an input data path unit 99
9, which again constitutes a byte-wide input FIFO with data being asynchronously written to the FIFO one byte at a time by either the video input control 998 or the Centronics control 997.

The data timer 996 includes various counters, and is used to monitor the current state of the FIFO in the output data path 993 and the input data path 999. In view of the foregoing, it appears possible with a coprocessor to execute dual stream instructions to simultaneously generate multiple images or multiple portions of a single image. The primary instruction stream is used to obtain an output image of the current page, and the secondary instruction stream can be used to begin rendering the next page while the primary instruction stream is idle. As a result, in the standard mode of operation, the image of the current page is rendered and then compressed using the JPEG coder 241. When you need to print an image,
The coprocessor 241 uses the JPEG coder 241 twice to decompress the JPEG encoded image. During idle time when no more JPEG decoded image portions are needed from the output device, it is possible to execute instructions for the construction of the next page or band. Generally, this process increases the rate at which images are generated due to the overlap of the coprocessor operations. In particular, when the coprocessor 224 is used, printing is performed by a printer attached to the coprocessor, and as a result, the rendering speed is increased. Therefore, a benefit is obtained in terms of speeding up the image processing operation.

It will be apparent from the foregoing that the preferred embodiment described above is one embodiment of the present invention and that obvious modifications can be made to those skilled in the art without departing from the scope of the present invention.

Appendix A Coprocessor Microprogramming In this section, each execution of a new instruction is performed in the coprocessor.
The operation performed will be described in detail. Coprocessor during instruction execution
All self-configuration performed by the
Is implemented by reading / writing internal registers.
Therefore, the coprocessor is connected to the external C bus interface.
Interface or PCI bus interface by host
Is fully microprogrammable
is there. However, in microprogramming using the host
In some cases it can be difficult due to host synchronization issues
Is expected. This chapter is based on the reader
It is assumed that you have sufficient knowledge in this regard. 1. Execution model 2. 2. Instruction set and coding Register set 4. Internal structure A. 1 General A1.1 General about coprocessor setup
Item All except the control instruction and local DMA instruction
For instructions, the data flow in the coprocessor is based
It is essentially under the control of a pixel organizer. Pic
The cell organizer starts the first data stream in the input data stream.
Switch, data count, and last data fetch
Responsible for determining when it was done. Coproce
Other modules in the server are basically sent
It simply responds to the data. A1.2 Module configuration order All modules are set up for each instruction
is not. Some modules have instruction decoding
Sometimes not configured at all. module
Configuration order is always PO, DCC, OO
B, OOC, MDP, JC, RO, and PIC. A1.3 Other register settings If an instruction is coded including the setting of certain register values,
If the register is a microprogram that follows the following order:
This is set by the user. 1. Modules with registers to be set, other
If the register set does not exist in the
Is set before any register setting. 2. Modules with registers to be set, other
If there is also a register set, that register is
After register setting, _c of the module
It is set immediately before the fg register. A1.4 Coding of inconsistent instruction operands Many instructions have operands and result data types that are not specified.
Is specified, if another data type is specified
Returns a meaningless result. For each operand,
The processor follows this procedure to format the desired operand.
To decide. 1. The internal format of the operand is one pixel
(Compressed or uncompressed bytes)
In that case, the corresponding operand organizer
Set to reflect. The data cache controller is
Not configured, and therefore perform in normal mode.
The calculation is continued. 2. The internal format of the operand is "other format"
If the coprocessor is specialized for
Generate Peland format. Operand B and E
Perland C is progressive. Operand A
And other formats are not originally specified,
Sessa's behavior is undefined. Corresponding Opera
The organizer goes into bypass mode and the data
Flash controller is the format of the opera
Is set to manage data. Microprog
Ramming is reasonably independent of the various modules.
You. A1.5 Syntax of pseudo-instructions • Instruction execution order is determined by the leftmost number.・ Register name is Helvetica Bold
Have been. -The register field is register. field
Indicated by • I and D are the instruction word and data word currently being decoded.
Mode is shown. A, B and C are the operand words currently decoded
A, operand word B, and operand word C.・ A_descriptor, B_deskripto
r and C_descriptor are currently decoded
Indicates the descriptor of the data word of the current instruction. R indicates the result word of the instruction currently being decoded. "X: Y" indicates a connection between X and Y. "$ X" indicates the register number X of the coprocessor. "Cbus (X)" indicates execution of C bus operation X
Is shown.・ " ^* Cbus (X) "is based on C bus operation X.
Indicates the data received.・ " ^* X "indicates a virtual memory address X. ・"? ? "" Indicates an unknown or undecided value. ・ "Set" indicates the setting of the data manipulation register.
Shows the setting. A. 2 Composition operator Notes: 1. The main opcodes are 0xC and 0xD The ambiguity is due to the byte at the highest address (ie,
Byte). 3. The accumulator or operand is premultiplied
May be. 4. The result may be non-premultiplied. 5. The instruction length is defined by the number of input pixels. A. 3 Color space conversion Notes: 1. The input space is always three-dimensional. 3 by default
Is the channel of the lowest order pixel. Ambiguity is eliminated
It is. 2. The format of the color table is one output channel.
Channel or four output channels
Either. A. 4 JPEG instruction Notes: 1. The operation code is 0x2. 2. Operand C may be a register for yatt
No. 3. There are many options.・ Subsampling is performed / not performed.・ Perform / do not perform filtering. -1, 3 or 4 scans. 4. These instructions have a number of settings
Related to registers. A. 4.1 Extension Notes: 1. The following registers are set before instruction execution
There is a need.・ Ro_idr: output image dimension number register ・ ro_cut: output cut register ・ ro_lmt: output restriction register A. 4.2 Compression Notes: 1. The following registers must be set before executing the instruction
There is. • po_idr: output image dimension register • jc_rml: restart marker interval • ro_cut: output cut register • ro_lmt: output restriction register A. 5 Data coding Notes: 1. All data coding operations are compressed and decompressed
Both cases are treated the same. These operation settings
It is almost the same as JPEG. 2. Possible encoding operations • Huffman coding • Predictive coding Possible decoding operations • Fast Huffman decoding • Slow Huffman decoding • packbits decoding (version A) • packbits decoding (version B) • predictive decoding Operand C may be a register for setting. 5. The following registers must be set before executing the instruction
There is.・ Ro_cut: output cut register ・ ro_lmt: output limit register A. 6 Transformation and convolution The operation code is 0x4 (convolution) and 0x5 (conversion).
Exchange). 2. Coprocessor for image conversion and image convolution
Perform operations that are supersets required for
The only difference between image transformation and image convolution is that the coprocessor
As far as image conversion is concerned, the kernel step size is
The size of the tunnel (horizontal, vertical)
Means that the step size is one source pixel
It is. 3. Options: • Snapping and interpolation to neighboring pixels • Whether to accumulate pixels (kernel) • Whether to perform pre-multiplication of source pixels • Clamp, wrap, absolute value of final result Note: Transformation and convolution cannot be performed on the original position. One
In short, the source pointer and the destination point
If they are the same, their contents are destroyed. A. 7 Matrix multiplication Notes: 1. The operation code is 0x3. Options: • Whether or not to premultiply the source pixel. • Clamp, wrap, or absoluteize the final result. • Operand C may be written to a register. A. 8 Halftone processing Notes: 1. The operation code is 0x7 2. Option is only halftone level value. The halftone screen is properly meshed or
Pixels or bids as long as they are unmeshed
Can be done against A. 9 Memory copy Notes: 1. The operation code is 0x92. This instruction is a memory copy
Use completely separate mechanisms to complete the
You.・ General-purpose data transfer instructions are
Utilizing data flow, data manipulation user in PO and RO
Various functions using knits are available. • Peripheral DMA instructions are direct between PIC and LMC
Use a simple connection. This means that data manipulation
And cannot be executed simultaneously with the subsequent instruction.
You. A. 9.1 General-purpose data transfer A. 9.2 Peripheral DMA transfer Notes: 1. Simultaneous execution is not required. This means that I
Handled by C. 2. Operand C may be a register to be set. Since PIC is a module that handles data, this instruction
Is different from other "active" instructions. A. 10 Photo CD decompression This group of instructions has three different operations: horizontal interpolation, vertical
It consists of direct interpolation and rest fusion. Vertical interpolation and rest fusion
The setting method is the same. Opeco for all these instructions
The mode is 0x9. A. 10.1 Horizontal interpolation Notes: 1. Executable on pixel or byte This instruction is an instruction with one operand.
Command C may be a register to be set. A. 10.2 Vertical interpolation and rest fusion Notes: 1. The settings for vertical interpolation and remnant fusion are the same. 2. Can be performed on both pixels and bytes. 3. This instruction has two operands.
Command C may be a register set. A. 11 Control instructions Notes: 1. Control commands are two types of operations, namely flow control commands.
And an internal access instruction. A. 11.1 Flow control Notes: The operation code is 0xB. Flow control instructions are currently available for various jump instructions and various
Consists of wait instructions. 3. There is no explicit installation within the coprocessor and
Is not an "active" instruction. That is, other instructions
What is the submodule in the coprocessor actually like
Do not go. 4. Operand C may be a register to be set. A. 11.2 Internal access (read) Notes: 1. The operation code is 0xA. The read instruction transfers data out of the coprocessor. 3. RO is the only one that actually does everything in the coprocessor
Module. A. 11.3 Internal access (write) Notes: 1. The operation code is 0xA. Write instructions transfer data into the coprocessor. 3. Since this instruction is not an “active” instruction,
The module doesn't actually do anything. A. 12 Reserved instructions Notes: Operation codes 0x0 and 0xF are reserved. 2. Reserved instructions give maskable errors. 3. These reserved instructions will be revised by the coprocessor in the future
Will be used as other instructions when
I have. Appendix B: Registers 1.1 Registers and Tables This section describes the coprocessor registers. This
These registers can be modified in three ways. 1. Specific coprocessor instructions are read / write registers
I have to do it. By using these instructions,
The register starts the PIC bus cycle of the initiator.
Or using a generic interface transaction
The memory associated with the local memory interface
Reading from or writing to memory. 2. Many registers change contents due to the side effects of instruction execution.
Become The coprocessor configures itself for instruction execution
The main mechanism of doing is to make various registers current state
This is realized by setting to reflect. order
After execution, each register reflects the state of the coprocessor
I do. Many typical operations are completely specified by certain instructions
Is set. Some registers have instruction execution
Must be set immediately before. The meaning of the “reserved” register bits The meaning of “reserved” for any register or its components is
It is as follows.・ Writing to the reserved place is possible, but the data
Is rejected.・ Reading from the reserved place can be performed, but the data
Data is undefined All unspecified registers and register fields
"Do" is "reserved". 1.1.1 Register classification Registers in the coprocessor behave as described in this section.
Classified based on These descriptions are: • External: External (access from module). CBus
External access using an interface. Sand
Command controller or external CBus interface
Use the target-mode PCI. note,
Registers are accessed from the PCI bus via Biset mode
Cannot set.・ Internal: Module internal (access from) Status register The status register is read-only from the outside,
Readable and writable. Config 1 register The Config 1 register is readable and writable from outside,
It is read-only from the department. Config 1 register
Type C CBus operations are not supported (ie,
Set mode is not supported).
Unequal byte (or larger) configuration
It is used as a register that holds application information. Config 2 register The Config 2 register is also readable and writable from outside,
Is read-only from. Config 2 register
IBus CBus operation (ie bit set mode)
Support that must be set on a bit-by-bit basis
Used as a register to hold configuration information
It is. Control 1 register Control 1 register is read / write from outside and inside
Possible. The control 1 register is a type C CBus operation.
Operation is not supported (that is, bit set mode is not supported).
Bytes (or
As a register to hold larger control information
Used. Control 2 register Control 2 register is read / write from outside and inside
Possible. The control 2 register is a type C CBus operation.
(I.e. bit set mode)
Holds control information that must be set in
Used as a register. Interrupt register The bits in the interrupt register are set to 1 internally.
Reset to 0 by writing 1 from outside
it can. The module interrupt / error register also
Ip. The module interrupt / error register is
It consists of three fields. [7: 0] Any errors generated by the module
-Meaning of status (23: 8) Any example generated by the module
Means out state [31:24] Any generated by the module
1.1.2 Register Map Meaning Interrupt Status Table 1.1 shows coprocessor registers. Number is ad
Register number, not address. Table 1.1 Coprocessor registers 1.1.3 Register definitions General-purpose module registers Instruction Controller Register I. ic_cfg The ic_cfg register is divided into three parts. Lowest order
The site contains global configuration information.
The third byte from the bottom is the config of stream A.
And the most significant byte is stream B
Configuration information. This register
Is 0x0000000000. m. is_stat This register is divided into four sections. Bottom
The order byte holds the internal state of the IC. 2nd from bottom
The first byte contains the decoded result of the current instruction and the current and
Holds the prefetched instruction stream. Top?
The second byte contains all the steps for stream A.
Status information. Most significant byte in stream B
Holds information about The reset value of this register is 0
x00000000. n. ic_err int This register indicates that an interrupt or error has occurred inside the IC.
Contains an active high flag that indicates whether So
Each bit is cleared by writing 1. o. ic_err_int_en This register is a mask for enabling various errors and interrupts.
And the reset value is 0x00000000. p. ic_ipa This register is used to fetch stream A instructions.
Holds the most significant 30 bits of the virtual address. Two
The least significant bit is 0 if the instruction should be aligned
Is assumed. The reset value of this register is 0x000
00000. q. ic_tda This register holds the "to do" value of stream A
I do. This is 32 bits until the correct instruction exists
(Wrapping) sequence number. This register
Is 0x0000000000. r. ic_fna This register holds the “end” value of stream A.
This is a 32-bit (wrapping) sequence number with the highest
Indicates an instruction that was completed later. Reset this register
The default value is 0x0000000000. s. ic_inta This register holds the "interrupt" number of stream A
I do. This can happen if the mechanism is valid and available.
32 bit (wrapping) to interrupt here
Is the sequence number. The reset value of this register is
0x00000000. t. ic_loa This register is the last duplicate instruction executed on stream A.
Holds the 32-bit (wrapping) sequence number of the instruction
I do. The reset value of this register is 0x00000000
0. u. ic_ipb This register is used to fetch stream B instructions.
Holds the most significant 30 bits of the virtual address. Two
The least significant bit is the instruction should be aligned
Assume 0. The reset value of this register is 0x00
000000. v. ic_tdp This register holds the "to do" value of stream B
I do. This is 32 bits until the correct instruction exists
(Wrapping) number. Reset value of this register
Is 0x00000000. w. ic_fnb This register holds the “end” value of stream B.
This is a 32-bit (wrapping) sequence number with the highest
Indicates an instruction that was completed later. Reset this register
The default value is 0x0000000000. x. ic_intb This register holds the "interrupt" number of stream B
I do. This can happen if the mechanism is valid and available.
32 bit (wrapping) to interrupt here
Is the sequence number. The reset value of this register is
0x00000000. y. ic_lob This register is the last duplicate instruction executed on stream B.
Holds the 32-bit (wrapping) sequence number of the instruction
I do. The reset value of this register is 0x00000000
0. z. ic_sema This register uses the side effects of the ic_stat register.
The reading of this register is streamed.
This is a side effect of requesting the register semaphore of the program A. aa. ic_semb This register uses the side effect of the ic_stat register.
Reading this register is
This is a side effect of the request for the register semaphore in the B-mode. Input interface register ab. iis_cfg ac. iis_stat ad. iis_err_int ae. iis_err_int_en af. iis_ic_addr ag. iis_dcc_addr ah. iis_po_addr ai. iis_burst aj. iis_base_addr ak. iis_test External interface controller register al. eic_cfg am. eic_stat an. eic_err_int error and interrupt of eic_err_int register
Bits can only be set by the EIC,
Can be reset only by Normal errors and interrupts
A bit is reset by writing a 1 to it.
You. PCI configuration register bits
Error bits that are
Must be cleared by writing to the
No. That is, what is the copy in eic_err_int
Has no effect. ao. eic_err_int_en ap. eic_test aq. eic_pob ar. eic_high_addr as. eic_wtlb_v at. eic_wtlb_p au. eic_mmu_v Note: The value of this register is
Error due to PCI bus error from error or MMU
If not, you can change it at any time. av. eic_mmu_p Note: The value of this register is
Error due to PCI bus error from error or MMU
If not, you can change it at any time. aw. eic_ip_addr Note: The value of this register is
Can be changed at any time if it is not invalid due to errors in the source
It is. ax. eic_rp_addr Note: The value of this register is
Can be changed at any time, unless invalid due to errors in the source
Noh. ay. eic_ig_addr Note: Value of this register
If the GBC is not invalid due to a general bus error,
Can be changed at any time. az. eic_rg_addr Note: The value of this register is
If it is not invalid, you can change it at any time. Alias of PCI bus configuration space PCI bus configuration consisting of 16 words
Space is indicated by addresses from 0xc0 to 0xcf
Aliased to register. Local memory controller register ba. lmi_cfg This register determines the LMC processing mode and parameters
Many configuration bits used to
And control bits. When sdram_1 pin is high
Bits that specifically refer to SDRAM processing have no effect.
Not. This register has a clkin frequency of 80M
Hz is 3.2 microseconds refresh interval
It has such a reset value 0x20,000100. all
The special modes and features of the
All access rights are set equal to zero. Refresh
Is active at reset, but other modules
Invalid (E = 0). Refresh affects E bit
Not done. bb. lmi_stat The status register is a module as well as information inside the machine.
The active and undecided bits of the rule. Statema
Shin runs at twice the clock rate of the CBus interface.
Operating and therefore the latest 80 MHz clock 2
Two fields to hold status information for each vehicle
is necessary. bc. lmi_err_int Error and interrupt status registers are interrupts, examples
In addition, information on error status is retained. Register is read / write
Yes, the read returns status information,
Writing a 1 resets that bit. Writing 0
The embedding has no effect on that bit. This register has the reset value 0x00000000
Must be done, this is due to interrupts and errors
Indicates that there is not. Reserved bits are always 0 and never
Cannot change state. bd. lmi_err_int_en register Error, exception, and interrupt enable registers are
It is used to select the valid or invalid of the embedded signal. register
Can read and write. This register is lmi_err_i
error, exception, and interrupt in the nt register.
Therefore, it is used to enable in bit units. this
Register bits and lmi_err_int register
There is a one-to-one correspondence between bits. If lmi_e
A particular bit in the rr_int_en register goes high.
Once the corresponding bit in the lmi_err_int register
Is enabled and if it is high, the LMC module
Module error, exception or interrupt signal, c_er
r, c_exp, or c_int can occur. Also
Specific bits of the lmi_err_int_en register.
Lmi_err_int regis
Corresponding bit of the data becomes invalid, c_err, c_e
xp or c_int cannot be generated.
Since there is no exception in LMC, the exp_m
The ask bits have no effect and are all reserved. this
Register reset values are used for all error and interrupt sources.
Is 0x0000000000 to invalidate. Not used
Bit is always 0 and cannot be set high.
Absent. be. lmi_dcfg This configuration register is a DRAM chip
Determine the size and configuration when using
Holds design parameters to be specified. This register is
Reset to maximize all timing limit values.
Hold the default value 0x0007ff80. bf. lmi_mode register This configuration register is part of the initialization process.
Information written to the SDRAM mode register as a ring
Hold. This register is always readable and writable,
Write to SDRAM by setting
It's fine. This register stores the reset value 0x0037
Have. This useful default value is power-up precharge
It is required immediately after the reset of level 1 or after. This
This sets the read delay to 3 clocks and the burst length
Set to a full page using sequential wrap.
After any reset, if sdram_1 pin goes low
, The SDRAM mode register is initially programmed.
To program, the initialization bit is set. mode
After a register write, this bit is automatically set to zero.
Is cleared. Peripheral interface register bg. pic_cfg register bh. pic_stat bi. pic_err_int pic_err_int register errors and interrupts
Bit is set by PIC only
Reset only by Each bit is 1
Reset by writing bj. pic_err_int_en bk. pic_abus_cfg bl. pic_abus_addr bm. pic_cent_cfg The pic_cent_cfg register is a Centronics module.
All aspects of the interface when the mode is enabled
Read / write signal and read-only switch
Contains the status signal. bn. pic_cent_dir bo. pic_reverse_cfg bp. pic_timer0 bq. pic_timer1 Data cache controller register br. dcc_cfg1 bs. dcc_cfg2 bt. dcc_stat bu. dcc_err_int bv. dcc_err_int_en bw. dcc_lv0 bx. dcc_lv1 by. dcc_lv2 bz. dcc_lv3 ca. dcc_addr cb. dcc_raddrb cc. dcc_raddrc cd. dcc_test Operand organizer register Operand organizer
The same two operand organizers
Exists: operand organizer B and operand
-Organizer C. These two operand augers
The registers for the riser are described here. ce. oon_cfg (oob_cfg = 0x70,
ooc_cfg = 0x80) cf. oon_stat (oob_cfg = 0x7
1, ooc_cfg = 0x81) cg. oon_err_int (oob_err_i
(nt = 0x72, err_int = 0x82) ch. oon_err_int_en (oob_er
r_int_en = 0x73, err_int_en =
0x83) ci. oon_dmr (oob_dmr = 0x74,
ooc_dmr = 0x84) cj. oon_subst (oob_subst = 0)
x75, ooc_subst = 0x85) ck. oon_cdp (oob_cdp = 0x76,
ooc_cdp = 0x86) cl. oon_len (oob_len = 0x77,
ooc_len = 0x8 cm. oon_said (oob_said = 0x7
8, ooc_said = 0x88) cn. oon_tile (oob_tile = 0x7
9, ooc_tile = 0x89) Pixel organizer register co. po_cfg cp. po_stat cq. po_err_int cr. po_err_int_en cs. po_dmr ct. po_subst cu. po_cdp cv. po_len cw. po_said cx. po_idr cy. po_muv_valid cz. po_muv Main data path register da. mdp_cfg All bits are reset to 0.
Is db. mdp_stat All bits are reset to zero. dc. mdp_err_int All bits are reset to zero. dd. mdp_err_int_en All bits are reset to zero. de. mdp_test All bits reset to 0
Is set. df mdp_op1 All bits reset to 0
Is done. dg mdp_op2 All bits reset to 0
Is done. dh mdp_por All bits reset to 0
Is done. di mdp_bi All bits are reset to 0.
It is. The mdp_bi register contains various registers for various modes.
Used for dj mdp_bm All bits reset to 0
It is. The mdp_bm register is different for different modes.
Used for dk mdp_len All bits reset to 0
Be done JPEG encoder register dl jc_cfg dm jc_stat dn jc_err_int do jc_err_int_en dp jc_rsi dq jc_decode dr jc_res ds jc_table_sel Result organizer register dtro_cfg duro_stat dv ro_err_int dw ro_err_int_en dx ro_dmr dy ro_subst dz ro_cdp ea ro_len eb ro_sa ecro_idr ed ro_vbase ee ro_cut ef ro_lmt Alias of PCI configuration space PC
I configuration space is 256 bytes, PC
I is a block of registers defined by
Configure PCI devices,
I am allowed to read the condition. It is PC
Accessed using the I configuration cycle
It is. The registers also read the internal memory of the coprocessor.
Is mirrored in the dedicated
It can be read using normal memory cycles. EIC
Configuration space format implemented in
The mat is shown in Table 1.141.1. Table 1.141.1 Spatial level of coprocessor PCI configuration
I-out Reserved registers and reserved registers in implemented registers
Returns 0 for reads and 0 for writes.
Has no effect. Configuration in the range 0x40-0xff
Regulation space addresses are also reserved. Ben
Configuration registers specific to the
Absent. eg vendor ID This register is read-only. Ben of CISRA
The header ID is 0x11AC. eh Device ID This register is read-only. Coprocessor data
The device ID is 0x0001. Device ID fee
The field is divided into two 8-bit fields:
The most significant 8 bits are numbers (0x) indicating the characteristics of the device.
0 is a coprocessor) and the least significant 8 bits are
Version number (0x1 is the version of the coprocessor)
). ei Command register Table 1.142 defines the fields of the command register.
Show. All unreserved bits in this register
Can read / write. After reset,
The register is set to 0x0000. ej Status register Status register file
The definition of the field is shown in Table 1.143. Reading this register
Imprinting is as usual. Some registers in this register
The set is read-only. Other bits are coprocessor
Set to 1 by the server only, 0 by the host only
Reset (except in test mode). The host
Reset by writing 1 to bit; write 0
The meaning does not make sense. After reset, this register
It is set to 0x0280. ek revision ID This is a read-only register
It is. The initial revision ID of the coprocessor is 0x01
It is. el class code This is a read-only
It is a register. Coprocessor is defined by PCISIG
This register is 0xF
Set to F0000. em Cache line size This is the system cache line size in 32-bit words.
This is a readable / writable register that determines the in-size.
This is because the coprocessor uses memory read lines and memory
Determined when using the double read command. Copro
Sessa supports values from 0 to 255 in this register.
To 0 in this register is the memory read line.
Disables the format of memory and memory multiplex reading. this
The register is set to 0x00 at reset. en Delay timer This register is used by the CPU for all PCI processing.
Readable and writable registers that specify the maximum number of clocks
It is. The coprocessor sets 0 to 2 in this register.
Supports 55 values. This register is reset
Is set to 0x00. eo header type This read-only register is set to 0x00
You. This means that the coprocessor has a type 0 layout
Means using configuration space
You. ep base address This readable and writable register is the internal register of the coprocessor.
Memory, internal memory, local memory, and general-purpose interface.
Used to place faces in the host memory map
Can be. 64 MB of coprocessor resources
(Not all are used) and therefore
Only the first 6 bits of the register can be written.
The remaining bits are all hardwired to zero.
The lower 4 bits of this register are read-only control
And these are also connected to zero. this child
Means that registers refer to memory space,
The processor can be mapped anywhere in the host's 32-bit space.
And coprocessor resources are targeted
Sometimes it means that prefetching is not possible. eq Subsystem vendor ID This read-only register is implemented by the host on the system.
To identify the PCI board vendor
(Component mounted on PCI interface on board
Component vendors). The contents of this register are
EIC configuration serial port at reset
Loaded using the er Subsystem ID This read-only register is implemented by the host in the system.
PCI boards that have been assigned. This Regis
Data is reset when reset
Loaded using serial port. This mechanism
Required for board function or configuration
External information and read from host
Enable. es Interrupt line These registers are readable and writable by the system software.
Enable recording of interrupt line routing information
Used by interrupt service software
Can access. Has no effect on the processing in the coprocessor
Do not give. This register is set to 0x00 at reset.
Is set. et interrupt pin This read-only register is hardwired to 0x01
Have been. This means that the coprocessor is
Indicates that the a_1 interrupt pin is to be used. eu Min_Gnt This read-only register is the one requested by the coprocessor.
The burst period length in units of / 4 microsecond is indicated to the host.
The optimal value for this register has not yet been determined. ev Max_Lat This read-only register is in 1/4 microsecond units
Of the PCI bus required by the coprocessor
Indicate the maximum roll delay to the host. Optimal for this register
The value has not been determined yet. 1.1.4 Internal memory map In this section, the pre-
Details of the objects that occur in the rule data area.
State. 1.1.5 Memory word field a eic_ptp

[Brief description of the drawings]

FIG. 1 illustrates the operation of a raster image coprocessor in a host computer environment.

FIG. 2 shows the raster image coprocessor of FIG. 1 in more detail;

FIG. 3 is a diagram showing a memory map of a raster image coprocessor.

FIG. 4 is a diagram showing a relationship among a CPU, an instruction queue, instruction operands, a result in a shared memory, and a coprocessor;

FIG. 5 shows an instruction generation unit, a memory management unit, a queue management unit,
Diagram showing relationships between coprocessors

FIG. 6 is a diagram illustrating an operation of a graphics coprocessor that reads an instruction from a pending instruction queue and arranges the instruction in an end instruction queue.

FIG. 7 illustrates a fixed-length circular buffer implementation of an instruction queue and illustrates the need to wait until the buffer overflows.

FIG. 8 is a diagram showing an instruction execution stream used in a coprocessor.

FIG. 9 is an instruction execution flowchart,

FIG. 10 is a diagram showing a standard instruction word format used in a coprocessor.

FIG. 11 is a diagram showing an instruction word field of a standard instruction.

FIG. 12 shows a data word field of a standard instruction.

FIG. 13 is a diagram schematically showing the instruction control unit in FIG. 2;

FIG. 14 is a diagram showing the execution control unit of FIG. 13 in more detail;

FIG. 15 is a state transition diagram of the instruction control unit.

FIG. 16 is a diagram illustrating an instruction decoding unit in FIG. 13;

17 is a diagram showing the instruction sequencer of FIG. 16 in more detail;

18 is a state transition diagram of the ID sequencer in FIG.

FIG. 19 is a diagram showing the prefetch buffer control unit in FIG. 13 in more detail;

FIG. 20 is a diagram showing a standard format of register storage and inter-module relations used in a coprocessor.

FIG. 21 is a diagram showing a format of control bus processing used in the coprocessor.

FIG. 22 is a diagram showing a data flow in a part of the coprocessor.

FIG. 23 shows examples of various data reformatting used in a coprocessor.

FIG. 24 illustrates various data reformatting examples used in the coprocessor.

FIG. 25 illustrates various data reformatting examples used in a coprocessor.

FIG. 26 illustrates various data reformatting examples used in the coprocessor.

FIG. 27 illustrates various data reformatting examples used in the coprocessor.

FIG. 28 illustrates various data reformatting examples used in the coprocessor.

FIG. 29 is a diagram showing various data reformatting examples used in the coprocessor.

FIG. 30 is a diagram showing a format conversion performed in the coprocessor.

FIG. 31 is a diagram illustrating format conversion performed in a coprocessor.

FIG. 32 is a diagram showing input data conversion processing executed in the coprocessor.

FIG. 33 shows various data transformations performed in the coprocessor.

FIG. 34 illustrates various data transformations performed in the coprocessor.

FIG. 35 illustrates various data transformations performed in the coprocessor.

FIG. 36 illustrates various data transformations performed in the coprocessor.

FIG. 37 illustrates various data transformations performed in the coprocessor.

FIG. 38 illustrates various data conversions performed in the coprocessor.

FIG. 39 illustrates various data conversions performed in the coprocessor.

FIG. 40 illustrates various data transformations performed in the coprocessor.

FIG. 41 illustrates various data conversions performed in the coprocessor.

FIG. 42 illustrates various internal to output data conversions performed in the coprocessor.

FIG. 43 is a diagram showing various data conversion examples executed in the coprocessor.

FIG. 44 is a diagram showing various data conversion examples executed in the coprocessor.

FIG. 45 is a diagram showing various data conversion examples executed in the coprocessor.

FIG. 46 is a diagram showing various data conversion examples executed in the coprocessor.

FIG. 47 is a diagram showing various data conversion examples executed in the coprocessor.

FIG. 48 illustrates various fields used in internal registers to determine which data conversion is to be used.

FIG. 49 is a block diagram of a graphics subsystem using data normalization.

FIG. 50 is a circuit diagram of a data normalization device.

FIG. 51 is a diagram showing pixel processing performed in the synthesis processing.

FIG. 52 is a diagram showing an instruction word format for a combining process;

FIG. 53 is a view showing a data word format for a combining process;

FIG. 54 shows an instruction word format for tile processing.

FIG. 55 is a view showing the operation of a tile instruction for an image.

FIG. 56 is a diagram showing use processing of a color section / in-section position table for remapping color values;

FIG. 57. Sections in MUV buffer of coprocessor /
Diagram showing the storage format of the section position table

FIG. 58 is a diagram showing a color conversion process using interpolation executed in the coprocessor.

FIG. 59 is a diagram showing an improvement process of a color conversion process at an edge executed in the coprocessor.

FIG. 60 is a diagram showing a color space conversion process for one output color executed in the coprocessor.

FIG. 61 illustrates memory storage in a cache of a coprocessor when using single color output color space conversion.

FIG. 62 is a diagram showing a technique used in multiple color space conversion.

FIG. 63 is a diagram showing an address remapping process for a cache used in a multiple color space conversion process;

FIG. 64 is a diagram showing an instruction word format in a color space conversion instruction.

FIG. 65 is a diagram showing a multiple color conversion method.

FIG. 66 is an exemplary view for explaining generation of an MCU in JPEG conversion processing executed by a coprocessor;

FIG. 67 is a view for explaining generation of an MCU in JPEG conversion processing executed by the coprocessor.

FIG. 68 is a view showing the structure of a JPEG encoding unit of the coprocessor.

FIG. 69 is a diagram showing the quantization unit of FIG. 68 in more detail;

FIG. 70 is a diagram showing the Huffman encoding unit of FIG. 68 in more detail;

FIG. 71 is a diagram showing a Huffman encoding unit and a decoding unit;

FIG. 72 is a diagram showing a Huffman encoding unit and a decoding unit;

FIG. 73 is a view for explaining JPEG data deletion / constraint processing used in the coprocessor.

FIG. 74 is a view for explaining deletion / constraint processing of JPEG data used in the coprocessor.

FIG. 75 is a view for explaining JPEG data deletion / constraint processing used in the coprocessor.

FIG. 76 shows an instruction word format of a JPEG instruction.

FIG. 77 is a block diagram of a general discrete cosine transform device (conventional example);

FIG. 78 is a diagram showing an arithmetic data path of a DCT device of a conventional example.

FIG. 79 is a block diagram of a DCT device used in a coprocessor.

FIG. 80 is a block diagram showing the arithmetic circuit of FIG. 79 in more detail;

FIG. 81 is a view showing an arithmetic data path of the DCT device of FIG. 79;

FIG. 82 is a diagram showing typical Huffman encoded data in which bit fields that are not encoded as in the JPEG format (ones that are not byte-aligned) are interleaved.

FIG. 83 is a diagram showing the overall structure of the Huffman decoding unit for JPEG data in FIG. 84 in more detail;

FIG. 84 is a view showing the overall structure of a Huffman decoding unit for JPEG data

FIG. 85 shows data processing in a stripper block for removing a byte-aligned uncoded bit field from input data, and also shows an example of a tag code corresponding to data output from the stripper.

FIG. 86 is a view showing the configuration and data flow of a data pre-shifter

FIG. 87 shows a control logic of the decoding unit in FIG. 81.

FIG. 88 is a diagram showing the configuration and data flow of a marker pre-shifter.

FIG. 89 is a block diagram of a combination circuit for decoding a Huffman code value in JPEG encoding;

FIG. 90 is a block diagram of the concept of a padding area and a padding bit decoding unit.

Fig. 91 is a diagram illustrating an example of a data format output from a decoding unit and used in a coprocessor.

FIG. 92 is a diagram showing a technique used in an image conversion instruction.

FIG. 93 shows an instruction word format in an image conversion instruction.

FIG. 94 is a diagram showing a format of an image conversion kernel used in the coprocessor.

FIG. 95 is a diagram showing a format of an image conversion kernel used in the coprocessor.

FIG. 96 is a diagram showing processing for using an index table for image conversion used in the coprocessor.

FIG. 97 is a view showing a data field format for an instruction used in conversion or convolution;

FIG. 98 is an explanatory diagram of a bp field of an instruction word.

FIG. 99 shows a convolution process used in the coprocessor.

FIG. 100 is an instruction word format diagram of a convolution instruction used in a coprocessor.

FIG. 101 is an instruction word format diagram of matrix multiplication used in the coprocessor,

FIG. 102 is a view showing a hierarchical image manipulation process used in the coprocessor.

FIG. 103 is a view showing a hierarchical image operation process used in the coprocessor.

FIG. 104 is a view showing a hierarchical image manipulation process used in the coprocessor.

FIG. 105 is a view showing a hierarchical image operation process used in the coprocessor.

FIG. 106 is a view showing an instruction word code in a hierarchical image instruction.

FIG. 107 is a diagram showing an instruction word code of a flow control instruction used in the coprocessor.

FIG. 108 shows the pixel organizer in more detail.

FIG. 109 is a diagram showing the operand fetch unit in the pixel organizer in more detail;

FIG. 110 shows various storage formats used in the coprocessor.

FIG. 111 shows various storage formats used in the coprocessor.

FIG. 112 shows various storage formats used in the coprocessor.

FIG. 113 shows various storage formats used in the coprocessor.

FIG. 114 shows various storage formats used in the coprocessor.

FIG. 115 is a diagram showing the MUV address generator in the pixel organizer of the coprocessor in more detail;

FIG. 116 shows a multiple value (MU) used in the coprocessor.
V) Block diagram of buffer

117 shows the structure of the encoder in FIG. 116.

118 shows the structure of the decoder in FIG. 116.

FIG. 119 is a view showing the structure of the address generation unit shown in FIG. 116 for generating a read address in the JPEG mode (pixel decomposition).

FIG. 120 is a diagram showing the structure of the address generation unit in FIG. 116 that generates a read address in the JPEG mode (pixel restoration).

FIG. 121 illustrates a configuration of a memory module including the storage device in FIG. 116.

FIG. 122 is a diagram showing a structure of a circuit for multiplexing a read address in a memory module;

FIG. 123 illustrates how a lookup table entry is stored in a buffer operating in a single lookup table mode.

FIG. 124 illustrates how a lookup table entry is stored in a buffer operating in a multiple lookup table mode.

FIG. 125 shows how pixels are stored in a buffer operating in JPEG mode (pixel decomposition)

FIG. 126 shows how a single color is stored from a buffer operating in JPEG mode (pixel recovery)

FIG. 127 shows the structure of the result organizer of the coprocessor in more detail.

FIG. 128 shows the structure of the operand organizer of the coprocessor in more detail.

Fig. 129 is a block diagram of a computer architecture for a main data path unit used in the coprocessor.

FIG. 130 is a block diagram of an input interface for receiving, storing, and rearranging input data objects for further processing.

FIG. 131 is a block diagram of an image data processor for performing arithmetic operations on input data objects.

FIG. 132 is a block diagram of a color channel processor for performing arithmetic operations on one channel of an input data object.

FIG. 133 is a block diagram of a multi-function block in the color channel processor.

FIG. 134 is a block diagram for a combining operation.

FIG. 135 is a view showing an inverse scan line conversion;

FIG. 136 is a block diagram of the steps required to calculate a value at a specified pixel.

Fig. 137 is a block diagram of an image conversion engine.

FIG. 138. Kernel Descriptor 2
Diagram showing two formats

Fig. 139 is a diagram showing the definition and interpretation of a bp field.

FIG. 140 is a block diagram of a multiplication / addition unit that performs matrix multiplication

FIG. 141 is a diagram showing a control, an address, and a data flow in a cache and a cache control unit in a coprocessor.

FIG. 142 is a diagram showing a memory configuration of a cache;

FIG. 143 is a diagram showing an address format for a cache control unit in the coprocessor.

FIG. 144 is a block diagram of a multi-function block in the color channel processor.

FIG. 145 illustrates a coprocessor input interface switch of the cache and cache controller of FIG. 144.

FIG. 146 is a diagram showing a 4-port dynamic local memory control unit of the coprocessor showing a main address and a data path.

FIG. 147 is a state mechanism diagram of the control unit in FIG. 146;

FIG. 148 shows a pseudo code listing in detail the functions in the arbitration unit of FIG. 146

FIG. 149 is a diagram showing the structure and terminology of a requester priority bit used in FIG. 146.

FIG. 150 is a diagram showing the external interface control unit in the coprocessor in more detail.

FIG. 151 is a diagram showing a mapping process to a physical address or a mapping process from a physical address used in the coprocessor.

FIG. 152 is a diagram showing a mapping process to a physical address or a mapping process from a physical address used in the coprocessor.

FIG. 153 is a diagram showing a mapping process to a physical address or a mapping process from a physical address used in the coprocessor.

FIG. 154 is a diagram illustrating mapping processing to a physical address or mapping processing from a physical address used in the coprocessor.

155 is a diagram showing the IBus receiving unit in FIG. 150 in more detail;

156 is a diagram showing the RBus receiving unit in FIG. 2 in more detail;

157 is a diagram showing the memory management unit in FIG. 150 in more detail;

FIG. 158 is a diagram showing the peripheral interface control unit in FIG. 2 in more detail;

 ────────────────────────────────────────────────── ─── Continuing from the front page (71) Applicant 000001007 Canon Inc. 3-30-2 Shimomaruko, Ota-ku, Tokyo (72) Inventor Tomas Thomas Prokop Australia 2150 Paramatti, New South Wales 13 Campbell Street / 15 (72) Inventor Trevor Robert Elbourne Australia 2094 Fairlight, Hilltop Crescent, New South Wales 5/54 (72) Inventor Mark Pullbar Australia 2042 Enmore, New South Wales Trafalgar Street 15

Claims (25)

[Claims] An apparatus for decoding a plurality of data blocks encoded with a plurality of variable length codes interleaved with variable length uncoded bit fields and having a plurality of fixed length uncoded fields, Removing a plurality of fixed-length uncoded fields, the plurality of variable-length codes interleaved with the variable-length uncoded bit fields and the variable-length uncoded bit fields, and the plurality of data blocks in a plurality of data blocks; A preprocessing unit that outputs a plurality of position signals indicating the positions of the fixed-length uncoded fields, and the decoded data of the variable-length coded data that is input between the fixed-length uncoded fields, Synchronizing the position signal with the data to be decoded, so as to be output from the decoding device during the position signal corresponding to the long uncoded field Decoding apparatus characterized by comprising a means for delivering the part device. 2. A first processing unit having a first barrel shifter set and a first register, the first processing unit processing the plurality of variable length codes interleaved with the variable length uncoded bit field, and a second barrel shifter. A second processing unit that has a set and a second register, and that processes a plurality of position signals indicating positions of the plurality of fixed-length uncoded fields in a plurality of data blocks; The decoding device according to claim 1, wherein two processing units are the same, and outputs of the first and second barrel shifter sets and the first and second processing units receive the same control signal. 3. An uncoded variable-length field, wherein an output of the second processing unit for processing a position signal indicating a position of the fixed-length uncoded field is removed from data stored in a data register at the time of decoding. 3. The decoding device according to claim 2, wherein the decoding device is used for determining the size of the decoding data. 4. The pre-processing unit removes a plurality of fixed-length uncoded fields, and interleaves the plurality of variable-length uncoded bit fields and the plurality of variable-length uncoded bit fields. The code is defined as a plurality of fixed-length codes consisting of a plurality of fixed-length bit fields, and one fixed-length bit field is passed or removed in the pre-processing field, and is passed in the pre-processing field. 2. The decoding apparatus according to claim 1, further comprising a tag indicating any one of the tags, and outputting the tag such that the tag exists before or after a marker indicating a fixed-length uncoded field. 5. The decoding device according to claim 1, wherein said data block is Huffman-coded. 6. A method for decoding a plurality of data blocks encoded by a plurality of variable length codes interleaved with variable length uncoded bit fields and having a plurality of fixed length uncoded fields. Removing a plurality of fixed-length uncoded fields, the plurality of variable-length codes interleaved with the variable-length uncoded bit fields and the variable-length uncoded bit fields, and the plurality of data blocks in a plurality of data blocks; A pre-processing step of outputting a plurality of position signals indicating the position of the fixed-length uncoded field, and the decoded data of the variable-length coded data input between the fixed-length uncoded fields, The position signal is synchronized with the data to be decoded so that it is output from the decoding device during the position signal corresponding to the long uncoded field. Decoding method characterized by not including a step of sending to the external device. 7. Processing the plurality of variable length codes interleaved with the variable length uncoded bit field using a first processing unit having a first barrel shifter set and a first register; Second barrel shifter set having a second register and a second register
Processing a plurality of position signals indicating positions of the plurality of fixed-length uncoded fields in a plurality of data blocks using a processing unit, wherein the first and second processing units are the same. 7. The decoding method according to claim 6, wherein the outputs of the first and second barrel shifter sets and the first and second processing units receive the same control signal. 8. An uncoded variable removed from data stored in a data register at the time of decoding in accordance with an output of the second processing unit which processes a position signal indicating a position of the fixed-length uncoded field. The method of claim 7, further comprising determining a size of the long field. 9. The method according to claim 1, wherein in the preprocessing step, a plurality of fixed-length uncoded fields are removed, and the plurality of variable-length uncoded bit fields are interleaved with the variable-length uncoded bit fields. A long code as a plurality of fixed-length codes consisting of a plurality of fixed-length bit fields, and that one fixed-length bit field has been passed or removed in the pre-processing field and has been passed in the pre-processing field. 7. The decoding method according to claim 6, further comprising a tag indicating any one of the following: and outputting the tag such that the tag exists before or after a marker indicating a fixed-length uncoded field. 10. The decoding method according to claim 6, wherein said data block is Huffman-coded. 11. A discrete cosine transform (DCT) device, comprising a transposed matrix storage means and a combination circuit interconnected with the transposed matrix storage means for performing a DCT operation without using a clocked storage means. A DCT device having a circuit. 12. The DCT apparatus according to claim 11, wherein the combination circuit has a predetermined number of stages for performing a DCT operation, and the stages are sequentially arranged. 13. The DCT apparatus according to claim 11, further comprising multiplexing means for multiplexing data input to said DCT apparatus and an output of said transposed matrix storage means. 14. The DCT device according to claim 11, further comprising control means for controlling an operation of the DCT device. 15. An inverse discrete cosine transform (DCT) device, comprising: transposed matrix storage means; interconnected with said transposed matrix storage means;
Inverse DC having an arithmetic circuit whose main component is a combinational circuit for performing a DCT operation without using storage means
T device. 16. The inverse DCT apparatus according to claim 15, wherein the combination circuit has a predetermined number of stages for performing an inverse DCT operation, and the stages are sequentially arranged. 17. The inverse DCT apparatus according to claim 15, further comprising multiplexing means for multiplexing data input to said inverse DCT apparatus and an output of said transposed matrix storage means. 18. The inverse DCT device according to claim 15, further comprising control means for controlling an operation of the inverse DCT device. 19. A discrete cosine transform (DCT) of the data.
A method for performing a DCT operation on input data in accordance with a first direction by using an operation circuit mainly including a combination circuit that performs a DCT operation without clocked storage means; Storing the data stored in the transposed matrix storage means in the second direction using the arithmetic circuit; and storing the data stored in the transposed matrix storage means in the second direction in accordance with the first direction. DCT operation to obtain transformed data. 20. The D according to claim 19, wherein the DCT is calculated in a predetermined number of stages arranged sequentially.
CT method. 21. The method according to claim 19, further comprising the step of multiplexing input data and an output of said transposed matrix storage means.
The described DCT method. 22. An inverse discrete cosine transform (DCT) method using an arithmetic circuit mainly composed of a combinational circuit for performing an inverse DCT operation without clocked storage means, and adjusting an input coefficient in the first direction. Performing a DCT operation; storing the input coefficient subjected to the DCT in the transposed matrix storage means interconnected with the combinational circuit in accordance with the first direction; Performing an inverse DCT operation on the stored coefficients according to the second direction to obtain inverse transformed data. 23. The inverse DCT method according to claim 22, wherein the inverse DCT is calculated in a predetermined number of stages arranged sequentially. 24. The method according to claim 22, further comprising the step of multiplexing input data and an output of said transposed matrix storage means.
The described inverse DCT method. 25. Claims 6 to 10 and 19 to 2
A storage medium that stores the method according to any one of claims 4 as program code executable by a computer.