JPH11122056A - Offset compensating circuit - Google Patents
Offset compensating circuitInfo
- Publication number
- JPH11122056A JPH11122056A JP9317581A JP31758197A JPH11122056A JP H11122056 A JPH11122056 A JP H11122056A JP 9317581 A JP9317581 A JP 9317581A JP 31758197 A JP31758197 A JP 31758197A JP H11122056 A JPH11122056 A JP H11122056A
- Authority
- JP
- Japan
- Prior art keywords
- input
- differential amplifier
- output
- voltage
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
- Amplifiers (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はホール素子やオペアンプ
等を用いたセンシング回路のオフセット補償に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to offset compensation of a sensing circuit using a hall element, an operational amplifier and the like.
【0002】[0002]
【従来の技術】コアにコイルを巻いてコイルに流した電
流に比例した磁束を前記コア内部に発生させて、その磁
束をホール素子で検出してその信号を電圧に変換する電
流センサが開発されている。これに用いられるホール素
子は製造上のバラツキからその入力である磁束がゼロで
あっても発生してしまうオフセット電圧が存在する。こ
のオフセット電圧を補償する為に従来は図3に示す様に
基準電圧発生器としてツェナーダイオード21、22を
用いて、その電圧を可変抵抗器23で調整してその出力
を加算回路8を介して差動アンプに入力して補償してい
た。2. Description of the Related Art A current sensor has been developed in which a coil is wound around a core and a magnetic flux proportional to a current flowing through the coil is generated inside the core, the magnetic flux is detected by a Hall element, and the signal is converted into a voltage. ing. The Hall element used therein has an offset voltage which is generated even if the magnetic flux which is the input is zero due to manufacturing variations. Conventionally, in order to compensate for this offset voltage, as shown in FIG. 3, Zener diodes 21 and 22 are used as reference voltage generators, the voltage is adjusted by a variable resistor 23, and the output is added via an adder circuit 8. Input to the differential amplifier to compensate.
【0003】[0003]
【発明が解決しようとする課題】近年、電流センサの用
途が拡大しそれを使用する時の電源電圧も±5Vと言う
低い要求がある。この様な要求に対して従来の基準電圧
発生器としてツェナーダイオードを用いたオフセット補
償回路では、電源電圧変動によるオフセット電圧の変動
が大きく残ってしまうと言う問題があった。この本質的
な問題はツェナーダイオード自身が低電圧になると安定
度が劣化する事に起因する。In recent years, the use of current sensors has expanded, and there is a demand for a low power supply voltage of ± 5 V when using them. In response to such a demand, a conventional offset compensation circuit using a Zener diode as a reference voltage generator has a problem that a large fluctuation in offset voltage due to a fluctuation in power supply voltage remains. This essential problem arises from the fact that the stability is degraded when the Zener diode itself has a low voltage.
【0004】[0004]
【課題を解決するための手段】本発明はこれらの課題を
解決するため次のような回路にしたものである。正と負
の電源の間に接続された基準電圧発生器の出力を第1の
差動アンプに入力し、その出力を第2の差動アンプのプ
ラスとマイナスに入力する事を特徴とするオフセット補
償回路。The present invention has the following circuit to solve these problems. An offset characterized in that the output of a reference voltage generator connected between a positive and a negative power supply is input to a first differential amplifier, and the output is input to a plus and a minus of a second differential amplifier. Compensation circuit.
【0005】[0005]
【作用】正と負の電源の間に接続された基準電圧発生器
は電源電圧変動に対して同相成分の電圧変動を発生す
る。これを第1の差動アンプに入力する。するとその出
力は差動アンプの同相信号除去比により電源電圧変動の
影響を受けない基準電圧発生器の電圧のみが発生する。
これを第2の差動アンプのプラスとマイナスに入力する
比率を変える事によりオフセット電圧をプラスからマイ
ナスに補償する事が出来る。The reference voltage generator connected between the positive and negative power supplies generates a voltage fluctuation of an in-phase component with respect to the power supply voltage fluctuation. This is input to the first differential amplifier. Then, only the voltage of the reference voltage generator, which is not affected by the power supply voltage fluctuation, is generated from the output due to the common mode signal rejection ratio of the differential amplifier.
The offset voltage can be compensated from positive to negative by changing the ratio of the positive and negative inputs of the second differential amplifier.
【0006】[0006]
【実施例】以下図面を参照して本発明の実施例を説明す
る。図1は本発明のオフセット補償回路を用いた電流セ
ンサの実施例であり、 1は第1の差動アンプ 2は第2の差動アンプ 3は基準電圧発生用のツェナーダイオード 4は抵抗 5はホール素子 6、7はアッテネーション回路 8、9は加算回路 10は定電流回路 である。尚Vccは正の電源、Veeは負の電源であ
る。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a current sensor using an offset compensation circuit according to the present invention. 1 is a first differential amplifier 2 is a second differential amplifier 3 is a Zener diode for generating a reference voltage 4 is a resistor 5 Hall elements 6 and 7 are attenuation circuits 8 and 9 are addition circuits 10 are constant current circuits. Vcc is a positive power supply, and Vee is a negative power supply.
【0007】図1の様にツェナーダイオード3のカソー
ドはVccに接続され、ツェナーダイオード3のアノー
ドは抵抗4のある端子に接続され、抵抗4の他端はVe
eに接続される。Vcc=+5V、Vee=−5Vとす
ると10Vの電圧があるのでツェナーダイオード3には
特性の良い5.1Vが使用出来る。As shown in FIG. 1, the cathode of the Zener diode 3 is connected to Vcc, the anode of the Zener diode 3 is connected to a terminal having a resistor 4, and the other end of the resistor 4 is connected to Ve.
e. Assuming that Vcc = + 5V and Vee = -5V, there is a voltage of 10V, so that 5.1V having good characteristics can be used for the Zener diode 3.
【0008】ツェナーダイオード3のアノードを差動ア
ンプ1のプラス入力に、ツェナーダイオード3のカソー
ドを差動アンプ1のマイナス入力に接続する。従って、
差動アンプ1の出力電圧は電源Vcc,Veeの変動の
影響を受けない安定な基準電圧が発生する。これをアッ
テネーション回路6、7に入力してそれぞれの出力を加
算回路8、9に入力する。ここでホール素子への鎖交磁
束がゼロの時に発生するオフセット電圧をキャンセルす
る様に前記アッテネーション回路6、7の減衰量を調整
すれば電源電圧変動を受けないオフセット調整回路が実
現できる。The anode of the Zener diode 3 is connected to the positive input of the differential amplifier 1, and the cathode of the Zener diode 3 is connected to the negative input of the differential amplifier 1. Therefore,
The output voltage of the differential amplifier 1 generates a stable reference voltage which is not affected by fluctuations of the power supplies Vcc and Vee. This is input to attenuation circuits 6 and 7, and the respective outputs are input to adders 8 and 9. Here, if the attenuation of the attenuation circuits 6 and 7 is adjusted so as to cancel the offset voltage generated when the flux linkage to the Hall element is zero, an offset adjustment circuit that is not affected by the power supply voltage can be realized.
【0009】一方、ツェナーダイオード3のアノードと
カソードは定電流回路10にも接続されこの入力電圧を
基準として電流を発生する。定電流回路の出力はホール
素子5の入力端子11に接続され、その反対側の入力端
子13はVeeに接続されてホール素子5は定電流駆動
される。これは一般にホール素子の感度の温度特性が定
電流駆動した方が安定する為に行うものである。On the other hand, the anode and cathode of the Zener diode 3 are also connected to a constant current circuit 10 to generate a current based on the input voltage. The output of the constant current circuit is connected to the input terminal 11 of the Hall element 5, and the input terminal 13 on the opposite side is connected to Vee, so that the Hall element 5 is driven with a constant current. This is generally performed in order to stabilize the temperature characteristic of the sensitivity of the Hall element when driven by a constant current.
【0010】この様にホール素子を定電流駆動してお
き、磁束がホール素子に鎖交すると、いわゆるホール効
果によりホール電圧Vhがホール素子5の出力端子1
2、14間に発生する。これを第2の差動アンプに入力
して増幅すればホール素子に鎖交した磁束に比例した電
圧が得られる。これを利用してコアにコイルを巻いてコ
イルに流した電流に比例した磁束を前記コア内部に発生
させて、その磁束をホール素子で検出させれば電流セン
サが構成出来る。As described above, when the Hall element is driven at a constant current and the magnetic flux is linked to the Hall element, the Hall voltage Vh is changed to the output terminal 1 of the Hall element 5 by the so-called Hall effect.
Occurs between 2 and 14. If this is input to the second differential amplifier and amplified, a voltage proportional to the magnetic flux linked to the Hall element can be obtained. By utilizing this, a magnetic flux proportional to the current flowing through the coil by winding the coil around the core is generated inside the core, and the magnetic flux is detected by a Hall element, whereby a current sensor can be configured.
【0011】図2に実際の回路図を示す。この回路によ
り、実現したオフセット電圧の電源電圧変動特性を図4
に示す。電源電圧変動特性は約±30mV以内であれば
実用に十分であり、図4はこれを満足している事がわか
る。尚、本発明は従来に比べ基準電圧源としてのツェナ
ーダイオードが1つで良い為、生産コスト低減に貢献す
るものである。FIG. 2 shows an actual circuit diagram. FIG. 4 shows the power supply voltage fluctuation characteristic of the offset voltage realized by this circuit.
Shown in If the power supply voltage fluctuation characteristic is within about ± 30 mV, it is sufficient for practical use, and FIG. 4 shows that this is satisfied. It should be noted that the present invention contributes to a reduction in production cost because only one zener diode is required as a reference voltage source as compared with the related art.
【0012】[0012]
【発明の効果】以上詳細に説明したように本発明によれ
ば低電源電圧時にも、電源電圧変動の影響を受けずにオ
フセット電圧の調整が可能になる。As described above in detail, according to the present invention, even at a low power supply voltage, the offset voltage can be adjusted without being affected by the power supply voltage fluctuation.
【図1】本発明の実施例の回路構成図FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.
【図2】本発明の実施例の回路図FIG. 2 is a circuit diagram of an embodiment of the present invention.
【図3】本発明の実施例のオフセット電圧の電源電圧変
動特性を示す図FIG. 3 is a diagram showing a power supply voltage fluctuation characteristic of an offset voltage according to the embodiment of the present invention.
【図3】従来例を示す図FIG. 3 shows a conventional example.
1 第1の差動アンプ 2 第2の差動アンプ 3 基準電圧発生用のツェナーダイオード 4 抵抗 5 ホール素子 6、7 アッテネーション回路 8、9 加算回路 10 定電流回路 DESCRIPTION OF SYMBOLS 1 1st differential amplifier 2 2nd differential amplifier 3 Zener diode for reference voltage generation 4 Resistance 5 Hall element 6, 7 Attenuation circuit 8, 9 Addition circuit 10 Constant current circuit
【手続補正書】[Procedure amendment]
【提出日】平成10年1月29日[Submission date] January 29, 1998
【手続補正1】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Correction target item name] Brief description of drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の実施例の回路構成図FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.
【図2】本発明の実施例の回路図FIG. 2 is a circuit diagram of an embodiment of the present invention.
【図3】本発明の実施例のオフセット電圧の電源電圧変
動特性を示す図FIG. 3 is a diagram showing a power supply voltage fluctuation characteristic of an offset voltage according to the embodiment of the present invention.
【図4】従来例を示す図FIG. 4 shows a conventional example.
【符号の説明】 1 第1の差動アンプ 2 第2の差動アンプ 3 基準電圧発生用のツェナーダイオード 4 抵抗 5 ホール素子 6、7 アッテネーション回路 8、9 加算回路 10 定電流回路 11、13 ホール素子の入力端子 12、14 ホール素子の出力端子[Description of Signs] 1 First differential amplifier 2 Second differential amplifier 3 Zener diode for generating reference voltage 4 Resistor 5 Hall element 6, 7 Attenuation circuit 8, 9 Addition circuit 10 Constant current circuit 11, 13 Hall Element input terminals 12, 14 Hall element output terminals
【手続補正2】[Procedure amendment 2]
【補正対象書類名】図面[Document name to be amended] Drawing
【補正対象項目名】図2[Correction target item name] Figure 2
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図2】 FIG. 2
Claims (3)
生器の出力を第1の差動アンプに入力し、その出力を第
2の差動アンプのプラスとマイナスに入力する事を特徴
とするオフセット補償回路。An output of a reference voltage generator connected between a positive power supply and a negative power supply is input to a first differential amplifier, and the output is input to plus and minus of a second differential amplifier. An offset compensation circuit characterized in that:
イオードを用いた事を特徴とするオフセット補償回路。2. An offset compensation circuit, wherein a zener diode is used for the reference voltage generator according to claim 1.
流回路に入力して、その出力をホール素子の入力に接続
し、ホール素子の出力を前記第2の差動アンプに入力し
て、その出力がホール素子に鎖交した磁束に比例した電
圧を得る事を特徴とするオフセット補償回路。3. An output of the reference voltage generator according to claim 1 is input to a constant current circuit, an output of which is connected to an input of a Hall element, and an output of the Hall element is input to the second differential amplifier. And an output compensating circuit for obtaining a voltage whose output is proportional to the magnetic flux linked to the Hall element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9317581A JPH11122056A (en) | 1997-10-13 | 1997-10-13 | Offset compensating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9317581A JPH11122056A (en) | 1997-10-13 | 1997-10-13 | Offset compensating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11122056A true JPH11122056A (en) | 1999-04-30 |
Family
ID=18089841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9317581A Pending JPH11122056A (en) | 1997-10-13 | 1997-10-13 | Offset compensating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11122056A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014137272A (en) * | 2013-01-16 | 2014-07-28 | Denso Corp | Voltage monitoring device |
CN109143122A (en) * | 2018-09-20 | 2019-01-04 | 上海岱梭动力科技有限公司 | Hall sensor |
JP2020169917A (en) * | 2019-04-04 | 2020-10-15 | 日本電産株式会社 | Signal processing circuit, and drive system for motor |
-
1997
- 1997-10-13 JP JP9317581A patent/JPH11122056A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014137272A (en) * | 2013-01-16 | 2014-07-28 | Denso Corp | Voltage monitoring device |
US10139453B2 (en) | 2013-01-16 | 2018-11-27 | Denso Corporation | Battery voltage monitoring device using capacitor circuit and switch failure detection circuit |
CN109143122A (en) * | 2018-09-20 | 2019-01-04 | 上海岱梭动力科技有限公司 | Hall sensor |
JP2020169917A (en) * | 2019-04-04 | 2020-10-15 | 日本電産株式会社 | Signal processing circuit, and drive system for motor |
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