JPH11120161A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a malfunction of a microcomputer associated with the drop of power supply voltage. SOLUTION: The total number of plural MOS transistors 15 which constitutes at least one bit of a specific address of a mask ROM is set to be appropriate value that is more than the total number of plural MOS transistors 6 which constitutes each bit of the other addresses of the mask ROM. With this, the effective range of power supply voltage of the microcomputer can be secured widely and the reset of the microcomputer or an alarm of battery exchange, etc., is surely carried out at a stage before the microcomputer malfunctions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer incorporated in a portable electronic device or the like.

[0002]

2. Description of the Related Art Generally, a portable electronic device (for example, a video camera recorder or the like) operates with a built-in microcomputer and a battery as a power supply. Now, the microcomputer has a built-in mask ROM in which program data for executing arithmetic processing is stored, and the electronic device executes various operations in accordance with the result of decoding the program data read from the mask ROM. It is.

In the case of a portable electronic device, the power supply voltage gradually decreases as the device is used. Therefore, a power supply voltage detection circuit for detecting whether the power supply voltage is within a range that guarantees normal operation of the microcomputer. When the power supply voltage drops to the minimum voltage that guarantees the normal operation of the microcomputer, the microcomputer is reset by a detection signal of the power supply voltage detection circuit to perform mask RO.
This has prevented the malfunction of reading M and urged battery replacement.

[0004]

However, when manufacturing an integrated circuit in which the function of the microcomputer and the function of the power supply voltage detection circuit are independently provided on the same chip,
There is a problem that the detection level of the power supply voltage detection circuit varies due to the characteristic variation of the semiconductor elements (resistance, transistor, capacitor, etc.) constituting the power supply voltage detection circuit. For example, if the detection level of the power supply voltage detection circuit is set to a level lower than the minimum voltage that guarantees normal operation of the microcomputer, the microcomputer already malfunctions before the power supply voltage detection circuit detects a drop in the power supply voltage. In this case, there is no point in providing the power supply voltage detection circuit.

Therefore, conventionally, the following measures have been taken. [Countermeasure 1] The detection level of the power supply voltage detection circuit is set higher within the range of the power supply voltage that can guarantee the normal operation of the microcomputer. However, this measure has a problem in that the effective range of the power supply voltage is narrowed, and the battery life of the electronic device using the microcomputer is shortened. [Countermeasure 2] When the microcomputer is shipped, the detection level of the power supply voltage detection circuit is measured, and a microcomputer having small variation in characteristics of the power supply voltage detection circuit is selected. However, this countermeasure is troublesome and impractical. Also, the problem of dead stock can not be overlooked.

SUMMARY OF THE INVENTION It is an object of the present invention to secure a wide range of power supply voltage at which a microcomputer operates normally and to reliably detect a drop in power supply voltage when the microcomputer is operating normally. I do.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and a plurality of serially connected MOS transistors constituting each bit are selectively provided in accordance with address data. A microcomputer having a built-in mask ROM that outputs binary data of a logical value “1” or a logical value “0” by turning on and off, and the mask ROM stores program data for operation control. A mask ROM in which the number of MOS transistors constituting at least one bit is set to be larger than the number of MOS transistors constituting each bit of another address; A detection circuit for detecting whether the content of the specific address of the mask ROM is in the first state. When it is detected that the change to the second state, characterized in that the power supply voltage to output a signal for warning that has dropped to near the minimum operation voltage.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a microcomputer of the present invention, which is assumed to be built in a portable electronic device. In FIG. 1, reference numeral 1 denotes a mask ROM, in which program data for controlling the operation of a microcomputer is printed by using a mask in a manufacturing process of the microcomputer (integrated circuit).

FIG. 2 is a circuit diagram showing the configuration of each bit of the mask ROM (1). In FIG. 2, (2) is a P-channel MOS transistor for precharging,
The source is connected to power supply VDD, and the gate is connected to precharge signal PRC. That is, the precharge signal PR
When C goes low at a predetermined timing,
The P-channel MOS transistor (2) turns on.
The P-channel MOS transistor (3) is connected in parallel with the P-channel MOS transistor (2), and the gate of the P-channel MOS transistor (3) is connected via the inverter (4) to the P-channel MOS transistors (2) and (3). ) Is connected to the common drain. That is, when the P-channel MOS transistor (2) is precharged, the P-channel MOS transistor (3) is also precharged in the same state. (5) is a plurality of N-channel type MOS transistors, and a P-channel type M transistor.
It is connected in series with the common drain of the OS transistors (2) and (3). The N-channel MOS transistor (6) is connected in series between the source of the lowermost N-channel MOS transistor (5) and ground. N-channel type M
Address data is applied to the gates of the OS transistors (5) and (6). The number of N-channel MOS transistors (5) corresponds to the number of bits of address data. When the number of bits of address data increases with the number of addresses of the mask ROM (1), the number of N-channel MOS transistors (5) increases.
The number of OS transistors (5) also increases. The N-channel MOS transistor (5) is of the enhancement type, and turns on when the address data has a logical value "1" and turns off when the address data has a logical value "0". On the other hand, the N-channel MOS transistor (6) is a depletion type, and is formed by masking one of an ON-state and an OFF-state when the address data has the logical value "1". For example, when the N-channel MOS transistor (6) is formed so as to be turned off regardless of the address data, even if the N-channel MOS transistors (5) and (6) are selected, the P-channel MOS transistor (2) is selected. (3) The common drain of (3) remains precharged to the power supply VDD, and the inverter (7)
A logical value "1" is output via (8). On the other hand, when the N-channel MOS transistor (6) is masked so as to be turned on by the address data of the logical value "1",
When the N-channel MOS transistors (5) and (6) are selected, the P-channel MOS transistors (2)
The common drain of (3) is grounded, and the inverter (7)
The logical value “0” is output via (8).

As shown in FIG. 3, at least one bit of the hatched specific address of the mask ROM (1) includes a plurality of N-channel MOS transistors (5) corresponding to the above-described other addresses. Type MO
An S-transistor (15) and an N-channel MOS transistor (6) which is turned on by address data having a logical value of "1" are connected in series. In particular, multiple N
The channel type MOS transistor (15) has two N
Channel type MOS transistors (15a) (15b)
Are connected in common so that a serial body of the address data corresponds to one bit of the address data. Therefore, the total number of N-channel MOS transistors (15) and (6) constituting at least one bit of a specific address is larger than the total number of N-channel MOS transistors (5) and (6) constituting each bit of another address. Will be set. However, N-channel type MOS transistors (5) (15)
Are the same size. Therefore, the degree of change of the bit output ROMOUT of the mask ROM (1) due to the decrease of the power supply voltage VDD is slower with the bit output of the specific address being delayed than the bit output of the other addresses.

When the power supply voltage VDD decreases with the use of portable electronic equipment, it becomes difficult to form the channels of the N-channel MOS transistors (5) and (6), and the logical value of the logical value output from the inverter (8) is reduced. Changes slow down. In particular, the output change of the inverter (8) at a specific address in the mask ROM (1) is more gradual than the output change of the inverter (8) at another address due to the number of N-channel MOS transistors (15). Become. Therefore,
By monitoring the state of the data at a specific address having a bad characteristic in the mask ROM (1), it is possible to reset or warn the microcomputer before the power supply voltage VDD drops to the minimum voltage that guarantees the normal operation of the microcomputer. It can be executed reliably.

The NAND gate (9) and the inverter (1)
0) is a read circuit connected in series to the inverter (8), and the NAND gate (9) is a timing signal TMG.
Is opened and closed. FIG. 4 is a diagram showing operation waveforms when the power supply voltage VDD decreases. For example, when the logical value ROMOUT output from the inverter (8) falls from the high level to the low level, the logical value ROMOUT at another address of the mask ROM (1) is indicated by a broken line as the power supply voltage VDD decreases. Thus, the logical value ROMOUT of the specific address of the mask ROM (1) falls even as the power supply voltage VDD similarly falls, as shown by the one-dot chain line. Slope becomes gentler. Therefore, when the timing signal TMG is at a high level, the inverter (10) of a specific address of the mask ROM (1) is output from the inverter (1) of another address.
The logical value "1" is output earlier than 0), and can be used for resetting the microcomputer, warning of battery replacement, and the like. At this time, since the logic value "0" is normally output from the inverter (10) at another address of the mask ROM (1), the power supply voltage guarantees the normal operation of the microcomputer before the microcomputer malfunctions. It is possible to reliably warn that the voltage has dropped to the vicinity of the minimum voltage.

Returning to FIG. 1, reference numeral (11) denotes a timer circuit for generating a timer interrupt signal at regular intervals. (12) is a program counter, and the mask R
OM (1) is specified. An interrupt circuit (13) stores an address value of the program counter (12) and program data for confirming the contents of a specific hatched area of the mask ROM (1) every time a timer interrupt signal is applied. The address value is changed. A determination circuit (14) determines the contents of a specific address of the mask ROM (1), and resets or resets the microcomputer when the bit value of the specific address changes from a logical value "0" to a logical value "1". It outputs a signal for warning of battery replacement and the like.

As described above, by appropriately setting the number of a plurality of N-channel MOS transistors constituting a specific address of the mask ROM (1), a wide effective range of the power supply voltage VDD can be secured. Further, before the microcomputer malfunctions, reset of the microcomputer, warning of battery replacement, and the like can be reliably executed. Note that M
The OS transistors (5), (6), and (15) may be of a P-channel type without any problem.

[0015]

According to the present invention, the effective range of the power supply voltage can be widened by appropriately setting the number of a plurality of MOS transistors constituting a specific address of a mask ROM. Further, there is obtained an advantage that a reset of the microcomputer, a warning of battery replacement, and the like can be reliably executed before the microcomputer malfunctions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer of the present invention.

FIG. 2 is a circuit diagram showing a part of another address of the mask ROM of FIG. 1;

FIG. 3 is a circuit diagram showing a part of a specific address of the mask ROM of FIG. 1;

FIG. 4 is a waveform chart showing the operation of FIGS. 2 and 3;

[Explanation of symbols]

 (1) Mask ROM (15) (6) N-channel MOS transistor (11) Timer circuit (13) Interrupt circuit (14) Judgment circuit

Claims (1)

[Claims] 1. A mask for outputting binary data of a logical value “1” or a logical value “0” by selectively turning on / off a plurality of serially connected MOS transistors constituting each bit in accordance with address data. A microcomputer having a built-in ROM and storing program data for operation control in the mask ROM; a plurality of Ms constituting at least one bit of a specific address;
A mask ROM in which the number of OS transistors is set to be larger than the number of a plurality of MOS transistors constituting each bit of another address; and a detection circuit for periodically detecting the contents of a specific address of the mask ROM, The detection circuit, when detecting that the content of the specific address of the mask ROM has changed from the first state to the second state, warns that the power supply voltage has dropped to near the minimum operating voltage. Microcomputer.