JPH11119731A - Display device for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize stable operation of a PDP display system by detecting an abnormality at the light emission of a panel and specifying an abnormal position. SOLUTION: A test signal generation circuit 41 outputs a test signal 72 of which video signal level is reduced as compared with that of a video signal 71, a row electrode current/voltage conversion circuit 51 converts a row electrode current 81 on a PDP panel into row electrode conversion voltage 82, comparators 52, 53 respectively compare the converted voltage 82 with row electrode block voltage 83 and row electrode line voltage 84 to be reference voltage levels, and a row electrode protection circuit 54 switches a driving waveform to be inputted to a timing control circuit 43 based on compared results, so that light can be emitted without expanding an abnormal position on the PDP panel and the abnormal position on the PDP panel, can easily be specified. As to column electrodes also, an abnormal position on the PDP panel can be specified by the similar constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PDP display device used for controlling light emission of a PDP panel.

[0002]

2. Description of the Related Art In recent years, there has been a tendency for image display systems to become larger and thinner. Therefore, even if the screen size becomes large, stable operation is required for various video sources, and therefore, a stable operation corresponding to various video sources is also required for a PDP display system.

Conventionally, a stable operation control of a PDP display system is disclosed in Japanese Patent Application Laid-Open No. 5-265395.

[0004] A conventional PDP display system will be described below. FIG. 4 is a functional block diagram showing the structure of a conventional PDP display system.

In FIG. 4, a conventional PDP display system is an AC discharge type plasma display panel (hereinafter referred to as an AC type PDP panel) 1 comprising a row electrode and a column electrode.
A row electrode control circuit 2 for applying a row electrode drive signal 36 to a row electrode of the AC PDP panel;
A column electrode control circuit 3 for applying a column electrode drive signal 37 to a column electrode of the DP panel; a vertical synchronization signal 21;
2, data processing clock signal 23, video data signal 2
4. A central control circuit 4 for outputting a video display / non-display switching signal 25 for switching video display / non-display, and controlling the row electrode control circuit 2 based on the vertical synchronization signal 21 and the horizontal synchronization signal 22 A row electrode control signal 26, a column electrode control signal 27 for controlling the column electrode control circuit 3,
A scan control unit 5 for outputting a scan timing control signal 28 for determining a time timing of a drive pulse of the C-type PDP panel 1; and a column electrode control circuit 3 based on the data processing clock signal 23 and the video data signal 24. A data processing unit 6 for outputting an output signal 29 for controlling the operation of the AC PDP panel 1 based on the scan timing control signal 28; a drive timing signal 30; a drive selection signal 31; Output as PDP timing generator 7
A timing check section 8 for judging whether the drive timing signal 30 is normal or abnormal, and outputting a result of the judgment as a timing check section output signal 32;
A row electrode selection signal 33 for controlling the row electrode control circuit 2 based on the non-display switching signal 25, the drive selection signal 31, and the timing check section output signal 32, and a column electrode selection for controlling the column electrode control circuit 3. A select unit 9 that outputs a signal 34; the scan control unit 5; the data processing unit 6; the PDP timing generator 7;
It comprises a timing control circuit 10 composed of the timing check section 8 and the selection section 9, and a clock generation circuit 11 for outputting a clock signal 35 for controlling the timing control circuit 10.

The operation of the conventional PDP display system configured as described above will be described with reference to FIG.

The vertical synchronizing signal 21 and the horizontal synchronizing signal 22 output from the central control circuit 4 are converted into the row electrode control signal 26 and the column electrode control signal 27 by the scan control unit 5, and the data processing is performed. The clock signal 23 and the video data signal 24 are converted into an output signal 29 by the data processing unit 6. The converted row electrode control signal 26 causes the row electrode control circuit 2 to output the row electrode drive signal 36 for driving the row electrode of the AC type PDP panel 1, and converts the converted column electrode control signal 27, The data processing unit output signal 29 causes the column electrode control circuit 3 to output the column electrode drive signal 37 for driving the column electrodes of the AC type PDP panel 1 so that the AC type PDP panel 1 emits light.

When an abnormal signal is generated in the row electrode drive signal 36 and the column electrode drive signal 37 when the AC PDP panel 1 emits light, the scan control unit 5
The scan timing control signal 28 output from the PDP timing generator 7 is converted into the drive timing signal 30 and the drive selection signal 31 by the PDP timing generator 7, and the converted drive timing signal 30 is converted by the timing check unit 8 during normal operation. The timing check unit output signal 32 is compared with the drive timing of the video display / non-display switching signal 25 and the drive selection signal 3
1. Based on the timing checker output signal 32, the selector 9 selects the row electrode so as to prevent an abnormal drive timing signal from being supplied to the row electrode control circuit 2 and the column electrode control circuit 3. This is a PDP display device that outputs a voltage 33 and the column electrode selection voltage 34, stops light emission of the AC type PDP panel, and prevents destruction of the display device at abnormal driving timing, thereby realizing a stable operation.

[0009]

However, in the above-described conventional configuration, if the AC PDP panel emits light again after detecting the abnormal signal and stopping the light emission, the abnormal portion may be enlarged. There is a problem that the light emitting display cannot be continued.

In the above-described conventional configuration, when an abnormal signal is detected, an abnormal driving timing signal is prevented from being supplied to the driving circuit to stop the light emission of the PDP panel. It is necessary to make the device emit light to confirm the abnormal portion again.

In the above-described conventional configuration, when an abnormal portion occurs in the PDP panel, a non-light emitting region exists in a unit of a row electrode and a unit of a column electrode, so that it is difficult to improve the yield of the PDP panel. Have.

[0012]

In order to solve this problem, a test signal generator of the present invention outputs the test signal for confirming a light emitting state of the PDP panel, and a test signal switching device is inputted. The video signal is switched to the test signal, the electrode current detection device measures the electrode current based on the test signal, the electrode current comparison device compares the electrode current with the electrode reference current, and the drive timing control device A drive signal for each electrode of the PDP panel is controlled based on an output signal of the electrode current comparison device.

In order to solve the above-mentioned problem, an arithmetic processing unit of the present invention calculates an abnormal occurrence location based on an output signal of the electrode current comparison device, and a drive timing control device determines the abnormality occurrence position. The video signal switching signal and the electrode control signal are output based on the output signal, and the test signal switching device switches the input video signal to the test signal based on the video signal switching signal, and displays an abnormal portion. The apparatus is configured to output and display an abnormal portion of the PDP panel for each electrode based on an output signal of the arithmetic processing unit.

According to another aspect of the present invention, there is provided a test signal generating apparatus, wherein an arithmetic processing unit calculates and calculates an abnormality occurrence location based on an output signal of the electrode current comparing device.
A drive timing control device outputs the video signal switching signal and the electrode control signal based on an output signal of the arithmetic processing device, and a test signal switching device outputs a video signal input based on the video signal switching signal. Is switched to the test signal, and the video signal processing device is configured to set the abnormality occurrence portion of the video signal to a black level based on the output signal of the arithmetic processing device.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a test signal generator for outputting a test signal for confirming a light emitting state of the PDP panel, an input video signal and the test signal. A video signal switching device for switching between signals, an electrode current detection device for detecting a current flowing through each electrode of the PDP panel based on the test signal, and an electrode current comparison device for comparing the electrode current with the electrode reference current And a drive timing control device for outputting the electrode control signal for controlling the drive timing of the PDP panel based on the output signal of the electrode current comparison device, and the PDP based on the test signal. It has the function of detecting the abnormal current of each electrode of the panel and controlling the light emission of the PDP panel.

According to a second aspect of the present invention, in addition to the test signal generating device, the electrode current detecting device, and the electrode current comparing device, an abnormality is generated based on an output signal of the electrode current comparing device. An arithmetic processing device that calculates the location of occurrence, a drive timing control device that outputs the video switching signal and the electrode control signal based on an output signal of the arithmetic processing device, and PDP
A video signal switching device that switches a video signal that is being input when an abnormality occurs in the panel to the test signal,
An abnormal point display device for outputting and displaying an abnormal point of the PDP panel on an electrode basis based on an output signal of the arithmetic processing unit, and detecting an abnormal current of each electrode of the PDP panel, It has the effect of switching the signal to the test signal and outputting and displaying the location of the PDP where an abnormality has occurred.

According to a third aspect of the present invention, the test signal generating device, the video signal switching device, the electrode current detecting device, the electrode current comparing device, the arithmetic processing device, In addition to the drive timing controller,
The image processing apparatus further comprises a video processing device for setting a black level at a location where an abnormality of the video signal occurs based on an output signal of the arithmetic processing device, and after detecting an abnormal current of each electrode of the PDP panel,
The video signal is switched to the test signal and the PDP
This has the effect of setting the video signal level at the location where an abnormality has occurred on the panel to the black level.

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG. Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a PDP according to an embodiment of the present invention.
FIG. 2 is a functional block diagram illustrating a structure of a display system.

In FIG. 1, reference numerals 1 to 40 denote various functional blocks and various signals in the prior art.

In the first embodiment of the present invention shown in FIG. 1, reference numeral 41 added to the conventional technique is a test signal generating circuit for outputting a test signal 72 for confirming a light emitting state of the AC type PDP panel 1, Reference numeral 42 denotes a switch signal 73 for converting the input video signal 71 and the test signal 72 into signals.
A video signal changeover switch that outputs a switch output signal 74 based on the control signal; a timing control circuit 43 that outputs a row electrode control signal 76 and a column electrode control signal 77 based on the central control circuit output signal 75 and the clock signal 35; 51 is A
A row electrode conversion voltage 8 obtained by converting a current (hereinafter, referred to as a row electrode current) 81 flowing through a row electrode of the C type PDP panel 1 into a voltage.
A row electrode current / voltage conversion circuit 52 that outputs 2 compares the row electrode converted voltage 82 with a voltage (hereinafter, referred to as a row block voltage) 83 obtained by converting a current in a block unit of the row electrode into a voltage (hereinafter referred to as a row block voltage) 83. A comparator 53 for outputting a signal 85, a row electrode conversion voltage 82 and a voltage (hereinafter referred to as a row line voltage) 84 obtained by converting a current of each row electrode line into a voltage 84
And outputs a comparator output signal 86.
Is a signal for limiting the row electrode control signal 76 output from the timing control circuit 43 based on the comparator output signal 85 and the comparator output signal 86 to protect the row electrode from being damaged (hereinafter referred to as the row electrode A row electrode protection circuit that outputs a protection signal (87) and a column electrode (61) that outputs a column electrode conversion voltage (92) obtained by converting a current (hereinafter, referred to as a column electrode current) 91 flowing through a column electrode of the AC PDP panel (1) into a voltage A current / voltage conversion circuit 62 compares the column electrode conversion voltage 92 with a voltage (hereinafter referred to as a column block voltage) 93 obtained by converting a current in a block unit of a column electrode into a voltage (hereinafter referred to as a column block voltage) 93 and outputs a comparator output signal 95. , 63 is the column electrode conversion voltage 92
And a comparator 94 which compares a current (hereinafter referred to as a column line voltage) 94 obtained by converting a current in a line unit of the column electrode into a voltage, and outputs a comparator output signal 96. 64 is the comparator output signal 95, A column electrode protection for outputting a signal (hereinafter referred to as a column electrode protection signal) 97 for limiting a column electrode control signal 77 output from the timing control circuit 43 based on the output signal 96 to protect the column electrode from damage. Circuit.

The operation of the PDP display system configured as described above will be described with reference to FIG.

In FIG. 1, when an abnormality occurs in the drive timing of the central control circuit 4, the central control circuit 4 prevents the abnormal drive signal from being supplied to the AC type PDP panel 1. Timing control circuit 43
To stop the light emission of the AC type PDP panel 1.

When the light is turned on again after the light emission is stopped, the switch output signal 74 is switched from the video signal 71 to the test signal 72 by the switch switching signal 73, and the switch output signal 74 is transmitted to the central control circuit 4 by the central control circuit 4. The central control circuit output signal 75 becomes the circuit output signal 75, and the central control circuit output signal 75 becomes the row electrode control signal 76 and the column electrode control signal 77 in the timing control circuit 43 to control the row electrode control circuit 2 and the column electrode control circuit 3. . The row electrode current 81 flowing through the row electrode control circuit 2 becomes the row electrode conversion voltage 82 in the row electrode current / voltage conversion circuit 51, and the row electrode conversion voltage 82 is a voltage during normal operation of the row electrode. The row electrode block voltage 83 and the row electrode line voltage 84 are compared with the comparator 52 and the comparator 53 to become the comparator output signal 85 and the comparator output signal 86, and the comparator output signal 85 and the comparison Output signal 8
Reference numeral 6 denotes the row electrode protection signal
Thus, the row electrode protection signal 87 controls the row electrode control signal 76 by the timing control circuit 43, so that the light emission of the AC type PDP panel 1 can be continued without damaging the abnormal portion on the row electrode side. Note that the same applies to the column electrodes as to the row electrodes.

That is, by switching the video signal 71 to the test signal 72, the video signal level is lowered, and the row electrode protection signal 87 and the column electrode protection signal 97 generate the A signal.
By switching the drive waveform of the abnormal part of the C-type PDP panel 1, it is possible to emit light without expanding the abnormal part of the AC-type PDP panel 1, and to easily identify the abnormal part of the AC-type PDP panel 1. be able to.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to FIG.

FIG. 2 shows a PDP according to an embodiment of the present invention.
FIG. 2 is a functional block diagram illustrating a structure of a display system.

In FIG. 2, reference numerals 1 to 40 denote various functional blocks and various signals in the prior art.
0 indicates various functional blocks and various signals in the first embodiment.

In the second embodiment of the present invention shown in FIG. 2, reference numeral 101 added to the first embodiment designates the row electrode control signal 76 based on the central control circuit output signal 75 and the clock signal 35, A timing control circuit that outputs the column electrode control signal 77 and a signal (hereinafter, referred to as a switch control signal) 106 for switching the video signal changeover switch 42. The timing control circuit 102 is based on the comparator output signal 85 and the comparator output signal 86. A signal indicating an abnormal portion on the row electrode side of the AC type PDP panel 1 (hereinafter, referred to as an LED control signal)
An arithmetic processing circuit that outputs 107; an LED display circuit 103 that displays an abnormal point on the row electrode side of the AC type PDP panel 1 with an LED based on the LED control signal 107;
Reference numeral 104 denotes a signal (hereinafter referred to as an LED control signal) 10 indicating an abnormal portion on the column electrode side of the AC PDP panel 1 based on the comparator output signal 95 and the comparator output signal 96.
An arithmetic processing circuit 105 for outputting 8 and an LED display circuit 105 for displaying an abnormal portion on the column electrode side of the AC type PDP panel 1 with LEDs based on the LED control signal 108.

The operation of the PDP display system configured as described above will be described with reference to FIG.

In FIG. 2, when an abnormality occurs in the drive timing in the central control circuit 4, the central control circuit 4 prevents the abnormal drive signal from being supplied to the AC type PDP panel 1. Central control circuit output signal 7
5 to control the timing control circuit 43 to output the switch control signal 106;
6 switches the switch output signal 74 from the video signal 71 to the test signal 72, the switch output signal 74 becomes the central control circuit output signal 75 in the central control circuit 4, and the central control circuit output signal 75 The timing control circuit 43 becomes the row electrode control signal 76 and the column electrode control signal 77, and controls the row electrode control circuit 2 and the column electrode control circuit 3. The row electrode current 81 flowing through the row electrode control circuit 2 becomes the row electrode conversion voltage 82 in the row electrode current / voltage conversion circuit 51, and the row electrode conversion voltage 82 is a voltage during normal operation of the row electrode. The row electrode block voltage 83 and the row electrode line voltage 84 are compared with the comparator 52 and the comparator 53 to become the comparator output signal 85 and the comparator output signal 86, and the comparator output signal 85 and the comparison The device output signal 86 becomes the LED control signal 107 indicating the abnormal position of the row side electrode in the arithmetic processing circuit 102, and the LED control signal 107
The ED display circuit 103 can display the location where the abnormality has occurred on a row electrode basis. Note that the same applies to the column electrodes as to the row electrodes.

That is, abnormal light emission of the AC type PDP panel 1 is detected by comparing the row electrode current 81 and the column electrode current 91 with the electrode current in normal operation, and after detecting the abnormal light emission, the switch control signal By switching the video signal 71 to the test signal 72 at 106 and lowering the video signal level, an abnormal portion of the AC PDP panel 1 is output to an external display device without stopping the light emission of the AC PDP panel 1. can do.

(Embodiment 3) Hereinafter, a third embodiment of the present invention will be described with reference to FIG.

FIG. 3 shows a PDP according to an embodiment of the present invention.
FIG. 2 is a functional block diagram illustrating a structure of a display system.

In FIG. 3, reference numerals 1 to 40 denote various functional blocks and various signals in the prior art.
0 indicates various functional blocks and various signals in the first embodiment, and 101 to 110 indicate various functional blocks and various signals in the second embodiment.

In the third embodiment of the present invention shown in FIG. 3, reference numeral 111 added to the second embodiment denotes the video signal 71.
The field memory 112 outputs a video data signal (hereinafter, referred to as a field memory output signal) 121 for one field period. A signal (hereinafter, referred to as a black level) of an abnormal line of the field memory signal 121 based on the line control signal 122 A line extraction circuit that outputs 123) 113 is one of the video signals 71
A line memory for outputting a video data signal (hereinafter, referred to as a line memory output signal) 124 for a line period; 114 a line memory signal 12 based on a dot control signal 125;
4 is a dot extraction circuit that outputs a signal (hereinafter, referred to as a dot extraction signal) 126 in which the abnormal occurrence dot is set to a black level (hereinafter referred to as a dot extraction signal). Signal indicating abnormal part (hereinafter referred to as OR circuit output signal) 1
An OR circuit for outputting 27, the video signal 71,
The AC type PD based on the OR circuit output signal 127
An AND circuit 117 outputs a video signal (hereinafter referred to as an AND circuit output signal) 128 in which an abnormal portion of the P panel 1 is set to a black level, and 117 controls the row electrode based on the central control circuit output signal 75 and the clock signal 35. A timing control circuit which outputs a signal (hereinafter referred to as a switch control signal) 129 for switching between the signal 76, the column electrode control signal 77, the AND circuit output signal 128, and the test signal 72;
An arithmetic processing 118 outputs a signal (hereinafter, referred to as a line control signal) 122 for setting the abnormal position on the row electrode side of the AC type PDP panel 1 to a black level based on the comparator output signal 85 and the comparator output signal 86. The circuit 119 outputs a signal (hereinafter referred to as a dot control signal) 125 for setting the abnormal portion on the column electrode side of the AC type PDP panel 1 to a black level based on the comparator output signal 95 and the comparator output signal 96. An arithmetic processing circuit.

The operation of the PDP display system configured as described above will be described with reference to FIG.

In FIG. 3, when an abnormality occurs in the drive timing in the central control circuit 4, the central control circuit 4 prevents the abnormal drive signal from being supplied to the AC PDP panel 1. Central control circuit output signal 7
5 to control the timing control circuit 43 to output the switch control signal 129,
At 29, the switch output signal 74 is switched from the video signal 71 to the test signal 72, and the switch output signal 74 becomes the central control circuit output signal 75 at the central control circuit 4, and the central control circuit output signal 75 The timing control circuit 43 becomes the row electrode control signal 76 and the column electrode control signal 77, and controls the row electrode control circuit 2 and the column electrode control circuit 3. The row electrode current 81 flowing through the row electrode control circuit 2 becomes the row electrode conversion voltage 82 in the row electrode current / voltage conversion circuit 51, and the row electrode conversion voltage 82 is a voltage during normal operation of the row electrode. The row electrode block voltage 83 and the row electrode line voltage 84 are compared with the comparator 52 and the comparator 53 to become the comparator output signal 85 and the comparator output signal 86, and the comparator output signal 85 and the comparison The output signal 86 becomes the line control signal 122, which is a signal for setting the abnormal portion of the row side electrode to a black level in the arithmetic processing circuit 118. Similarly, the column electrode current 9 flowing through the column electrode control circuit 3 is also applied to the column electrode.
1 is the column electrode converted voltage 92 in the column electrode current / voltage conversion circuit 61, and the column electrode converted voltage 92 is the column electrode block voltage 93 which is a voltage during normal operation of the column electrode;
The column electrode line voltage 94 is compared with the comparator 62 and the comparator 63 to become the comparator output signal 95 and the comparator output signal 96, and the comparator output signal 95 and the comparator output signal 96 are used for the arithmetic operation. A signal for setting an abnormal portion of the column side electrode to a black level in the processing circuit 119 The dot control signal 1
It will be 25. As a result, the video signal 71 is converted into a video signal in which an abnormality occurrence part is set to a black level by the line control signal 122 and the dot control signal 125 to the AND circuit output signal 128, and after being converted, the switch control signal 129 becomes The switch output signal 74 can be switched from the test signal 72 to the AND circuit output signal 128.

That is, abnormal light emission of the AC type PDP panel 1 is detected by comparing the row electrode current 81 and the column electrode current 91 with the electrode current during normal operation, and after detecting abnormal light emission, the line control signal 122, by setting the video signal level of the abnormal portion of the AC PDP panel 1 indicated by the dot control signal 125 to a black level,
The non-light-emitting pixels of the system PDP panel 1 can be minimized, and the expansion of abnormal portions can be prevented, and the yield of the AC system PDP panel 1 can be improved.

[0040]

As described above, the present invention provides a test signal generator for outputting a test signal for confirming the light emitting state of the PDP panel, and a video signal for switching between the input video signal and the test signal. A switching device, an electrode current detection device that detects a current flowing through each electrode of the PDP panel based on the test signal output from the test signal generation device, and an electrode current measured by the electrode current detection device. An electrode current comparison device that compares the electrode reference current flowing during normal operation; and a drive timing control device that outputs the electrode control signal that controls the drive timing of the PDP panel based on an output signal of the electrode current comparison device. By providing the PDP panel, the video signal level is lowered, and the drive waveform of the abnormal portion of the PDP panel is switched, so that the PDP panel is changed. Limiting the current flowing to the electrodes of Le,
By emitting light without enlarging an abnormal portion of the PDP panel, an advantageous effect that an abnormal portion of the PDP panel can be easily specified can be obtained.

As described above, according to the present invention, there is provided an arithmetic processing device for calculating an abnormality occurrence location based on an output signal of the electrode current comparing device, and an input device based on an output signal of the arithmetic processing device. A drive timing control device that outputs the video switching signal and the electrode control signal for switching a video signal to be output to the test signal, and a video that is input based on the video switching signal when an abnormality occurs in the PDP panel. A video signal switching device for switching a signal to the test signal; and an abnormal location display device for displaying an abnormal location of the PDP panel on an electrode basis based on an output signal of the arithmetic processing unit, thereby providing the PDP panel. This has the advantageous effect that an abnormal portion of the PDP panel can be output and displayed outside without stopping the light emission of the PDP panel.

Further, as described above, the present invention provides the PDP
By providing a video processing device for setting the video signal level of the abnormal portion of the PDP panel to a black level based on the output signal of the arithmetic processing device when an abnormality occurs in the panel,
An advantageous effect is obtained that the non-light emitting pixels of the PDP panel are minimized and the abnormal portion is prevented from being enlarged, and the yield of the PDP panel can be improved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a PDP display system according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram showing a PDP display system according to a second embodiment of the present invention.

FIG. 3 is a functional block diagram showing a PDP display system according to a third embodiment of the present invention.

FIG. 4 is a functional block diagram showing a conventional PDP display system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 AC discharge type plasma display panel 2 Row electrode control circuit 3 Column electrode control circuit 4 Central control circuit 6 Scan control unit 7 Data processing unit 5 PDP timing generator 8 Select unit 9 Timing check unit 10 Timing control circuit 11 Clock generation circuit 21 Vertical Synchronization signal 22 Horizontal synchronization signal 23 Data processing clock signal 24 Video data signal 25 Video display / non-display switching signal 26 Row electrode control signal 27 Column electrode control signal 28 Scan timing control signal 29 Data processing unit output signal 30 Drive timing signal 31 Drive selection signal 32 Timing check section output signal 33 Row electrode selection signal 34 Column electrode selection signal 35 Clock signal 36 Row electrode drive signal 37 Column electrode drive signal 41 Test signal generation circuit 42 Video signal switching Switch 43 Timing control circuit 51 Row electrode current / voltage conversion circuit 52 Comparator 53 Comparator 54 Row electrode protection circuit 61 Row electrode current / voltage conversion circuit 62 Comparator 63 Comparator 64 Row electrode protection circuit 71 Video signal 72 Test signal 73 Switch switching signal 74 Switch output signal 75 Central control circuit output signal 76 Row electrode control signal 77 Column electrode control signal 81 Row electrode current 82 Row electrode current conversion voltage 83 Row electrode block voltage 84 Row electrode line voltage 85 Comparator output signal 86 Compare Output signal 87 row electrode protection signal 91 column electrode current 92 column electrode current conversion voltage 93 column electrode block voltage 94 column electrode line voltage 95 comparator output signal 96 comparator output signal 97 column electrode protection signal 101 timing control circuit 102 arithmetic processing Circuit 103 LED display circuit 1 4 Arithmetic Processing Circuit 105 LED Display Circuit 106 Switch Control Signal 107 LED Control Signal 108 LED Control Signal 111 Field Memory Circuit 112 Line Extraction Circuit 113 Line Memory Circuit 114 Dot Extraction Circuit 115 OR Circuit 116 AND Circuit 117 Timing Control Circuit 118 Operation Processing Circuit 119 arithmetic processing circuit 121 field memory output signal 122 line control signal 123 line extraction signal 124 line memory output signal 125 dot control signal 126 dot extraction signal 127 OR circuit output signal 128 AND circuit output signal 129 switch control signal

Claims (3)

[Claims] 1. A plasma display panel (PDP)
A test signal generator for outputting a test signal for confirming the light emission state of the panel, a video signal switching device for switching between the input video signal and the test signal, and an output from the test signal generator. An electrode current detecting device for detecting a current flowing through each electrode of the PDP panel based on the test signal; a current measured by the electrode current detecting device (hereinafter referred to as an electrode current); and an electrode current flowing during normal operation (hereinafter referred to as an electrode). An electrode current comparison device for comparing a reference current) and a drive timing control device for outputting a signal (hereinafter, referred to as an electrode control signal) for controlling a drive timing of the PDP panel based on an output signal of the electrode current comparison device. A PDP display device comprising: 2. A test signal generator for outputting a test signal for confirming a light emitting state of a plasma display panel, and each electrode of the PDP panel based on the test signal output from the test signal generator. The electrode current detection device that detects a current flowing through the electrode current comparison device that compares the electrode current measured during the normal operation with the electrode current measured by the electrode current detection device,
An arithmetic processing unit for calculating an abnormality occurrence location based on an output signal of the electrode current comparison device, and a signal for switching a video signal input based on an output signal of the arithmetic processing device to the test signal (hereinafter, referred to as a test signal) An image switching signal) and a drive timing control device that outputs the electrode control signal;
A video signal switching device for switching a video signal input based on the video switching signal to the test signal when an abnormality occurs in the PDP panel; and a video signal switching device for controlling the PDP panel based on an output signal of the arithmetic processing device. A PDP display device comprising: an abnormal point display device that outputs and displays an abnormal point on an electrode basis. 3. The test signal generator for outputting the test signal for confirming the light emission state of the plasma display panel, and each of the PDP panels based on the test signal output from the test signal generator. The electrode current detection device for detecting a current flowing through an electrode, the electrode current comparison device for comparing the electrode current measured by the electrode current detection device with the electrode reference current flowing during normal operation, and the electrode current comparison device. An arithmetic processing unit that calculates an abnormality occurrence location based on an output signal; and the video switching signal and the electrode control signal for switching a video signal input based on an output signal of the arithmetic processing device to the test signal. A drive timing control device for outputting
A video signal switching device that switches a video signal input based on the video switching signal to the test signal when an abnormality occurs in the panel; and an output signal of the arithmetic processing device when an abnormality occurs in the PDP panel. A PDP display device, further comprising a video processing device for setting an abnormal occurrence portion of the video signal to a black level.