JPH11111927A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a resistor layer of a high sheet resistance without damaging the sharpness of a heterojunction interface by diffusing zinc as a P-type impurity into an epitaxial substrate of a compound semiconductor at a high concentration by vapor phase diffusion. SOLUTION: An organic matter of zinc is diffused by vapor phase diffusion into an opening with an SiN film 17 as a selective diffusion mask to form a zinc diffusion resistor layer 16. Then, dimethylzinc or diethylzinc, which is a liquid organic metal is supplied in a gaseous state to the semiconductor substrate with high purity hydrogen as a carrier gas. An AlGaAs layer is deposited on a layer above a GaAs layer and zinc is selectively diffused into the AlGaAs layer, thereby preventing the diffusion of zinc the GaAs layer. By diffusing zinc at 600 deg.C or about, the destruction of a sharp crystal structure in a heterojunction interface can be prevented. Then, the zinc diffusion resistor layer 16 is covered by an insulator and an ormic contact formation section is etched, and metal is deposited on the p-AlGaAs layer, thereby obtaining a resistor including an electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a heterojunction field effect transistor and a resistor applied to, for example, a microwave communication device and the like, and a method of manufacturing the same, and more particularly to the formation of a resistance layer.

[0002]

2. Description of the Related Art A microwave integrated circuit (MMIC; monolith) which is indispensable for a microwave communication device such as mobile communication.
High-speed operability and low-noise characteristics are required for a high-speed microwave IC.

[0003] The MMIC is configured using a field effect transistor (FET) using a GaAs substrate as a basic element. The electron mobility of GaAs is about five times that of Si.
Is frequently used. MOSFET, MES as FET
FET (metal semiconductor F
ET) or junction field effect transistor (junctio)
n FET; JFET) has been used.

In a conventional MMIC, a MESFET or a JF
Separately from the step of manufacturing an FET such as ET, an impurity is introduced into a desired region to provide a resistance layer. In the FET manufacturing process, an impurity is introduced by ion implantation into a GaAs substrate, and then annealed by heating usually to 800 ° C. or higher. In the resistance layer manufacturing process, the impurity is introduced into a desired region, Activation annealing was performed in the same step as in the above.

Recently, MOSFET, MESFET and JF
The channel structure is different from the conventional FET such as ET,
High electron mobility transistor (high electron
nmobility transistor; HEM
T) is in mass production. FIG. 6 shows a sectional view of the basic structure of the HEMT. Resistivity 10 ^6- containing almost no impurities
A buffer layer 62 is provided on a semi-insulating GaAs substrate 61 of 10 ⁸ Ωcm.

The GaAs substrate 61 has a GaAs melting point (12
Since it is a bulk crystal grown at 38 ° C.), it contains many point defects and lattice defects such as dislocations. Therefore, when the operating epitaxial layer is grown directly on the substrate 61,
The quality of the epitaxial layer near the substrate in the early stage of growth becomes poor. To prevent this, a buffer layer 62 is formed by epitaxial growth between the substrate 61 and the active epitaxial layer.

On the buffer layer 62, an i-GaAs layer (electron transit layer) 63 in which impurities are reduced as much as possible is formed, and an n ⁺ -AlGaAs layer (electron supply layer) 64 is formed thereon by epitaxial growth. n ⁺ -AlGaAs layer 6
The electrons generated from 4 move to the junction interface with the i-GaAs layer 63 to form a channel and serve as a current path. HEM
The heterojunction used for T is GaAs / AlGa described above.
In addition to As, GaAs / InGaAs, AlGaAs / I
nGaAs, InGaAs / AlInAs, Si / Si
Ge may be used.

In the HEMT, electrons and donor ions are spatially separated, so that electrons traveling in the channel are not scattered by the donor ions. Therefore, high-speed movement of electrons becomes possible. The switching time of the HEMT can be reduced to about 10 ps.
High speed operation of 0 times or more is possible, and operation is possible at low voltage.

The channel in the HEMT has a thickness of about 10
At 15 nm, the number of atomic layers is extremely thin, about 20 to 30 layers, and there is no degree of freedom of electron transfer in the vertical direction of the bonding surface.
It is a two-dimensional electron channel. Therefore, HEM
In T, the quality of the crystallinity near the heterojunction interface between the electron supply layer and the electron transit layer is an important issue, and it is necessary to control the atomic size.

On the other hand, the resistance of a normal transistor has a resistance of several kΩ to several tens of kΩ.
A high resistance of 0 kΩ is often required, and it is desirable to form a resistance layer having a sheet resistance (area resistivity) of several kΩ / □. As a method of manufacturing a resistance layer in an MMIC, there are a method of using an epitaxial layer and a method of forming a resistance layer using a metal thin film. In a conventional MMIC, a resistive layer is formed in a different step from the FET area in a different step.

[0011]

However, in the above-described conventional method for manufacturing a resistance layer of an MMIC, when an epitaxial layer is used as a resistor, a channel layer is used. In this case, the sheet resistance is determined by the channel resistance of the transistor, and it is impossible to obtain an arbitrarily controlled sheet resistance.

The channel layer has a low sheet resistance,
In order to make the resistance of several tens of kΩ required for the MIC, the chip size becomes large, which is disadvantageous in miniaturization. Furthermore, at room temperature, since most of the noise of the HEMT is thermal noise, there is a problem that the noise increases as the resistance increases.

When a resistance layer is formed using a metal thin film, NiCr, TaN, or the like is used as a material, but the sheet resistance is several hundreds Ω / □, which is one order of magnitude lower than the sheet resistance required for MMIC. . Also, deposit a metal thin film
Since the etching is performed, the steps are increased, which is contrary to the planerization of the resistance.

Further, a HEM using an epitaxial substrate
In the case of forming a resistor in T, after the crystal growth of the operating epitaxial layer is performed at 500 to 600 ° C., impurities are ion-implanted to form a resistor layer. After the ion implantation into the resistance layer, annealing is performed by heating to 800 ° C. or more, so that the crystallinity of the active epitaxial layer is deteriorated, which is not desirable particularly in maintaining a steep heterojunction interface.

The present invention has been made in view of the above problems, and accordingly, the present invention relates to a semiconductor device having a heterojunction field-effect transistor and a resistor, wherein the crystallinity of the epitaxial layer and the heterojunction interface It is an object of the present invention to provide a semiconductor device in which a resistance layer having a high sheet resistance is formed by introducing impurities without impairing the steepness of the semiconductor device, and a method for manufacturing the same.

[0016]

In order to achieve the above object, a semiconductor device of the present invention comprises a heterojunction field effect transistor formed on a substrate of a first conductivity type, and a semiconductor layer forming the transistor. And a resistance layer formed of a second conductivity type impurity diffusion layer opposite to the first conductivity type. As a result, a resistance layer having a high sheet resistance can be obtained, and the chip size can be reduced.

The semiconductor device according to the present invention is preferably
The semiconductor layer is formed of at least an epitaxially grown layer of a group III-V compound semiconductor.
Thereby, in the HEMT, crystallinity was controlled at an atomic size level between the electron supply layer and the electron transit layer.
A good heterojunction interface can be obtained.

The semiconductor device of the present invention is preferably
The semiconductor layer is an n-type semiconductor made of GaAs or AlGaAs. Thereby, H
It is possible to form a resistance layer having a high resistance value on a desired layer of the EMT.

The semiconductor device of the present invention is preferably
The p-type impurity layer is made of zinc. Thus, when zinc is diffused at a high concentration as a p-type impurity, an ohmic contact can be easily obtained, and the resistance can be adjusted while checking the resistance. Therefore, the controllability of the resistance value is improved, and a resistance layer having a desired resistance value can be formed.

The semiconductor device of the present invention is preferably
The resistance value of the resistor is controlled by controlling the Al composition in the AlGaAs layer and adjusting the diffusion rate at which zinc is vapor-phase diffused. Thus, when the AlGaAs layer is stacked on the GaAs layer, zinc is selectively diffused into the AlGaAs layer,
It is possible to precisely and easily control the diffusion in the vertical direction such that the diffusion is not performed in the aAs layer.

Furthermore, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized in that zinc is vapor-phase-diffused into an arbitrary semiconductor layer of a heterojunction field effect transistor formed on a GaAs substrate. Forming a p-type impurity layer and using the p-type impurity layer as a resistor.

This eliminates the need for a step of annealing at a temperature of 800 ° C. or higher, which is necessary when forming a resistance layer by ion implantation. Therefore, it is possible to prevent the crystal structure at the heterojunction interface of the operation epitaxial layer from being deteriorated by heating. Further, by using the p-type impurity layer of the heterojunction field-effect transistor as a resistor, the resistance layer can be reduced in size and made planar.

The method of manufacturing a semiconductor device of the present invention described above
The p-type impurity layer, which is the resistor, is a layer formed by epitaxial growth, and preferably, the p-type impurity layer is AlGaAs formed by epitaxial growth.
Or a GaAs layer. As a result, in the HEMT, a favorable heterojunction interface in which crystallinity is controlled at the atomic size level between the electron supply layer and the electron transit layer can be obtained. It is possible to form a high resistance layer.

The method for manufacturing a semiconductor device of the present invention described above
By controlling the Al composition in the AlGaAs layer, the diffusion rate at which zinc is vapor-phase diffused is adjusted, and the resistance value of the resistor is controlled. Thus, G
An AlGaAs layer is laminated on the upper layer of the aAs layer, and the upper layer of Al is formed.
Zinc can be selectively diffused only in the GaAs layer, and not in the GaAs layer, but the diffusion in the vertical direction can be controlled.

[0025]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional view of a semiconductor device according to this embodiment. The HEMT unit 01 and the resistance unit 02 are formed on the same substrate. HEMT part 01 and resistance part 0
2 is separated by a groove formed by etching. Buffer layer 12, i-G on GaAs substrate 11
An aAs layer (electron transit layer) 13 and an n ⁺ -AlGaAs layer (electron supply layer) 14 are deposited. HEMT part 01
An n ⁺ -GaAs layer 15 is further provided as an upper layer,
Has a zinc diffusion resistance layer 16 as an upper layer.

FIGS. 2A to 2D show the first embodiment of FIG.
FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device of FIG.

The GaAs substrate 11 shown in FIG.
A bulk crystal grown at an s melting point (1238 ° C.) is used. The growth of the bulk crystal is performed by, for example, the horizontal Bridgman method, and semi-insulating GaAs obtained by the horizontal Bridgman method is 4000 to 5000 cm ² / Vs at room temperature.
It has a high carrier mobility and a transition density of 10 ² to 1
A substrate of about 0 ³ / cm ² is obtained. In addition to the horizontal Bridgman method, a bulk crystal can be grown by a liquid sealing pulling method.

[0029] GaAs is vapor-phased on the GaAs substrate 11
The buffer layer 12 is formed by epitaxial growth.
You. The GaAs substrate 11 is a bulk crystal and has a point defect and
Includes many lattice defects such as migration. Therefore, the buffer layer 12
Operation epitaxy directly on the GaAs substrate 11 without providing
Growth of the epitaxial layer, the initial epitaxy close to the substrate
Good quality crystallinity cannot be obtained in the char layer.

For example, when the buffer layer 12 is not provided, a problem arises that hysteresis is observed in a plot (IV characteristic) of the drain current with respect to the drain voltage, and the transconductance is reduced in a low current region.
To prevent this, the buffer layer 12 is provided on the GaAs substrate 11 with a thickness of 3 to 5 μm.

In the method of growing GaAs in the vapor phase epitaxially on the buffer layer 12, AsCl ₃ is supplied as a source of As.
And a hydride method using AsH ₃ or PH ₃ . Usually, on a heated Ga source,
Hydrogen containing AsCl ₃ is flowed to cause a gas phase reaction of Ga, AsCl ₃ and H ₂ , and the chloride method is used to deposit GaAs on the substrate. When growing a mixed crystal of InGaAsP or the like, a hydride method is used.

On the buffer layer 12, an i-GaAs layer (electron transit layer) 13 with reduced impurities is formed as much as possible, and an n ⁺ -AlGaAs layer (electron supply layer) 14 is further formed thereon by epitaxial growth. In forming the i-GaAs layer 13, a molecular beam epitaxy method can be used in addition to the vapor phase epitaxy method (chloride method) similar to the formation of the buffer layer 12.

In the molecular beam epitaxy method, 10 ^-10 T
A semiconductor substrate is placed in a chamber with an ultra-high vacuum of orr or less, and the raw material is irradiated as a molecular beam from the ejection cell containing the raw material to the semiconductor substrate. When the molecular beam reaches the substrate surface, the molecules are adsorbed on the substrate surface, and the semiconductor layer grows.

In the molecular beam epitaxial method, the growth rate of the semiconductor layer is lower than in other epitaxial methods.
The growth rate when growing GaAs on an aAs substrate is 0.1 to 2 μm / h. Therefore, the molecular beam epitaxy method is disadvantageous when forming a thick semiconductor layer, but is advantageous when forming a thin film multilayer structure like an operating epitaxial layer of HEMT.

An n ⁺ -AlG layer is formed on the i-GaAs layer 13.
In order to form the aAs layer 14, the molecular beam epitaxy method or the metal organic vapor phase epitaxy method can be used. In the vapor phase epitaxial method (chloride method), a semiconductor containing Al such as Al _1-x Ga _x As cannot be grown, but Al is changed to Al (CH ₃ ) ₃ or Al (C ₂
By supplying a gas phase as H _{5) 3} organometallic,
A semiconductor layer containing Al can be formed.

Electrons generated from the n ⁺ -AlGaAs layer 14 move to the junction interface with the i-GaAs layer 13 to form a channel and serve as a current path. An n ⁺ -GaAs layer 15 is epitaxially grown on the n ⁺ -AlGaAs layer 14.

As shown in FIG. 2B, for example, the HEMT portion 01 and the resistor portion 0 are formed by performing mesa etching.
2 after the isolation with n
^{The +} -GaAs layer 15 is removed by etching. Alternatively, instead of mesa etching, a high resistance layer can be formed on the epitaxial layer by ion implantation of O ⁺ or B ⁺ . In the case of performing isolation by ion implantation, heating for annealing is not performed, so that the crystal structure of the epitaxial layer is not affected.

As shown in FIG. 2C, n
^The SiN film 17 is formed on the
Deposit about nm. An opening is formed in the SiN film 17 at a portion where the zinc diffusion resistance layer 16 is to be formed by photolithography.

As shown in FIG. 2D, using the SiN film 17 as a selective diffusion mask, an organic substance of zinc is diffused in the opening by a gas phase diffusion method to form a zinc diffusion resistance layer 16.

The liquid organometallic dimethyl zinc (DM
Z; Zn (CH ₃ ) ₂ ) or diethylzinc (DEZ;
Zn (C ₂ H ₅ ) ₂ ) is supplied to the semiconductor substrate in a gaseous state using high-purity hydrogen as a carrier gas. Zinc concentration 2
When diffused at X10 ¹⁹ cm ⁻³ and a depth of about 50 nm, a resistance having a sheet resistance of several kΩ / □ is obtained.

The diffusion rate of zinc increases as the Al composition of AlGaAs increases. In the present embodiment, GaAs
An AlGaAs layer is stacked on top of the
Zinc is selectively diffused into the As layer, and the diffusion of zinc into the GaAs layer can be suppressed.

The diffusion of zinc is performed at about 600 ° C. The heating is about the same as the crystal growth temperature (500 to 600 ° C.) of the active epitaxial layer, and can prevent the crystal structure of the active epitaxial layer, particularly the steep crystal structure at the heterojunction interface from being damaged.

The zinc diffusion resistance layer 16 is covered with an insulator, the portion where the ohmic contact is formed is etched, and p-AlG
When a metal is deposited on the aAs layer, a resistance including electrodes is obtained.

In the present invention, diffusing an n-type impurity into a GaAs substrate to form a resistance layer is more difficult than diffusing a p-type impurity. Examples of the n-type impurity for GaAs include S, Se, Si, Sn, etc., but all have a low diffusion coefficient, and the diffusion coefficient greatly varies depending on the partial pressure of As and the density of lattice defects.

As the n-type impurity introduced into GaAs, Si is frequently used. To diffuse Si, the substrate must be heated to about 850 ° C. Therefore, in a structure in which thin films are epitaxially grown and stacked as in the present invention, a problem that a crystal structure is deteriorated by heating is likely to occur.

(Embodiment 2) FIG. 3 is a sectional view of a semiconductor device according to another embodiment. As in the first embodiment, GaAs
The s substrate 21 and the buffer layer 22 are formed, and the buffer layer 2
2, an i-AlGaAs layer 28a and an n-AlGa
As layer (electron supply layer) 24a, i-AlGaAs layer 28
b, i-InGaAs layer (electron transit layer; channel) 2
3, i-AlGaAs layer 28c, n-AlGaAs layer (electron supply layer) 24b, n-GaAs layer 25a, i-A
An operation epitaxial layer composed of the lGaAs layer 28d and the n-GaAs layer 25b is formed.

The i-AlGaAs layer 28a is mainly introduced for the same purpose as the buffer layer 22. i-AlGaAs
The layers 28b and 28c are provided for the purpose of making the spatial separation between the electron supply layer and the electron transit layer more strict. Since the electron supply layer contains a high concentration of impurities, a part of the potential of the impurities affects an adjacent layer. In order to prevent scattering due to impurities and decrease in electron mobility, an extremely thin i-A is provided between the electron supply layer and the electron transit layer (channel).
The lGaAs layers 28b and 28c are formed.

The thickness of each epitaxial layer is n-AlG
The aAs layers (electron supply layers) 24a and 24b have a thickness of about 10 nm,
The i-InGaAs layer (electron transit layer; channel) 23 is about 15 nm, and the i-AlGaAs layers 28b, 28c, 2
8d is made as thin as about 1 to 3 nm (2 to 3 atomic layers).

After exposing a desired layer by etching, a SiN film 27 is deposited. An opening is provided by etching the zinc diffusion region (26a, 26b, 26c) of the SiN film 27. As in the first embodiment, zinc is diffused by a gas phase diffusion method. As shown in the second embodiment, a zinc diffusion resistance layer can be formed in a desired layer including a bulk layer (GaAs substrate 21) other than the epitaxial layer.

When the p-gate region is formed by diffusing zinc, the p-gate region can be formed in the same step as the formation of the resistance layer of the present invention. In the second embodiment, p
The gate region 26a and the zinc diffusion resistance layers 26b, 26c
Are formed in different layers in the same step.

(Embodiment 3) FIG. 4 is a sectional view of a semiconductor device according to another embodiment. Embodiment 3 is a hetero FET
And a zinc diffusion resistance layer formed on the same substrate, which is obtained by further multiplying the first embodiment.

On a GaAs substrate 31, a buffer layer 32,
n-AlGaAs layer (electron supply layer) 34a, i-AlG
aAs layer 37a, i-InGaAs layer (electron transit layer; channel) 33, i-AlGaAs layer 37b, n-AlG
aAs layer (electron supply layer) 34b, i-AlGaAs layer 3
7c, the n ⁺ -GaAs layer 35 is epitaxially grown in order to form an active epitaxial layer.

As in the first embodiment, for example, mesa etching is performed to separate the HEMT unit 01 from the resistance unit 02. After removing the n ⁺ -GaAs layer 35 of the resistance portion 02 by etching, a SiN film is deposited, and an opening is provided in a region of the SiN film where zinc is diffused by photolithography. Using the SiN film as a selective diffusion mask, zinc is vapor-phase diffused to form a p-type zinc diffusion resistance layer.

By using InGaAs for the electron transit layer, it is possible to transfer electrons at a higher speed than in the case where AlGaAs is used. The electron mobility at room temperature is
180 cm ² / Vs for AlAs and 8500 c for GaAs
m ² / Vs and InAs are about 33000 cm ² / Vs. The electron mobility in the case of a ternary mixed crystal is usually Al
GaAs is 180 to 8500 cm ² / Vs, InGaAs
s is in the range of 8500 to 33000 cm ² / Vs.

I-AlGaAs layers 37a, 37b, 37
c is the i-AlGaAs layer 28a of FIG. 3 (Embodiment 2).
As in the case of ~ c, the potential of the high-concentration impurity contained in the electron supply layer is provided for the purpose of preventing the electron traveling layer from infiltrating and scattering electrons.

The presence of the n ⁺ -GaAs layer 35 in the HEMT portion 01 facilitates ohmic contact between the source electrode 38 and the drain electrode 40. The metal which becomes the source electrode 38, the gate electrode 39, and the drain electrode 40 is deposited to form the HEMT unit 01.

(Embodiment 4) FIG. 5 is a sectional view of a semiconductor device according to Embodiment 4. Embodiment 4 is an example in which an FET including an epitaxial layer and a diffusion resistance layer are formed on the same substrate. A buffer layer 52 is laminated on a GaAs substrate 51, and an i-AlGaAs layer 53 is further formed by epitaxial growth to function as a buffer.
n-InGaAs layer (channel buried layer) 54, i-
Operational epitaxial layers of an AlGaAs layer (channel layer) 55 and an n ⁺ -GaAs layer 56 are deposited.

Metals for the source electrode 58, the gate electrode 59, and the drain electrode 60 are deposited to form an FET portion. As shown in FIG. 5, the formation of the resistive layer of the present invention can be applied to a doped channel layer in a conventional FET or the like.

According to the method of manufacturing a semiconductor device according to the embodiment of the present invention described above, a p-type impurity is vapor-phase diffused into an epitaxial substrate of a compound semiconductor, whereby a high sheet resistance can be obtained without impairing the sharpness of an epitaxial interface. Can be formed to form an MMIC.

The semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above embodiment. For example, HEM
The heterojunction used for T is formed by the above GaAs / AlGa
Instead of As or InGaAs / AlGaAs, In
It is also possible to use GaAs / AlInAs. Alternatively, the thickness of each thin film layer constituting the active epitaxial layer of the HEMT can be appropriately changed according to the design of the MMIC. In addition, various changes can be made without departing from the gist of the present invention.

[0061]

According to the semiconductor device of the present invention, high-concentration zinc is diffused as a p-type impurity into the epitaxial substrate of a compound semiconductor in a gaseous phase, so that the heterojunction interface does not lose its steepness and the high sheet thickness is maintained. A resistance layer of resistance can be obtained. According to the method for manufacturing a semiconductor device of the present invention,
An MMIC in which the FET and the resistance layer are formed on the same substrate can be configured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2 (a) to 2 (d) show Embodiment 1 of the present invention.
13 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional semiconductor device (HEMT).

[Explanation of symbols]

01 ... HEMT section, 02 ... Resistance section, 11, 21, 31,
51, 61... GaAs substrate, 12, 22, 32, 52,
62: buffer layer, 13: i-GaAs layer (electron transit layer), 23, 33, 63 ... i-InGaAs layer (electron transit layer), 14, 24a, 24b, 34a, 34b, 64
... n ⁺ -AlGaAs layer (electron supply layer), 54 ... nI
nGaAs layers, 15, 25a, 25b, 35, 56... n
⁺ -GaAs layer, 16, 26b, 26c, 36, 57a
... p-type zinc diffusion resistance layer, 26a ... p gate region, 17,
27 ... SiN film, 28a, 28b, 28c, 28d, 3
7a, 37b, 37c, 53, 55 ... i-AlGaAs
Layers, 57b ... resistance electrodes, 38, 58 ... source electrodes, 3
9, 59 ... gate electrode, 40, 60 ... drain electrode.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Wada 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (29)

[Claims] A field effect transistor having a channel layer formed on a semiconductor layer of a first conductivity type; and a field effect transistor having a first conductivity type opposite to the first conductivity type formed on at least one of the semiconductor layer and the channel layer. A semiconductor device having a resistance layer formed of a two-conductivity-type impurity diffusion layer. 2. The semiconductor device according to claim 1, wherein said semiconductor layer and said channel layer are each formed of an epitaxially grown layer of at least a group III-V compound semiconductor. 3. The semiconductor layer according to claim 2, wherein the semiconductor layer is an n-type semiconductor made of GaAs, and the resistance layer is a p-type impurity gas-phase diffusion layer.
13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein the semiconductor layer is formed of n-type AlGaAs.
3. The semiconductor device according to claim 2, wherein the resistance layer is a p-type impurity gas phase diffusion layer.
13. The semiconductor device according to claim 1. 5. The p-type impurity layer is zinc.
13. The semiconductor device according to claim 1. 6. The p-type impurity layer is made of zinc.
13. The semiconductor device according to claim 1. 7. The semiconductor device according to claim 4, wherein a resistance value of said resistor is controlled by controlling an Al composition in said AlGaAs layer and adjusting a diffusion rate of vapor-phase diffusion of zinc. 8. A field effect transistor having a channel layer formed between first and second semiconductor layers of a first conductivity type; and at least one of the first and second semiconductor layers or the channel layer. And a resistance layer comprising a second conductivity type impurity diffusion layer opposite to the first conductivity type. 9. The semiconductor device according to claim 8, wherein said semiconductor layer and said channel layer are each formed of an epitaxially grown layer of at least a group III-V compound semiconductor. 10. The semiconductor layer is an n-type semiconductor made of GaAs, and the resistance layer is a p-type impurity gas-phase diffusion layer.
13. The semiconductor device according to claim 1. 11. The semiconductor layer according to claim 9, wherein the semiconductor layer is an n-type semiconductor made of AlGaAs, and the resistance layer is a p-type impurity gas-phase diffusion layer.
13. The semiconductor device according to claim 1. 12. The semiconductor device according to claim 10, wherein said p-type impurity layer is zinc. 13. The semiconductor device according to claim 11, wherein said p-type impurity layer is zinc. 14. The semiconductor device according to claim 11, wherein a resistance value of said resistor is controlled by controlling an Al composition in said AlGaAs layer and adjusting a diffusion rate of vapor-phase diffusion of zinc. 15. A field effect transistor having a channel layer formed between first and second non-conductive semiconductor layers, and at least one of the first and second semiconductor layers or the channel layer. And a resistance layer comprising an impurity diffusion layer. 16. The semiconductor device according to claim 15, wherein said semiconductor layer and said channel layer are made of an epitaxially grown layer of at least a group III-V compound semiconductor. 17. The semiconductor device according to claim 1, wherein the semiconductor layer is an n-type semiconductor made of GaAs, and the resistance layer is a vapor-phase diffusion layer of a p-type impurity.
7. The semiconductor device according to 6. 18. The semiconductor device according to claim 1, wherein the semiconductor layer is an n-type semiconductor made of AlGaAs, and the resistance layer is a vapor-phase diffusion layer of a p-type impurity.
7. The semiconductor device according to 6. 19. The semiconductor device according to claim 17, wherein said p-type impurity layer is zinc. 20. The semiconductor device according to claim 18, wherein said p-type impurity layer is zinc. 21. The semiconductor device according to claim 18, wherein a resistance value of said resistor is controlled by controlling an Al composition in said AlGaAs layer and adjusting a diffusion rate of vapor-phase diffusion of zinc. 22. A method for manufacturing a semiconductor device comprising a field effect transistor having a channel layer formed on a semiconductor layer of a first conductivity type and a resistance layer, wherein at least one of the semiconductor layer and the channel layer is provided. For a predetermined region of the layer, a second conductive type opposite to the first conductive type is used.
A method for manufacturing a semiconductor device, wherein the impurity of the conductivity type is diffused in the vapor phase to form the resistance layer. 23. The semiconductor layer of the first conductivity type and the channel layer are formed by epitaxially growing at least a group III-V compound semiconductor.
The manufacturing method of the semiconductor device described in the above. 24. The semiconductor device according to claim 2, wherein the semiconductor layer is an n-type semiconductor made of GaAs, and the resistance layer is a vapor-phase diffusion layer of a p-type impurity.
4. The method for manufacturing a semiconductor device according to item 3. 25. The semiconductor device according to claim 2, wherein the semiconductor layer is an n-type semiconductor made of AlGaAs, and the resistance layer is a vapor-phase diffusion layer of a p-type impurity.
4. The method for manufacturing a semiconductor device according to item 3. 26. The method according to claim 24, wherein said p-type impurity layer is zinc. 27. The method according to claim 25, wherein said p-type impurity layer is zinc. 28. The method of manufacturing a semiconductor device according to claim 25, wherein the resistance value of said resistor is controlled by controlling the Al composition in said AlGaAs layer and adjusting a diffusion rate at which zinc is vapor-phase diffused. 29. A method for manufacturing a semiconductor device comprising a resistance layer and a field effect transistor having a channel layer formed between a first and a second semiconductor layer of a non-conductivity type, comprising the steps of: A method of manufacturing a semiconductor device, wherein an impurity is vapor-phase diffused into at least a predetermined region of any one of the layers to form the resistance layer.